drivers/gpu/drm/i915/i915_pmu.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #ifndef __I915_PMU_H__
  25 #define __I915_PMU_H__
  26
  27 enum {
  28         __I915_SAMPLE_FREQ_ACT = 0,
  29         __I915_SAMPLE_FREQ_REQ,
  30         __I915_SAMPLE_RC6,
  31         __I915_SAMPLE_RC6_ESTIMATED,
  32         __I915_NUM_PMU_SAMPLERS
  33 };
  34
  35 /**
  36  * How many different events we track in the global PMU mask.
  37  *
  38  * It is also used to know to needed number of event reference counters.
  39  */
  40 #define I915_PMU_MASK_BITS \
  41         ((1 << I915_PMU_SAMPLE_BITS) + \
  42          (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
  43
  44 struct i915_pmu_sample {
  45         u64 cur;
  46 };
  47
  48 struct i915_pmu {
  49         /**
  50          * @node: List node for CPU hotplug handling.
  51          */
  52         struct hlist_node node;
  53         /**
  54          * @base: PMU base.
  55          */
  56         struct pmu base;
  57         /**
  58          * @lock: Lock protecting enable mask and ref count handling.
  59          */
  60         spinlock_t lock;
  61         /**
  62          * @timer: Timer for internal i915 PMU sampling.
  63          */
  64         struct hrtimer timer;
  65         /**
  66          * @enable: Bitmask of all currently enabled events.
  67          *
  68          * Bits are derived from uAPI event numbers in a way that low 16 bits
  69          * correspond to engine event _sample_ _type_ (I915_SAMPLE_QUEUED is
  70          * bit 0), and higher bits correspond to other events (for instance
  71          * I915_PMU_ACTUAL_FREQUENCY is bit 16 etc).
  72          *
  73          * In other words, low 16 bits are not per engine but per engine
  74          * sampler type, while the upper bits are directly mapped to other
  75          * event types.
  76          */
  77         u64 enable;
  78         /**
  79          * @enable_count: Reference counts for the enabled events.
  80          *
  81          * Array indices are mapped in the same way as bits in the @enable field
  82          * and they are used to control sampling on/off when multiple clients
  83          * are using the PMU API.
  84          */
  85         unsigned int enable_count[I915_PMU_MASK_BITS];
  86         /**
  87          * @timer_enabled: Should the internal sampling timer be running.
  88          */
  89         bool timer_enabled;
  90         /**
  91          * @sample: Current and previous (raw) counters for sampling events.
  92          *
  93          * These counters are updated from the i915 PMU sampling timer.
  94          *
  95          * Only global counters are held here, while the per-engine ones are in
  96          * struct intel_engine_cs.
  97          */
  98         struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
  99         /**
 100          * @suspended_jiffies_last: Cached suspend time from PM core.
 101          */
 102         unsigned long suspended_jiffies_last;
 103 };
 104
 105 #ifdef CONFIG_PERF_EVENTS
 106 void i915_pmu_register(struct drm_i915_private *i915);
 107 void i915_pmu_unregister(struct drm_i915_private *i915);
 108 void i915_pmu_gt_parked(struct drm_i915_private *i915);
 109 void i915_pmu_gt_unparked(struct drm_i915_private *i915);
 110 #else
 111 static inline void i915_pmu_register(struct drm_i915_private *i915) {}
 112 static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
 113 static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
 114 static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
 115 #endif
 116
 117 #endif