drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  */
  36
  37 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
  38 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  39
  40 #define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin"
  41 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 6)
  42
  43 #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin"
  44 MODULE_FIRMWARE(I915_CSR_KBL);
  45 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  46
  47 #define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin"
  48 MODULE_FIRMWARE(I915_CSR_SKL);
  49 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 27)
  50
  51 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
  52 MODULE_FIRMWARE(I915_CSR_BXT);
  53 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  54
  55
  56 #define CSR_MAX_FW_SIZE                 0x2FFF
  57 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  58
  59 struct intel_css_header {
  60         /* 0x09 for DMC */
  61         uint32_t module_type;
  62
  63         /* Includes the DMC specific header in dwords */
  64         uint32_t header_len;
  65
  66         /* always value would be 0x10000 */
  67         uint32_t header_ver;
  68
  69         /* Not used */
  70         uint32_t module_id;
  71
  72         /* Not used */
  73         uint32_t module_vendor;
  74
  75         /* in YYYYMMDD format */
  76         uint32_t date;
  77
  78         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  79         uint32_t size;
  80
  81         /* Not used */
  82         uint32_t key_size;
  83
  84         /* Not used */
  85         uint32_t modulus_size;
  86
  87         /* Not used */
  88         uint32_t exponent_size;
  89
  90         /* Not used */
  91         uint32_t reserved1[12];
  92
  93         /* Major Minor */
  94         uint32_t version;
  95
  96         /* Not used */
  97         uint32_t reserved2[8];
  98
  99         /* Not used */
 100         uint32_t kernel_header_info;
 101 } __packed;
 102
 103 struct intel_fw_info {
 104         uint16_t reserved1;
 105
 106         /* Stepping (A, B, C, ..., *). * is a wildcard */
 107         char stepping;
 108
 109         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 110         char substepping;
 111
 112         uint32_t offset;
 113         uint32_t reserved2;
 114 } __packed;
 115
 116 struct intel_package_header {
 117         /* DMC container header length in dwords */
 118         unsigned char header_len;
 119
 120         /* always value would be 0x01 */
 121         unsigned char header_ver;
 122
 123         unsigned char reserved[10];
 124
 125         /* Number of valid entries in the FWInfo array below */
 126         uint32_t num_entries;
 127
 128         struct intel_fw_info fw_info[20];
 129 } __packed;
 130
 131 struct intel_dmc_header {
 132         /* always value would be 0x40403E3E */
 133         uint32_t signature;
 134
 135         /* DMC binary header length */
 136         unsigned char header_len;
 137
 138         /* 0x01 */
 139         unsigned char header_ver;
 140
 141         /* Reserved */
 142         uint16_t dmcc_ver;
 143
 144         /* Major, Minor */
 145         uint32_t        project;
 146
 147         /* Firmware program size (excluding header) in dwords */
 148         uint32_t        fw_size;
 149
 150         /* Major Minor version */
 151         uint32_t fw_version;
 152
 153         /* Number of valid MMIO cycles present. */
 154         uint32_t mmio_count;
 155
 156         /* MMIO address */
 157         uint32_t mmioaddr[8];
 158
 159         /* MMIO data */
 160         uint32_t mmiodata[8];
 161
 162         /* FW filename  */
 163         unsigned char dfile[32];
 164
 165         uint32_t reserved1[2];
 166 } __packed;
 167
 168 struct stepping_info {
 169         char stepping;
 170         char substepping;
 171 };
 172
 173 static const struct stepping_info skl_stepping_info[] = {
 174         {'A', '0'}, {'B', '0'}, {'C', '0'},
 175         {'D', '0'}, {'E', '0'}, {'F', '0'},
 176         {'G', '0'}, {'H', '0'}, {'I', '0'},
 177         {'J', '0'}, {'K', '0'}
 178 };
 179
 180 static const struct stepping_info bxt_stepping_info[] = {
 181         {'A', '0'}, {'A', '1'}, {'A', '2'},
 182         {'B', '0'}, {'B', '1'}, {'B', '2'}
 183 };
 184
 185 static const struct stepping_info no_stepping_info = { '*', '*' };
 186
 187 static const struct stepping_info *
 188 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 189 {
 190         const struct stepping_info *si;
 191         unsigned int size;
 192
 193         if (IS_SKYLAKE(dev_priv)) {
 194                 size = ARRAY_SIZE(skl_stepping_info);
 195                 si = skl_stepping_info;
 196         } else if (IS_BROXTON(dev_priv)) {
 197                 size = ARRAY_SIZE(bxt_stepping_info);
 198                 si = bxt_stepping_info;
 199         } else {
 200                 size = 0;
 201                 si = NULL;
 202         }
 203
 204         if (INTEL_REVID(dev_priv) < size)
 205                 return si + INTEL_REVID(dev_priv);
 206
 207         return &no_stepping_info;
 208 }
 209
 210 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 211 {
 212         uint32_t val, mask;
 213
 214         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 215
 216         if (IS_GEN9_LP(dev_priv))
 217                 mask |= DC_STATE_DEBUG_MASK_CORES;
 218
 219         /* The below bit doesn't need to be cleared ever afterwards */
 220         val = I915_READ(DC_STATE_DEBUG);
 221         if ((val & mask) != mask) {
 222                 val |= mask;
 223                 I915_WRITE(DC_STATE_DEBUG, val);
 224                 POSTING_READ(DC_STATE_DEBUG);
 225         }
 226 }
 227
 228 /**
 229  * intel_csr_load_program() - write the firmware from memory to register.
 230  * @dev_priv: i915 drm device.
 231  *
 232  * CSR firmware is read from a .bin file and kept in internal memory one time.
 233  * Everytime display comes back from low power state this function is called to
 234  * copy the firmware from internal memory to registers.
 235  */
 236 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 237 {
 238         u32 *payload = dev_priv->csr.dmc_payload;
 239         uint32_t i, fw_size;
 240
 241         if (!HAS_CSR(dev_priv)) {
 242                 DRM_ERROR("No CSR support available for this platform\n");
 243                 return;
 244         }
 245
 246         if (!dev_priv->csr.dmc_payload) {
 247                 DRM_ERROR("Tried to program CSR with empty payload\n");
 248                 return;
 249         }
 250
 251         fw_size = dev_priv->csr.dmc_fw_size;
 252         assert_rpm_wakelock_held(dev_priv);
 253
 254         preempt_disable();
 255
 256         for (i = 0; i < fw_size; i++)
 257                 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
 258
 259         preempt_enable();
 260
 261         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 262                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 263                            dev_priv->csr.mmiodata[i]);
 264         }
 265
 266         dev_priv->csr.dc_state = 0;
 267
 268         gen9_set_dc_state_debugmask(dev_priv);
 269 }
 270
 271 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 272                               const struct firmware *fw)
 273 {
 274         struct intel_css_header *css_header;
 275         struct intel_package_header *package_header;
 276         struct intel_dmc_header *dmc_header;
 277         struct intel_csr *csr = &dev_priv->csr;
 278         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 279         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 280         uint32_t i;
 281         uint32_t *dmc_payload;
 282         uint32_t required_version;
 283
 284         if (!fw)
 285                 return NULL;
 286
 287         /* Extract CSS Header information*/
 288         css_header = (struct intel_css_header *)fw->data;
 289         if (sizeof(struct intel_css_header) !=
 290             (css_header->header_len * 4)) {
 291                 DRM_ERROR("DMC firmware has wrong CSS header length "
 292                           "(%u bytes)\n",
 293                           (css_header->header_len * 4));
 294                 return NULL;
 295         }
 296
 297         csr->version = css_header->version;
 298
 299         if (IS_CANNONLAKE(dev_priv)) {
 300                 required_version = CNL_CSR_VERSION_REQUIRED;
 301         } else if (IS_GEMINILAKE(dev_priv)) {
 302                 required_version = GLK_CSR_VERSION_REQUIRED;
 303         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 304                 required_version = KBL_CSR_VERSION_REQUIRED;
 305         } else if (IS_SKYLAKE(dev_priv)) {
 306                 required_version = SKL_CSR_VERSION_REQUIRED;
 307         } else if (IS_BROXTON(dev_priv)) {
 308                 required_version = BXT_CSR_VERSION_REQUIRED;
 309         } else {
 310                 MISSING_CASE(INTEL_REVID(dev_priv));
 311                 required_version = 0;
 312         }
 313
 314         if (csr->version != required_version) {
 315                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 316                          " please use v%u.%u\n",
 317                          CSR_VERSION_MAJOR(csr->version),
 318                          CSR_VERSION_MINOR(csr->version),
 319                          CSR_VERSION_MAJOR(required_version),
 320                          CSR_VERSION_MINOR(required_version));
 321                 return NULL;
 322         }
 323
 324         readcount += sizeof(struct intel_css_header);
 325
 326         /* Extract Package Header information*/
 327         package_header = (struct intel_package_header *)
 328                 &fw->data[readcount];
 329         if (sizeof(struct intel_package_header) !=
 330             (package_header->header_len * 4)) {
 331                 DRM_ERROR("DMC firmware has wrong package header length "
 332                           "(%u bytes)\n",
 333                           (package_header->header_len * 4));
 334                 return NULL;
 335         }
 336         readcount += sizeof(struct intel_package_header);
 337
 338         /* Search for dmc_offset to find firware binary. */
 339         for (i = 0; i < package_header->num_entries; i++) {
 340                 if (package_header->fw_info[i].substepping == '*' &&
 341                     si->stepping == package_header->fw_info[i].stepping) {
 342                         dmc_offset = package_header->fw_info[i].offset;
 343                         break;
 344                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 345                            si->substepping == package_header->fw_info[i].substepping) {
 346                         dmc_offset = package_header->fw_info[i].offset;
 347                         break;
 348                 } else if (package_header->fw_info[i].stepping == '*' &&
 349                            package_header->fw_info[i].substepping == '*')
 350                         dmc_offset = package_header->fw_info[i].offset;
 351         }
 352         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 353                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 354                           si->stepping);
 355                 return NULL;
 356         }
 357         readcount += dmc_offset;
 358
 359         /* Extract dmc_header information. */
 360         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 361         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 362                 DRM_ERROR("DMC firmware has wrong dmc header length "
 363                           "(%u bytes)\n",
 364                           (dmc_header->header_len));
 365                 return NULL;
 366         }
 367         readcount += sizeof(struct intel_dmc_header);
 368
 369         /* Cache the dmc header info. */
 370         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 371                 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
 372                           dmc_header->mmio_count);
 373                 return NULL;
 374         }
 375         csr->mmio_count = dmc_header->mmio_count;
 376         for (i = 0; i < dmc_header->mmio_count; i++) {
 377                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 378                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 379                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 380                                   dmc_header->mmioaddr[i]);
 381                         return NULL;
 382                 }
 383                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 384                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 385         }
 386
 387         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 388         nbytes = dmc_header->fw_size * 4;
 389         if (nbytes > CSR_MAX_FW_SIZE) {
 390                 DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
 391                 return NULL;
 392         }
 393         csr->dmc_fw_size = dmc_header->fw_size;
 394
 395         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 396         if (!dmc_payload) {
 397                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 398                 return NULL;
 399         }
 400
 401         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 402 }
 403
 404 static void csr_load_work_fn(struct work_struct *work)
 405 {
 406         struct drm_i915_private *dev_priv;
 407         struct intel_csr *csr;
 408         const struct firmware *fw = NULL;
 409
 410         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 411         csr = &dev_priv->csr;
 412
 413         request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
 414         if (fw)
 415                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 416
 417         if (dev_priv->csr.dmc_payload) {
 418                 intel_csr_load_program(dev_priv);
 419
 420                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 421
 422                 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
 423                          dev_priv->csr.fw_path,
 424                          CSR_VERSION_MAJOR(csr->version),
 425                          CSR_VERSION_MINOR(csr->version));
 426         } else {
 427                 dev_notice(dev_priv->drm.dev,
 428                            "Failed to load DMC firmware %s."
 429                            " Disabling runtime power management.\n",
 430                            csr->fw_path);
 431                 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
 432                            INTEL_UC_FIRMWARE_URL);
 433         }
 434
 435         release_firmware(fw);
 436 }
 437
 438 /**
 439  * intel_csr_ucode_init() - initialize the firmware loading.
 440  * @dev_priv: i915 drm device.
 441  *
 442  * This function is called at the time of loading the display driver to read
 443  * firmware from a .bin file and copied into a internal memory.
 444  */
 445 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 446 {
 447         struct intel_csr *csr = &dev_priv->csr;
 448
 449         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 450
 451         if (!HAS_CSR(dev_priv))
 452                 return;
 453
 454         if (IS_CANNONLAKE(dev_priv))
 455                 csr->fw_path = I915_CSR_CNL;
 456         else if (IS_GEMINILAKE(dev_priv))
 457                 csr->fw_path = I915_CSR_GLK;
 458         else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 459                 csr->fw_path = I915_CSR_KBL;
 460         else if (IS_SKYLAKE(dev_priv))
 461                 csr->fw_path = I915_CSR_SKL;
 462         else if (IS_BROXTON(dev_priv))
 463                 csr->fw_path = I915_CSR_BXT;
 464         else {
 465                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 466                 return;
 467         }
 468
 469         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 470
 471         /*
 472          * Obtain a runtime pm reference, until CSR is loaded,
 473          * to avoid entering runtime-suspend.
 474          */
 475         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 476
 477         schedule_work(&dev_priv->csr.work);
 478 }
 479
 480 /**
 481  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 482  * @dev_priv: i915 drm device
 483  *
 484  * Prepare the DMC firmware before entering system suspend. This includes
 485  * flushing pending work items and releasing any resources acquired during
 486  * init.
 487  */
 488 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 489 {
 490         if (!HAS_CSR(dev_priv))
 491                 return;
 492
 493         flush_work(&dev_priv->csr.work);
 494
 495         /* Drop the reference held in case DMC isn't loaded. */
 496         if (!dev_priv->csr.dmc_payload)
 497                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 498 }
 499
 500 /**
 501  * intel_csr_ucode_resume() - init CSR firmware during system resume
 502  * @dev_priv: i915 drm device
 503  *
 504  * Reinitialize the DMC firmware during system resume, reacquiring any
 505  * resources released in intel_csr_ucode_suspend().
 506  */
 507 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 508 {
 509         if (!HAS_CSR(dev_priv))
 510                 return;
 511
 512         /*
 513          * Reacquire the reference to keep RPM disabled in case DMC isn't
 514          * loaded.
 515          */
 516         if (!dev_priv->csr.dmc_payload)
 517                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 518 }
 519
 520 /**
 521  * intel_csr_ucode_fini() - unload the CSR firmware.
 522  * @dev_priv: i915 drm device.
 523  *
 524  * Firmmware unloading includes freeing the internal memory and reset the
 525  * firmware loading status.
 526  */
 527 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 528 {
 529         if (!HAS_CSR(dev_priv))
 530                 return;
 531
 532         intel_csr_ucode_suspend(dev_priv);
 533
 534         kfree(dev_priv->csr.dmc_payload);
 535 }