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bpf: Prevent memory disambiguation attack
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_ddi.c
blob6aff9d096e13d08addb7b0bdf143aa9e73c2223b
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 };
36
37 static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48 };
49
50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
64 };
65
66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
76 };
77
78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
92 };
93
94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
104 };
105
106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
116 };
117
118 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
128 };
129
130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
142 };
143
144 /* Skylake H and S */
145 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x000000DF, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
155 };
156
157 /* Skylake U */
158 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
159 { 0x0000201B, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x1 },
162 { 0x80009010, 0x000000C0, 0x1 },
163 { 0x0000201B, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
166 { 0x00002016, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x1 },
168 };
169
170 /* Skylake Y */
171 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
174 { 0x80007011, 0x000000CD, 0x3 },
175 { 0x80009010, 0x000000C0, 0x3 },
176 { 0x00000018, 0x0000009D, 0x0 },
177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
179 { 0x00000018, 0x00000088, 0x0 },
180 { 0x80005012, 0x000000C0, 0x3 },
181 };
182
183 /* Kabylake H and S */
184 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194 };
195
196 /* Kabylake U */
197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207 };
208
209 /* Kabylake Y */
210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220 };
221
222 /*
223 * Skylake/Kabylake H and S
224 * eDP 1.4 low vswing translation parameters
225 */
226 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237 };
238
239 /*
240 * Skylake/Kabylake U
241 * eDP 1.4 low vswing translation parameters
242 */
243 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
254 };
255
256 /*
257 * Skylake/Kabylake Y
258 * eDP 1.4 low vswing translation parameters
259 */
260 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271 };
272
273 /* Skylake/Kabylake U, H and S */
274 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
281 { 0x80006012, 0x000000CD, 0x1 },
282 { 0x00000018, 0x000000DF, 0x0 },
283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
286 };
287
288 /* Skylake/Kabylake Y */
289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
292 { 0x80007011, 0x000000CB, 0x3 },
293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
296 { 0x80006013, 0x000000C0, 0x3 },
297 { 0x00000018, 0x0000008A, 0x0 },
298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
301 };
302
303 struct bxt_ddi_buf_trans {
304 u8 margin; /* swing value */
305 u8 scale; /* scale value */
306 u8 enable; /* scale enable */
307 u8 deemphasis;
308 };
309
310 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
311 /* Idx NT mV diff db */
312 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
313 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
314 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
315 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
316 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
317 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
318 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
319 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
320 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
321 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
322 };
323
324 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
325 /* Idx NT mV diff db */
326 { 26, 0, 0, 128, }, /* 0: 200 0 */
327 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
328 { 48, 0, 0, 96, }, /* 2: 200 4 */
329 { 54, 0, 0, 69, }, /* 3: 200 6 */
330 { 32, 0, 0, 128, }, /* 4: 250 0 */
331 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
332 { 54, 0, 0, 85, }, /* 6: 250 4 */
333 { 43, 0, 0, 128, }, /* 7: 300 0 */
334 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
335 { 48, 0, 0, 128, }, /* 9: 300 0 */
336 };
337
338 /* BSpec has 2 recommended values - entries 0 and 8.
339 * Using the entry with higher vswing.
340 */
341 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
342 /* Idx NT mV diff db */
343 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
344 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
345 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
346 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
347 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
348 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
349 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
350 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
351 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
352 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
353 };
354
355 struct cnl_ddi_buf_trans {
356 u8 dw2_swing_sel;
357 u8 dw7_n_scalar;
358 u8 dw4_cursor_coeff;
359 u8 dw4_post_cursor_2;
360 u8 dw4_post_cursor_1;
361 };
362
363 /* Voltage Swing Programming for VccIO 0.85V for DP */
364 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
365 /* NT mV Trans mV db */
366 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
367 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
368 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
369 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
370 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
371 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
372 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
373 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
374 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
375 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
376 };
377
378 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
379 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
380 /* NT mV Trans mV db */
381 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
382 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
383 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
384 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
385 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
386 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
387 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
388 };
389
390 /* Voltage Swing Programming for VccIO 0.85V for eDP */
391 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
392 /* NT mV Trans mV db */
393 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
394 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
395 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
396 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
397 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
398 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
399 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
400 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
401 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
402 };
403
404 /* Voltage Swing Programming for VccIO 0.95V for DP */
405 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
406 /* NT mV Trans mV db */
407 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
408 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
409 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
410 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
411 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
412 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
413 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
414 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
415 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
416 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
417 };
418
419 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
420 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
421 /* NT mV Trans mV db */
422 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
423 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
424 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
425 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
426 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
427 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
428 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
429 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
430 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
431 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
432 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
433 };
434
435 /* Voltage Swing Programming for VccIO 0.95V for eDP */
436 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
437 /* NT mV Trans mV db */
438 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
439 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
440 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
441 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
442 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
443 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
444 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
445 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
446 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
447 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
448 };
449
450 /* Voltage Swing Programming for VccIO 1.05V for DP */
451 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
452 /* NT mV Trans mV db */
453 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
454 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
455 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
456 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
457 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
458 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
459 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
460 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
461 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
462 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
463 };
464
465 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
466 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
467 /* NT mV Trans mV db */
468 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
469 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
470 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
471 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
472 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
473 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
474 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
475 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
476 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
477 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
478 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
479 };
480
481 /* Voltage Swing Programming for VccIO 1.05V for eDP */
482 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
483 /* NT mV Trans mV db */
484 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
485 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
486 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
487 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
488 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
489 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
490 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
491 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
492 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
493 };
494
495 static const struct ddi_buf_trans *
496 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
497 {
498 if (dev_priv->vbt.edp.low_vswing) {
499 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
500 return bdw_ddi_translations_edp;
501 } else {
502 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
503 return bdw_ddi_translations_dp;
504 }
505 }
506
507 static const struct ddi_buf_trans *
508 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
509 {
510 if (IS_SKL_ULX(dev_priv)) {
511 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
512 return skl_y_ddi_translations_dp;
513 } else if (IS_SKL_ULT(dev_priv)) {
514 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
515 return skl_u_ddi_translations_dp;
516 } else {
517 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
518 return skl_ddi_translations_dp;
519 }
520 }
521
522 static const struct ddi_buf_trans *
523 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
524 {
525 if (IS_KBL_ULX(dev_priv)) {
526 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
527 return kbl_y_ddi_translations_dp;
528 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
529 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
530 return kbl_u_ddi_translations_dp;
531 } else {
532 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
533 return kbl_ddi_translations_dp;
534 }
535 }
536
537 static const struct ddi_buf_trans *
538 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
539 {
540 if (dev_priv->vbt.edp.low_vswing) {
541 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
542 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
543 return skl_y_ddi_translations_edp;
544 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
545 IS_CFL_ULT(dev_priv)) {
546 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
547 return skl_u_ddi_translations_edp;
548 } else {
549 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
550 return skl_ddi_translations_edp;
551 }
552 }
553
554 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
555 return kbl_get_buf_trans_dp(dev_priv, n_entries);
556 else
557 return skl_get_buf_trans_dp(dev_priv, n_entries);
558 }
559
560 static const struct ddi_buf_trans *
561 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
562 {
563 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
564 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
565 return skl_y_ddi_translations_hdmi;
566 } else {
567 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
568 return skl_ddi_translations_hdmi;
569 }
570 }
571
572 static int skl_buf_trans_num_entries(enum port port, int n_entries)
573 {
574 /* Only DDIA and DDIE can select the 10th register with DP */
575 if (port == PORT_A || port == PORT_E)
576 return min(n_entries, 10);
577 else
578 return min(n_entries, 9);
579 }
580
581 static const struct ddi_buf_trans *
582 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
583 enum port port, int *n_entries)
584 {
585 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
586 const struct ddi_buf_trans *ddi_translations =
587 kbl_get_buf_trans_dp(dev_priv, n_entries);
588 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
589 return ddi_translations;
590 } else if (IS_SKYLAKE(dev_priv)) {
591 const struct ddi_buf_trans *ddi_translations =
592 skl_get_buf_trans_dp(dev_priv, n_entries);
593 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
594 return ddi_translations;
595 } else if (IS_BROADWELL(dev_priv)) {
596 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
597 return bdw_ddi_translations_dp;
598 } else if (IS_HASWELL(dev_priv)) {
599 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
600 return hsw_ddi_translations_dp;
601 }
602
603 *n_entries = 0;
604 return NULL;
605 }
606
607 static const struct ddi_buf_trans *
608 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
609 enum port port, int *n_entries)
610 {
611 if (IS_GEN9_BC(dev_priv)) {
612 const struct ddi_buf_trans *ddi_translations =
613 skl_get_buf_trans_edp(dev_priv, n_entries);
614 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
615 return ddi_translations;
616 } else if (IS_BROADWELL(dev_priv)) {
617 return bdw_get_buf_trans_edp(dev_priv, n_entries);
618 } else if (IS_HASWELL(dev_priv)) {
619 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
620 return hsw_ddi_translations_dp;
621 }
622
623 *n_entries = 0;
624 return NULL;
625 }
626
627 static const struct ddi_buf_trans *
628 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
629 int *n_entries)
630 {
631 if (IS_BROADWELL(dev_priv)) {
632 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
633 return bdw_ddi_translations_fdi;
634 } else if (IS_HASWELL(dev_priv)) {
635 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
636 return hsw_ddi_translations_fdi;
637 }
638
639 *n_entries = 0;
640 return NULL;
641 }
642
643 static const struct ddi_buf_trans *
644 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
645 int *n_entries)
646 {
647 if (IS_GEN9_BC(dev_priv)) {
648 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
649 } else if (IS_BROADWELL(dev_priv)) {
650 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
651 return bdw_ddi_translations_hdmi;
652 } else if (IS_HASWELL(dev_priv)) {
653 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
654 return hsw_ddi_translations_hdmi;
655 }
656
657 *n_entries = 0;
658 return NULL;
659 }
660
661 static const struct bxt_ddi_buf_trans *
662 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
663 {
664 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
665 return bxt_ddi_translations_dp;
666 }
667
668 static const struct bxt_ddi_buf_trans *
669 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
670 {
671 if (dev_priv->vbt.edp.low_vswing) {
672 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
673 return bxt_ddi_translations_edp;
674 }
675
676 return bxt_get_buf_trans_dp(dev_priv, n_entries);
677 }
678
679 static const struct bxt_ddi_buf_trans *
680 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
681 {
682 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
683 return bxt_ddi_translations_hdmi;
684 }
685
686 static const struct cnl_ddi_buf_trans *
687 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
688 {
689 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
690
691 if (voltage == VOLTAGE_INFO_0_85V) {
692 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
693 return cnl_ddi_translations_hdmi_0_85V;
694 } else if (voltage == VOLTAGE_INFO_0_95V) {
695 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
696 return cnl_ddi_translations_hdmi_0_95V;
697 } else if (voltage == VOLTAGE_INFO_1_05V) {
698 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
699 return cnl_ddi_translations_hdmi_1_05V;
700 } else {
701 *n_entries = 1; /* shut up gcc */
702 MISSING_CASE(voltage);
703 }
704 return NULL;
705 }
706
707 static const struct cnl_ddi_buf_trans *
708 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
709 {
710 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
711
712 if (voltage == VOLTAGE_INFO_0_85V) {
713 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
714 return cnl_ddi_translations_dp_0_85V;
715 } else if (voltage == VOLTAGE_INFO_0_95V) {
716 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
717 return cnl_ddi_translations_dp_0_95V;
718 } else if (voltage == VOLTAGE_INFO_1_05V) {
719 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
720 return cnl_ddi_translations_dp_1_05V;
721 } else {
722 *n_entries = 1; /* shut up gcc */
723 MISSING_CASE(voltage);
724 }
725 return NULL;
726 }
727
728 static const struct cnl_ddi_buf_trans *
729 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
730 {
731 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
732
733 if (dev_priv->vbt.edp.low_vswing) {
734 if (voltage == VOLTAGE_INFO_0_85V) {
735 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
736 return cnl_ddi_translations_edp_0_85V;
737 } else if (voltage == VOLTAGE_INFO_0_95V) {
738 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
739 return cnl_ddi_translations_edp_0_95V;
740 } else if (voltage == VOLTAGE_INFO_1_05V) {
741 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
742 return cnl_ddi_translations_edp_1_05V;
743 } else {
744 *n_entries = 1; /* shut up gcc */
745 MISSING_CASE(voltage);
746 }
747 return NULL;
748 } else {
749 return cnl_get_buf_trans_dp(dev_priv, n_entries);
750 }
751 }
752
753 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
754 {
755 int n_entries, level, default_entry;
756
757 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
758
759 if (IS_CANNONLAKE(dev_priv)) {
760 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
761 default_entry = n_entries - 1;
762 } else if (IS_GEN9_LP(dev_priv)) {
763 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
764 default_entry = n_entries - 1;
765 } else if (IS_GEN9_BC(dev_priv)) {
766 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
767 default_entry = 8;
768 } else if (IS_BROADWELL(dev_priv)) {
769 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
770 default_entry = 7;
771 } else if (IS_HASWELL(dev_priv)) {
772 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
773 default_entry = 6;
774 } else {
775 WARN(1, "ddi translation table missing\n");
776 return 0;
777 }
778
779 /* Choose a good default if VBT is badly populated */
780 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
781 level = default_entry;
782
783 if (WARN_ON_ONCE(n_entries == 0))
784 return 0;
785 if (WARN_ON_ONCE(level >= n_entries))
786 level = n_entries - 1;
787
788 return level;
789 }
790
791 /*
792 * Starting with Haswell, DDI port buffers must be programmed with correct
793 * values in advance. This function programs the correct values for
794 * DP/eDP/FDI use cases.
795 */
796 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
797 const struct intel_crtc_state *crtc_state)
798 {
799 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
800 u32 iboost_bit = 0;
801 int i, n_entries;
802 enum port port = encoder->port;
803 const struct ddi_buf_trans *ddi_translations;
804
805 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
806 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
807 &n_entries);
808 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
809 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
810 &n_entries);
811 else
812 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
813 &n_entries);
814
815 /* If we're boosting the current, set bit 31 of trans1 */
816 if (IS_GEN9_BC(dev_priv) &&
817 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
818 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
819
820 for (i = 0; i < n_entries; i++) {
821 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
822 ddi_translations[i].trans1 | iboost_bit);
823 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
824 ddi_translations[i].trans2);
825 }
826 }
827
828 /*
829 * Starting with Haswell, DDI port buffers must be programmed with correct
830 * values in advance. This function programs the correct values for
831 * HDMI/DVI use cases.
832 */
833 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
834 int level)
835 {
836 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
837 u32 iboost_bit = 0;
838 int n_entries;
839 enum port port = encoder->port;
840 const struct ddi_buf_trans *ddi_translations;
841
842 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
843
844 if (WARN_ON_ONCE(!ddi_translations))
845 return;
846 if (WARN_ON_ONCE(level >= n_entries))
847 level = n_entries - 1;
848
849 /* If we're boosting the current, set bit 31 of trans1 */
850 if (IS_GEN9_BC(dev_priv) &&
851 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
852 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
853
854 /* Entry 9 is for HDMI: */
855 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
856 ddi_translations[level].trans1 | iboost_bit);
857 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
858 ddi_translations[level].trans2);
859 }
860
861 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
862 enum port port)
863 {
864 i915_reg_t reg = DDI_BUF_CTL(port);
865 int i;
866
867 for (i = 0; i < 16; i++) {
868 udelay(1);
869 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
870 return;
871 }
872 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
873 }
874
875 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
876 {
877 switch (pll->id) {
878 case DPLL_ID_WRPLL1:
879 return PORT_CLK_SEL_WRPLL1;
880 case DPLL_ID_WRPLL2:
881 return PORT_CLK_SEL_WRPLL2;
882 case DPLL_ID_SPLL:
883 return PORT_CLK_SEL_SPLL;
884 case DPLL_ID_LCPLL_810:
885 return PORT_CLK_SEL_LCPLL_810;
886 case DPLL_ID_LCPLL_1350:
887 return PORT_CLK_SEL_LCPLL_1350;
888 case DPLL_ID_LCPLL_2700:
889 return PORT_CLK_SEL_LCPLL_2700;
890 default:
891 MISSING_CASE(pll->id);
892 return PORT_CLK_SEL_NONE;
893 }
894 }
895
896 /* Starting with Haswell, different DDI ports can work in FDI mode for
897 * connection to the PCH-located connectors. For this, it is necessary to train
898 * both the DDI port and PCH receiver for the desired DDI buffer settings.
899 *
900 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
901 * please note that when FDI mode is active on DDI E, it shares 2 lines with
902 * DDI A (which is used for eDP)
903 */
904
905 void hsw_fdi_link_train(struct intel_crtc *crtc,
906 const struct intel_crtc_state *crtc_state)
907 {
908 struct drm_device *dev = crtc->base.dev;
909 struct drm_i915_private *dev_priv = to_i915(dev);
910 struct intel_encoder *encoder;
911 u32 temp, i, rx_ctl_val, ddi_pll_sel;
912
913 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
914 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
915 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
916 }
917
918 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
919 * mode set "sequence for CRT port" document:
920 * - TP1 to TP2 time with the default value
921 * - FDI delay to 90h
922 *
923 * WaFDIAutoLinkSetTimingOverrride:hsw
924 */
925 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
926 FDI_RX_PWRDN_LANE0_VAL(2) |
927 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
928
929 /* Enable the PCH Receiver FDI PLL */
930 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
931 FDI_RX_PLL_ENABLE |
932 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
933 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
934 POSTING_READ(FDI_RX_CTL(PIPE_A));
935 udelay(220);
936
937 /* Switch from Rawclk to PCDclk */
938 rx_ctl_val |= FDI_PCDCLK;
939 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
940
941 /* Configure Port Clock Select */
942 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
943 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
944 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
945
946 /* Start the training iterating through available voltages and emphasis,
947 * testing each value twice. */
948 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
949 /* Configure DP_TP_CTL with auto-training */
950 I915_WRITE(DP_TP_CTL(PORT_E),
951 DP_TP_CTL_FDI_AUTOTRAIN |
952 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
953 DP_TP_CTL_LINK_TRAIN_PAT1 |
954 DP_TP_CTL_ENABLE);
955
956 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
957 * DDI E does not support port reversal, the functionality is
958 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
959 * port reversal bit */
960 I915_WRITE(DDI_BUF_CTL(PORT_E),
961 DDI_BUF_CTL_ENABLE |
962 ((crtc_state->fdi_lanes - 1) << 1) |
963 DDI_BUF_TRANS_SELECT(i / 2));
964 POSTING_READ(DDI_BUF_CTL(PORT_E));
965
966 udelay(600);
967
968 /* Program PCH FDI Receiver TU */
969 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
970
971 /* Enable PCH FDI Receiver with auto-training */
972 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
973 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
974 POSTING_READ(FDI_RX_CTL(PIPE_A));
975
976 /* Wait for FDI receiver lane calibration */
977 udelay(30);
978
979 /* Unset FDI_RX_MISC pwrdn lanes */
980 temp = I915_READ(FDI_RX_MISC(PIPE_A));
981 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
982 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
983 POSTING_READ(FDI_RX_MISC(PIPE_A));
984
985 /* Wait for FDI auto training time */
986 udelay(5);
987
988 temp = I915_READ(DP_TP_STATUS(PORT_E));
989 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
990 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
991 break;
992 }
993
994 /*
995 * Leave things enabled even if we failed to train FDI.
996 * Results in less fireworks from the state checker.
997 */
998 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
999 DRM_ERROR("FDI link training failed!\n");
1000 break;
1001 }
1002
1003 rx_ctl_val &= ~FDI_RX_ENABLE;
1004 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1005 POSTING_READ(FDI_RX_CTL(PIPE_A));
1006
1007 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1008 temp &= ~DDI_BUF_CTL_ENABLE;
1009 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1010 POSTING_READ(DDI_BUF_CTL(PORT_E));
1011
1012 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1013 temp = I915_READ(DP_TP_CTL(PORT_E));
1014 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1015 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1016 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1017 POSTING_READ(DP_TP_CTL(PORT_E));
1018
1019 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1020
1021 /* Reset FDI_RX_MISC pwrdn lanes */
1022 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1023 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1024 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1025 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1026 POSTING_READ(FDI_RX_MISC(PIPE_A));
1027 }
1028
1029 /* Enable normal pixel sending for FDI */
1030 I915_WRITE(DP_TP_CTL(PORT_E),
1031 DP_TP_CTL_FDI_AUTOTRAIN |
1032 DP_TP_CTL_LINK_TRAIN_NORMAL |
1033 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1034 DP_TP_CTL_ENABLE);
1035 }
1036
1037 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1038 {
1039 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1040 struct intel_digital_port *intel_dig_port =
1041 enc_to_dig_port(&encoder->base);
1042
1043 intel_dp->DP = intel_dig_port->saved_port_bits |
1044 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1045 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1046 }
1047
1048 static struct intel_encoder *
1049 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1050 {
1051 struct drm_device *dev = crtc->base.dev;
1052 struct intel_encoder *encoder, *ret = NULL;
1053 int num_encoders = 0;
1054
1055 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1056 ret = encoder;
1057 num_encoders++;
1058 }
1059
1060 if (num_encoders != 1)
1061 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1062 pipe_name(crtc->pipe));
1063
1064 BUG_ON(ret == NULL);
1065 return ret;
1066 }
1067
1068 /* Finds the only possible encoder associated with the given CRTC. */
1069 struct intel_encoder *
1070 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
1071 {
1072 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1073 struct intel_encoder *ret = NULL;
1074 struct drm_atomic_state *state;
1075 struct drm_connector *connector;
1076 struct drm_connector_state *connector_state;
1077 int num_encoders = 0;
1078 int i;
1079
1080 state = crtc_state->base.state;
1081
1082 for_each_new_connector_in_state(state, connector, connector_state, i) {
1083 if (connector_state->crtc != crtc_state->base.crtc)
1084 continue;
1085
1086 ret = to_intel_encoder(connector_state->best_encoder);
1087 num_encoders++;
1088 }
1089
1090 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1091 pipe_name(crtc->pipe));
1092
1093 BUG_ON(ret == NULL);
1094 return ret;
1095 }
1096
1097 #define LC_FREQ 2700
1098
1099 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1100 i915_reg_t reg)
1101 {
1102 int refclk = LC_FREQ;
1103 int n, p, r;
1104 u32 wrpll;
1105
1106 wrpll = I915_READ(reg);
1107 switch (wrpll & WRPLL_PLL_REF_MASK) {
1108 case WRPLL_PLL_SSC:
1109 case WRPLL_PLL_NON_SSC:
1110 /*
1111 * We could calculate spread here, but our checking
1112 * code only cares about 5% accuracy, and spread is a max of
1113 * 0.5% downspread.
1114 */
1115 refclk = 135;
1116 break;
1117 case WRPLL_PLL_LCPLL:
1118 refclk = LC_FREQ;
1119 break;
1120 default:
1121 WARN(1, "bad wrpll refclk\n");
1122 return 0;
1123 }
1124
1125 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1126 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1127 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1128
1129 /* Convert to KHz, p & r have a fixed point portion */
1130 return (refclk * n * 100) / (p * r);
1131 }
1132
1133 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1134 enum intel_dpll_id pll_id)
1135 {
1136 i915_reg_t cfgcr1_reg, cfgcr2_reg;
1137 uint32_t cfgcr1_val, cfgcr2_val;
1138 uint32_t p0, p1, p2, dco_freq;
1139
1140 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1141 cfgcr2_reg = DPLL_CFGCR2(pll_id);
1142
1143 cfgcr1_val = I915_READ(cfgcr1_reg);
1144 cfgcr2_val = I915_READ(cfgcr2_reg);
1145
1146 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1147 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1148
1149 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1150 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1151 else
1152 p1 = 1;
1153
1154
1155 switch (p0) {
1156 case DPLL_CFGCR2_PDIV_1:
1157 p0 = 1;
1158 break;
1159 case DPLL_CFGCR2_PDIV_2:
1160 p0 = 2;
1161 break;
1162 case DPLL_CFGCR2_PDIV_3:
1163 p0 = 3;
1164 break;
1165 case DPLL_CFGCR2_PDIV_7:
1166 p0 = 7;
1167 break;
1168 }
1169
1170 switch (p2) {
1171 case DPLL_CFGCR2_KDIV_5:
1172 p2 = 5;
1173 break;
1174 case DPLL_CFGCR2_KDIV_2:
1175 p2 = 2;
1176 break;
1177 case DPLL_CFGCR2_KDIV_3:
1178 p2 = 3;
1179 break;
1180 case DPLL_CFGCR2_KDIV_1:
1181 p2 = 1;
1182 break;
1183 }
1184
1185 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1186
1187 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1188 1000) / 0x8000;
1189
1190 return dco_freq / (p0 * p1 * p2 * 5);
1191 }
1192
1193 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1194 enum intel_dpll_id pll_id)
1195 {
1196 uint32_t cfgcr0, cfgcr1;
1197 uint32_t p0, p1, p2, dco_freq, ref_clock;
1198
1199 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1200 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1201
1202 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1203 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1204
1205 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1206 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1207 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1208 else
1209 p1 = 1;
1210
1211
1212 switch (p0) {
1213 case DPLL_CFGCR1_PDIV_2:
1214 p0 = 2;
1215 break;
1216 case DPLL_CFGCR1_PDIV_3:
1217 p0 = 3;
1218 break;
1219 case DPLL_CFGCR1_PDIV_5:
1220 p0 = 5;
1221 break;
1222 case DPLL_CFGCR1_PDIV_7:
1223 p0 = 7;
1224 break;
1225 }
1226
1227 switch (p2) {
1228 case DPLL_CFGCR1_KDIV_1:
1229 p2 = 1;
1230 break;
1231 case DPLL_CFGCR1_KDIV_2:
1232 p2 = 2;
1233 break;
1234 case DPLL_CFGCR1_KDIV_4:
1235 p2 = 4;
1236 break;
1237 }
1238
1239 ref_clock = dev_priv->cdclk.hw.ref;
1240
1241 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1242
1243 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1244 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1245
1246 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1247 return 0;
1248
1249 return dco_freq / (p0 * p1 * p2 * 5);
1250 }
1251
1252 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1253 {
1254 int dotclock;
1255
1256 if (pipe_config->has_pch_encoder)
1257 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1258 &pipe_config->fdi_m_n);
1259 else if (intel_crtc_has_dp_encoder(pipe_config))
1260 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1261 &pipe_config->dp_m_n);
1262 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1263 dotclock = pipe_config->port_clock * 2 / 3;
1264 else
1265 dotclock = pipe_config->port_clock;
1266
1267 if (pipe_config->ycbcr420)
1268 dotclock *= 2;
1269
1270 if (pipe_config->pixel_multiplier)
1271 dotclock /= pipe_config->pixel_multiplier;
1272
1273 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1274 }
1275
1276 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1277 struct intel_crtc_state *pipe_config)
1278 {
1279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1280 int link_clock = 0;
1281 uint32_t cfgcr0;
1282 enum intel_dpll_id pll_id;
1283
1284 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1285
1286 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1287
1288 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1289 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1290 } else {
1291 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1292
1293 switch (link_clock) {
1294 case DPLL_CFGCR0_LINK_RATE_810:
1295 link_clock = 81000;
1296 break;
1297 case DPLL_CFGCR0_LINK_RATE_1080:
1298 link_clock = 108000;
1299 break;
1300 case DPLL_CFGCR0_LINK_RATE_1350:
1301 link_clock = 135000;
1302 break;
1303 case DPLL_CFGCR0_LINK_RATE_1620:
1304 link_clock = 162000;
1305 break;
1306 case DPLL_CFGCR0_LINK_RATE_2160:
1307 link_clock = 216000;
1308 break;
1309 case DPLL_CFGCR0_LINK_RATE_2700:
1310 link_clock = 270000;
1311 break;
1312 case DPLL_CFGCR0_LINK_RATE_3240:
1313 link_clock = 324000;
1314 break;
1315 case DPLL_CFGCR0_LINK_RATE_4050:
1316 link_clock = 405000;
1317 break;
1318 default:
1319 WARN(1, "Unsupported link rate\n");
1320 break;
1321 }
1322 link_clock *= 2;
1323 }
1324
1325 pipe_config->port_clock = link_clock;
1326
1327 ddi_dotclock_get(pipe_config);
1328 }
1329
1330 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1331 struct intel_crtc_state *pipe_config)
1332 {
1333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1334 int link_clock = 0;
1335 uint32_t dpll_ctl1;
1336 enum intel_dpll_id pll_id;
1337
1338 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1339
1340 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1341
1342 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1343 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1344 } else {
1345 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1346 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1347
1348 switch (link_clock) {
1349 case DPLL_CTRL1_LINK_RATE_810:
1350 link_clock = 81000;
1351 break;
1352 case DPLL_CTRL1_LINK_RATE_1080:
1353 link_clock = 108000;
1354 break;
1355 case DPLL_CTRL1_LINK_RATE_1350:
1356 link_clock = 135000;
1357 break;
1358 case DPLL_CTRL1_LINK_RATE_1620:
1359 link_clock = 162000;
1360 break;
1361 case DPLL_CTRL1_LINK_RATE_2160:
1362 link_clock = 216000;
1363 break;
1364 case DPLL_CTRL1_LINK_RATE_2700:
1365 link_clock = 270000;
1366 break;
1367 default:
1368 WARN(1, "Unsupported link rate\n");
1369 break;
1370 }
1371 link_clock *= 2;
1372 }
1373
1374 pipe_config->port_clock = link_clock;
1375
1376 ddi_dotclock_get(pipe_config);
1377 }
1378
1379 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1380 struct intel_crtc_state *pipe_config)
1381 {
1382 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1383 int link_clock = 0;
1384 u32 val, pll;
1385
1386 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1387 switch (val & PORT_CLK_SEL_MASK) {
1388 case PORT_CLK_SEL_LCPLL_810:
1389 link_clock = 81000;
1390 break;
1391 case PORT_CLK_SEL_LCPLL_1350:
1392 link_clock = 135000;
1393 break;
1394 case PORT_CLK_SEL_LCPLL_2700:
1395 link_clock = 270000;
1396 break;
1397 case PORT_CLK_SEL_WRPLL1:
1398 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1399 break;
1400 case PORT_CLK_SEL_WRPLL2:
1401 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1402 break;
1403 case PORT_CLK_SEL_SPLL:
1404 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1405 if (pll == SPLL_PLL_FREQ_810MHz)
1406 link_clock = 81000;
1407 else if (pll == SPLL_PLL_FREQ_1350MHz)
1408 link_clock = 135000;
1409 else if (pll == SPLL_PLL_FREQ_2700MHz)
1410 link_clock = 270000;
1411 else {
1412 WARN(1, "bad spll freq\n");
1413 return;
1414 }
1415 break;
1416 default:
1417 WARN(1, "bad port clock sel\n");
1418 return;
1419 }
1420
1421 pipe_config->port_clock = link_clock * 2;
1422
1423 ddi_dotclock_get(pipe_config);
1424 }
1425
1426 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1427 {
1428 struct intel_dpll_hw_state *state;
1429 struct dpll clock;
1430
1431 /* For DDI ports we always use a shared PLL. */
1432 if (WARN_ON(!crtc_state->shared_dpll))
1433 return 0;
1434
1435 state = &crtc_state->dpll_hw_state;
1436
1437 clock.m1 = 2;
1438 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1439 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1440 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1441 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1442 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1443 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1444
1445 return chv_calc_dpll_params(100000, &clock);
1446 }
1447
1448 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1449 struct intel_crtc_state *pipe_config)
1450 {
1451 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1452
1453 ddi_dotclock_get(pipe_config);
1454 }
1455
1456 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1457 struct intel_crtc_state *pipe_config)
1458 {
1459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1460
1461 if (INTEL_GEN(dev_priv) <= 8)
1462 hsw_ddi_clock_get(encoder, pipe_config);
1463 else if (IS_GEN9_BC(dev_priv))
1464 skl_ddi_clock_get(encoder, pipe_config);
1465 else if (IS_GEN9_LP(dev_priv))
1466 bxt_ddi_clock_get(encoder, pipe_config);
1467 else if (IS_CANNONLAKE(dev_priv))
1468 cnl_ddi_clock_get(encoder, pipe_config);
1469 }
1470
1471 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1472 {
1473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1475 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1476 u32 temp;
1477
1478 if (!intel_crtc_has_dp_encoder(crtc_state))
1479 return;
1480
1481 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1482
1483 temp = TRANS_MSA_SYNC_CLK;
1484 switch (crtc_state->pipe_bpp) {
1485 case 18:
1486 temp |= TRANS_MSA_6_BPC;
1487 break;
1488 case 24:
1489 temp |= TRANS_MSA_8_BPC;
1490 break;
1491 case 30:
1492 temp |= TRANS_MSA_10_BPC;
1493 break;
1494 case 36:
1495 temp |= TRANS_MSA_12_BPC;
1496 break;
1497 default:
1498 MISSING_CASE(crtc_state->pipe_bpp);
1499 break;
1500 }
1501
1502 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1503 }
1504
1505 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1506 bool state)
1507 {
1508 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1511 uint32_t temp;
1512
1513 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1514 if (state == true)
1515 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1516 else
1517 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1518 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1519 }
1520
1521 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1522 {
1523 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1525 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1526 enum pipe pipe = crtc->pipe;
1527 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1528 enum port port = encoder->port;
1529 uint32_t temp;
1530
1531 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1532 temp = TRANS_DDI_FUNC_ENABLE;
1533 temp |= TRANS_DDI_SELECT_PORT(port);
1534
1535 switch (crtc_state->pipe_bpp) {
1536 case 18:
1537 temp |= TRANS_DDI_BPC_6;
1538 break;
1539 case 24:
1540 temp |= TRANS_DDI_BPC_8;
1541 break;
1542 case 30:
1543 temp |= TRANS_DDI_BPC_10;
1544 break;
1545 case 36:
1546 temp |= TRANS_DDI_BPC_12;
1547 break;
1548 default:
1549 BUG();
1550 }
1551
1552 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1553 temp |= TRANS_DDI_PVSYNC;
1554 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1555 temp |= TRANS_DDI_PHSYNC;
1556
1557 if (cpu_transcoder == TRANSCODER_EDP) {
1558 switch (pipe) {
1559 case PIPE_A:
1560 /* On Haswell, can only use the always-on power well for
1561 * eDP when not using the panel fitter, and when not
1562 * using motion blur mitigation (which we don't
1563 * support). */
1564 if (IS_HASWELL(dev_priv) &&
1565 (crtc_state->pch_pfit.enabled ||
1566 crtc_state->pch_pfit.force_thru))
1567 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1568 else
1569 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1570 break;
1571 case PIPE_B:
1572 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1573 break;
1574 case PIPE_C:
1575 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1576 break;
1577 default:
1578 BUG();
1579 break;
1580 }
1581 }
1582
1583 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1584 if (crtc_state->has_hdmi_sink)
1585 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1586 else
1587 temp |= TRANS_DDI_MODE_SELECT_DVI;
1588
1589 if (crtc_state->hdmi_scrambling)
1590 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1591 if (crtc_state->hdmi_high_tmds_clock_ratio)
1592 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1593 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1594 temp |= TRANS_DDI_MODE_SELECT_FDI;
1595 temp |= (crtc_state->fdi_lanes - 1) << 1;
1596 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1597 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1598 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1599 } else {
1600 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1601 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1602 }
1603
1604 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1605 }
1606
1607 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1608 enum transcoder cpu_transcoder)
1609 {
1610 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1611 uint32_t val = I915_READ(reg);
1612
1613 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1614 val |= TRANS_DDI_PORT_NONE;
1615 I915_WRITE(reg, val);
1616 }
1617
1618 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1619 {
1620 struct drm_device *dev = intel_connector->base.dev;
1621 struct drm_i915_private *dev_priv = to_i915(dev);
1622 struct intel_encoder *encoder = intel_connector->encoder;
1623 int type = intel_connector->base.connector_type;
1624 enum port port = encoder->port;
1625 enum pipe pipe = 0;
1626 enum transcoder cpu_transcoder;
1627 uint32_t tmp;
1628 bool ret;
1629
1630 if (!intel_display_power_get_if_enabled(dev_priv,
1631 encoder->power_domain))
1632 return false;
1633
1634 if (!encoder->get_hw_state(encoder, &pipe)) {
1635 ret = false;
1636 goto out;
1637 }
1638
1639 if (port == PORT_A)
1640 cpu_transcoder = TRANSCODER_EDP;
1641 else
1642 cpu_transcoder = (enum transcoder) pipe;
1643
1644 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1645
1646 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1647 case TRANS_DDI_MODE_SELECT_HDMI:
1648 case TRANS_DDI_MODE_SELECT_DVI:
1649 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1650 break;
1651
1652 case TRANS_DDI_MODE_SELECT_DP_SST:
1653 ret = type == DRM_MODE_CONNECTOR_eDP ||
1654 type == DRM_MODE_CONNECTOR_DisplayPort;
1655 break;
1656
1657 case TRANS_DDI_MODE_SELECT_DP_MST:
1658 /* if the transcoder is in MST state then
1659 * connector isn't connected */
1660 ret = false;
1661 break;
1662
1663 case TRANS_DDI_MODE_SELECT_FDI:
1664 ret = type == DRM_MODE_CONNECTOR_VGA;
1665 break;
1666
1667 default:
1668 ret = false;
1669 break;
1670 }
1671
1672 out:
1673 intel_display_power_put(dev_priv, encoder->power_domain);
1674
1675 return ret;
1676 }
1677
1678 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1679 enum pipe *pipe)
1680 {
1681 struct drm_device *dev = encoder->base.dev;
1682 struct drm_i915_private *dev_priv = to_i915(dev);
1683 enum port port = encoder->port;
1684 enum pipe p;
1685 u32 tmp;
1686 bool ret;
1687
1688 if (!intel_display_power_get_if_enabled(dev_priv,
1689 encoder->power_domain))
1690 return false;
1691
1692 ret = false;
1693
1694 tmp = I915_READ(DDI_BUF_CTL(port));
1695
1696 if (!(tmp & DDI_BUF_CTL_ENABLE))
1697 goto out;
1698
1699 if (port == PORT_A) {
1700 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1701
1702 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1703 case TRANS_DDI_EDP_INPUT_A_ON:
1704 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1705 *pipe = PIPE_A;
1706 break;
1707 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1708 *pipe = PIPE_B;
1709 break;
1710 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1711 *pipe = PIPE_C;
1712 break;
1713 }
1714
1715 ret = true;
1716
1717 goto out;
1718 }
1719
1720 for_each_pipe(dev_priv, p) {
1721 enum transcoder cpu_transcoder = (enum transcoder) p;
1722
1723 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1724
1725 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1726 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1727 TRANS_DDI_MODE_SELECT_DP_MST)
1728 goto out;
1729
1730 *pipe = p;
1731 ret = true;
1732
1733 goto out;
1734 }
1735 }
1736
1737 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1738
1739 out:
1740 if (ret && IS_GEN9_LP(dev_priv)) {
1741 tmp = I915_READ(BXT_PHY_CTL(port));
1742 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1743 BXT_PHY_LANE_POWERDOWN_ACK |
1744 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1745 DRM_ERROR("Port %c enabled but PHY powered down? "
1746 "(PHY_CTL %08x)\n", port_name(port), tmp);
1747 }
1748
1749 intel_display_power_put(dev_priv, encoder->power_domain);
1750
1751 return ret;
1752 }
1753
1754 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1755 {
1756 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1757 enum pipe pipe;
1758
1759 if (intel_ddi_get_hw_state(encoder, &pipe))
1760 return BIT_ULL(dig_port->ddi_io_power_domain);
1761
1762 return 0;
1763 }
1764
1765 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1766 {
1767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1768 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1769 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1770 enum port port = encoder->port;
1771 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1772
1773 if (cpu_transcoder != TRANSCODER_EDP)
1774 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1775 TRANS_CLK_SEL_PORT(port));
1776 }
1777
1778 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1779 {
1780 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1781 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1782
1783 if (cpu_transcoder != TRANSCODER_EDP)
1784 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1785 TRANS_CLK_SEL_DISABLED);
1786 }
1787
1788 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1789 enum port port, uint8_t iboost)
1790 {
1791 u32 tmp;
1792
1793 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1794 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1795 if (iboost)
1796 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1797 else
1798 tmp |= BALANCE_LEG_DISABLE(port);
1799 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1800 }
1801
1802 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1803 int level, enum intel_output_type type)
1804 {
1805 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1806 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1807 enum port port = encoder->port;
1808 uint8_t iboost;
1809
1810 if (type == INTEL_OUTPUT_HDMI)
1811 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1812 else
1813 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1814
1815 if (iboost == 0) {
1816 const struct ddi_buf_trans *ddi_translations;
1817 int n_entries;
1818
1819 if (type == INTEL_OUTPUT_HDMI)
1820 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1821 else if (type == INTEL_OUTPUT_EDP)
1822 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1823 else
1824 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1825
1826 if (WARN_ON_ONCE(!ddi_translations))
1827 return;
1828 if (WARN_ON_ONCE(level >= n_entries))
1829 level = n_entries - 1;
1830
1831 iboost = ddi_translations[level].i_boost;
1832 }
1833
1834 /* Make sure that the requested I_boost is valid */
1835 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1836 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1837 return;
1838 }
1839
1840 _skl_ddi_set_iboost(dev_priv, port, iboost);
1841
1842 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1843 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1844 }
1845
1846 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
1847 int level, enum intel_output_type type)
1848 {
1849 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1850 const struct bxt_ddi_buf_trans *ddi_translations;
1851 enum port port = encoder->port;
1852 int n_entries;
1853
1854 if (type == INTEL_OUTPUT_HDMI)
1855 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1856 else if (type == INTEL_OUTPUT_EDP)
1857 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
1858 else
1859 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
1860
1861 if (WARN_ON_ONCE(!ddi_translations))
1862 return;
1863 if (WARN_ON_ONCE(level >= n_entries))
1864 level = n_entries - 1;
1865
1866 bxt_ddi_phy_set_signal_level(dev_priv, port,
1867 ddi_translations[level].margin,
1868 ddi_translations[level].scale,
1869 ddi_translations[level].enable,
1870 ddi_translations[level].deemphasis);
1871 }
1872
1873 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1874 {
1875 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1876 enum port port = encoder->port;
1877 int n_entries;
1878
1879 if (IS_CANNONLAKE(dev_priv)) {
1880 if (encoder->type == INTEL_OUTPUT_EDP)
1881 cnl_get_buf_trans_edp(dev_priv, &n_entries);
1882 else
1883 cnl_get_buf_trans_dp(dev_priv, &n_entries);
1884 } else if (IS_GEN9_LP(dev_priv)) {
1885 if (encoder->type == INTEL_OUTPUT_EDP)
1886 bxt_get_buf_trans_edp(dev_priv, &n_entries);
1887 else
1888 bxt_get_buf_trans_dp(dev_priv, &n_entries);
1889 } else {
1890 if (encoder->type == INTEL_OUTPUT_EDP)
1891 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1892 else
1893 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1894 }
1895
1896 if (WARN_ON(n_entries < 1))
1897 n_entries = 1;
1898 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1899 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1900
1901 return index_to_dp_signal_levels[n_entries - 1] &
1902 DP_TRAIN_VOLTAGE_SWING_MASK;
1903 }
1904
1905 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
1906 int level, enum intel_output_type type)
1907 {
1908 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1909 const struct cnl_ddi_buf_trans *ddi_translations;
1910 enum port port = encoder->port;
1911 int n_entries, ln;
1912 u32 val;
1913
1914 if (type == INTEL_OUTPUT_HDMI)
1915 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1916 else if (type == INTEL_OUTPUT_EDP)
1917 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
1918 else
1919 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
1920
1921 if (WARN_ON_ONCE(!ddi_translations))
1922 return;
1923 if (WARN_ON_ONCE(level >= n_entries))
1924 level = n_entries - 1;
1925
1926 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1927 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1928 val &= ~SCALING_MODE_SEL_MASK;
1929 val |= SCALING_MODE_SEL(2);
1930 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1931
1932 /* Program PORT_TX_DW2 */
1933 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1934 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1935 RCOMP_SCALAR_MASK);
1936 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1937 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1938 /* Rcomp scalar is fixed as 0x98 for every table entry */
1939 val |= RCOMP_SCALAR(0x98);
1940 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1941
1942 /* Program PORT_TX_DW4 */
1943 /* We cannot write to GRP. It would overrite individual loadgen */
1944 for (ln = 0; ln < 4; ln++) {
1945 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1946 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1947 CURSOR_COEFF_MASK);
1948 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1949 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1950 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1951 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1952 }
1953
1954 /* Program PORT_TX_DW5 */
1955 /* All DW5 values are fixed for every table entry */
1956 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1957 val &= ~RTERM_SELECT_MASK;
1958 val |= RTERM_SELECT(6);
1959 val |= TAP3_DISABLE;
1960 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1961
1962 /* Program PORT_TX_DW7 */
1963 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1964 val &= ~N_SCALAR_MASK;
1965 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1966 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1967 }
1968
1969 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
1970 int level, enum intel_output_type type)
1971 {
1972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1973 enum port port = encoder->port;
1974 int width, rate, ln;
1975 u32 val;
1976
1977 if (type == INTEL_OUTPUT_HDMI) {
1978 width = 4;
1979 rate = 0; /* Rate is always < than 6GHz for HDMI */
1980 } else {
1981 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1982
1983 width = intel_dp->lane_count;
1984 rate = intel_dp->link_rate;
1985 }
1986
1987 /*
1988 * 1. If port type is eDP or DP,
1989 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1990 * else clear to 0b.
1991 */
1992 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
1993 if (type != INTEL_OUTPUT_HDMI)
1994 val |= COMMON_KEEPER_EN;
1995 else
1996 val &= ~COMMON_KEEPER_EN;
1997 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
1998
1999 /* 2. Program loadgen select */
2000 /*
2001 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2002 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2003 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2004 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2005 */
2006 for (ln = 0; ln <= 3; ln++) {
2007 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2008 val &= ~LOADGEN_SELECT;
2009
2010 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2011 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2012 val |= LOADGEN_SELECT;
2013 }
2014 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2015 }
2016
2017 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2018 val = I915_READ(CNL_PORT_CL1CM_DW5);
2019 val |= SUS_CLOCK_CONFIG;
2020 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2021
2022 /* 4. Clear training enable to change swing values */
2023 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2024 val &= ~TX_TRAINING_EN;
2025 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2026
2027 /* 5. Program swing and de-emphasis */
2028 cnl_ddi_vswing_program(encoder, level, type);
2029
2030 /* 6. Set training enable to trigger update */
2031 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2032 val |= TX_TRAINING_EN;
2033 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2034 }
2035
2036 static uint32_t translate_signal_level(int signal_levels)
2037 {
2038 int i;
2039
2040 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2041 if (index_to_dp_signal_levels[i] == signal_levels)
2042 return i;
2043 }
2044
2045 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2046 signal_levels);
2047
2048 return 0;
2049 }
2050
2051 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2052 {
2053 uint8_t train_set = intel_dp->train_set[0];
2054 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2055 DP_TRAIN_PRE_EMPHASIS_MASK);
2056
2057 return translate_signal_level(signal_levels);
2058 }
2059
2060 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2061 {
2062 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2063 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2064 struct intel_encoder *encoder = &dport->base;
2065 int level = intel_ddi_dp_level(intel_dp);
2066
2067 if (IS_CANNONLAKE(dev_priv))
2068 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2069 else
2070 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2071
2072 return 0;
2073 }
2074
2075 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2076 {
2077 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2078 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2079 struct intel_encoder *encoder = &dport->base;
2080 int level = intel_ddi_dp_level(intel_dp);
2081
2082 if (IS_GEN9_BC(dev_priv))
2083 skl_ddi_set_iboost(encoder, level, encoder->type);
2084
2085 return DDI_BUF_TRANS_SELECT(level);
2086 }
2087
2088 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2089 const struct intel_shared_dpll *pll)
2090 {
2091 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2092 enum port port = encoder->port;
2093 uint32_t val;
2094
2095 if (WARN_ON(!pll))
2096 return;
2097
2098 mutex_lock(&dev_priv->dpll_lock);
2099
2100 if (IS_CANNONLAKE(dev_priv)) {
2101 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2102 val = I915_READ(DPCLKA_CFGCR0);
2103 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2104 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2105 I915_WRITE(DPCLKA_CFGCR0, val);
2106
2107 /*
2108 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2109 * This step and the step before must be done with separate
2110 * register writes.
2111 */
2112 val = I915_READ(DPCLKA_CFGCR0);
2113 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2114 I915_WRITE(DPCLKA_CFGCR0, val);
2115 } else if (IS_GEN9_BC(dev_priv)) {
2116 /* DDI -> PLL mapping */
2117 val = I915_READ(DPLL_CTRL2);
2118
2119 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2120 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2121 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2122 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2123
2124 I915_WRITE(DPLL_CTRL2, val);
2125
2126 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2127 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2128 }
2129
2130 mutex_unlock(&dev_priv->dpll_lock);
2131 }
2132
2133 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2134 {
2135 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2136 enum port port = encoder->port;
2137
2138 if (IS_CANNONLAKE(dev_priv))
2139 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2140 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2141 else if (IS_GEN9_BC(dev_priv))
2142 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2143 DPLL_CTRL2_DDI_CLK_OFF(port));
2144 else if (INTEL_GEN(dev_priv) < 9)
2145 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2146 }
2147
2148 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2149 const struct intel_crtc_state *crtc_state,
2150 const struct drm_connector_state *conn_state)
2151 {
2152 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2154 enum port port = encoder->port;
2155 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2156 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2157 int level = intel_ddi_dp_level(intel_dp);
2158
2159 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2160
2161 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2162 crtc_state->lane_count, is_mst);
2163
2164 intel_edp_panel_on(intel_dp);
2165
2166 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2167
2168 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2169
2170 if (IS_CANNONLAKE(dev_priv))
2171 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2172 else if (IS_GEN9_LP(dev_priv))
2173 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2174 else
2175 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2176
2177 intel_ddi_init_dp_buf_reg(encoder);
2178 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2179 intel_dp_start_link_train(intel_dp);
2180 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2181 intel_dp_stop_link_train(intel_dp);
2182 }
2183
2184 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2185 const struct intel_crtc_state *crtc_state,
2186 const struct drm_connector_state *conn_state)
2187 {
2188 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2189 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2191 enum port port = encoder->port;
2192 int level = intel_ddi_hdmi_level(dev_priv, port);
2193 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2194
2195 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2196 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2197
2198 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2199
2200 if (IS_CANNONLAKE(dev_priv))
2201 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2202 else if (IS_GEN9_LP(dev_priv))
2203 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2204 else
2205 intel_prepare_hdmi_ddi_buffers(encoder, level);
2206
2207 if (IS_GEN9_BC(dev_priv))
2208 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2209
2210 intel_dig_port->set_infoframes(&encoder->base,
2211 crtc_state->has_infoframe,
2212 crtc_state, conn_state);
2213 }
2214
2215 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2216 const struct intel_crtc_state *crtc_state,
2217 const struct drm_connector_state *conn_state)
2218 {
2219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2220 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2221 enum pipe pipe = crtc->pipe;
2222
2223 /*
2224 * When called from DP MST code:
2225 * - conn_state will be NULL
2226 * - encoder will be the main encoder (ie. mst->primary)
2227 * - the main connector associated with this port
2228 * won't be active or linked to a crtc
2229 * - crtc_state will be the state of the first stream to
2230 * be activated on this port, and it may not be the same
2231 * stream that will be deactivated last, but each stream
2232 * should have a state that is identical when it comes to
2233 * the DP link parameteres
2234 */
2235
2236 WARN_ON(crtc_state->has_pch_encoder);
2237
2238 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2239
2240 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2241 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2242 else
2243 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2244 }
2245
2246 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2247 {
2248 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2249 enum port port = encoder->port;
2250 bool wait = false;
2251 u32 val;
2252
2253 val = I915_READ(DDI_BUF_CTL(port));
2254 if (val & DDI_BUF_CTL_ENABLE) {
2255 val &= ~DDI_BUF_CTL_ENABLE;
2256 I915_WRITE(DDI_BUF_CTL(port), val);
2257 wait = true;
2258 }
2259
2260 val = I915_READ(DP_TP_CTL(port));
2261 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2262 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2263 I915_WRITE(DP_TP_CTL(port), val);
2264
2265 if (wait)
2266 intel_wait_ddi_buf_idle(dev_priv, port);
2267 }
2268
2269 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2270 const struct intel_crtc_state *old_crtc_state,
2271 const struct drm_connector_state *old_conn_state)
2272 {
2273 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2274 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2275 struct intel_dp *intel_dp = &dig_port->dp;
2276
2277 /*
2278 * Power down sink before disabling the port, otherwise we end
2279 * up getting interrupts from the sink on detecting link loss.
2280 */
2281 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2282
2283 intel_disable_ddi_buf(encoder);
2284
2285 intel_edp_panel_vdd_on(intel_dp);
2286 intel_edp_panel_off(intel_dp);
2287
2288 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2289
2290 intel_ddi_clk_disable(encoder);
2291 }
2292
2293 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2294 const struct intel_crtc_state *old_crtc_state,
2295 const struct drm_connector_state *old_conn_state)
2296 {
2297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2298 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2299 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2300
2301 intel_disable_ddi_buf(encoder);
2302
2303 dig_port->set_infoframes(&encoder->base, false,
2304 old_crtc_state, old_conn_state);
2305
2306 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2307
2308 intel_ddi_clk_disable(encoder);
2309
2310 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2311 }
2312
2313 static void intel_ddi_post_disable(struct intel_encoder *encoder,
2314 const struct intel_crtc_state *old_crtc_state,
2315 const struct drm_connector_state *old_conn_state)
2316 {
2317 /*
2318 * When called from DP MST code:
2319 * - old_conn_state will be NULL
2320 * - encoder will be the main encoder (ie. mst->primary)
2321 * - the main connector associated with this port
2322 * won't be active or linked to a crtc
2323 * - old_crtc_state will be the state of the last stream to
2324 * be deactivated on this port, and it may not be the same
2325 * stream that was activated last, but each stream
2326 * should have a state that is identical when it comes to
2327 * the DP link parameteres
2328 */
2329
2330 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2331 intel_ddi_post_disable_hdmi(encoder,
2332 old_crtc_state, old_conn_state);
2333 else
2334 intel_ddi_post_disable_dp(encoder,
2335 old_crtc_state, old_conn_state);
2336 }
2337
2338 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2339 const struct intel_crtc_state *old_crtc_state,
2340 const struct drm_connector_state *old_conn_state)
2341 {
2342 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2343 uint32_t val;
2344
2345 /*
2346 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2347 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2348 * step 13 is the correct place for it. Step 18 is where it was
2349 * originally before the BUN.
2350 */
2351 val = I915_READ(FDI_RX_CTL(PIPE_A));
2352 val &= ~FDI_RX_ENABLE;
2353 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2354
2355 intel_disable_ddi_buf(encoder);
2356 intel_ddi_clk_disable(encoder);
2357
2358 val = I915_READ(FDI_RX_MISC(PIPE_A));
2359 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2360 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2361 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2362
2363 val = I915_READ(FDI_RX_CTL(PIPE_A));
2364 val &= ~FDI_PCDCLK;
2365 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2366
2367 val = I915_READ(FDI_RX_CTL(PIPE_A));
2368 val &= ~FDI_RX_PLL_ENABLE;
2369 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2370 }
2371
2372 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2373 const struct intel_crtc_state *crtc_state,
2374 const struct drm_connector_state *conn_state)
2375 {
2376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2377 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2378 enum port port = encoder->port;
2379
2380 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2381 intel_dp_stop_link_train(intel_dp);
2382
2383 intel_edp_backlight_on(crtc_state, conn_state);
2384 intel_psr_enable(intel_dp, crtc_state);
2385 intel_edp_drrs_enable(intel_dp, crtc_state);
2386
2387 if (crtc_state->has_audio)
2388 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2389 }
2390
2391 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2392 const struct intel_crtc_state *crtc_state,
2393 const struct drm_connector_state *conn_state)
2394 {
2395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2396 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2397 enum port port = encoder->port;
2398
2399 intel_hdmi_handle_sink_scrambling(encoder,
2400 conn_state->connector,
2401 crtc_state->hdmi_high_tmds_clock_ratio,
2402 crtc_state->hdmi_scrambling);
2403
2404 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2405 * are ignored so nothing special needs to be done besides
2406 * enabling the port.
2407 */
2408 I915_WRITE(DDI_BUF_CTL(port),
2409 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2410
2411 if (crtc_state->has_audio)
2412 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2413 }
2414
2415 static void intel_enable_ddi(struct intel_encoder *encoder,
2416 const struct intel_crtc_state *crtc_state,
2417 const struct drm_connector_state *conn_state)
2418 {
2419 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2420 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2421 else
2422 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
2423 }
2424
2425 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2426 const struct intel_crtc_state *old_crtc_state,
2427 const struct drm_connector_state *old_conn_state)
2428 {
2429 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2430
2431 if (old_crtc_state->has_audio)
2432 intel_audio_codec_disable(encoder,
2433 old_crtc_state, old_conn_state);
2434
2435 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2436 intel_psr_disable(intel_dp, old_crtc_state);
2437 intel_edp_backlight_off(old_conn_state);
2438 }
2439
2440 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2441 const struct intel_crtc_state *old_crtc_state,
2442 const struct drm_connector_state *old_conn_state)
2443 {
2444 if (old_crtc_state->has_audio)
2445 intel_audio_codec_disable(encoder,
2446 old_crtc_state, old_conn_state);
2447
2448 intel_hdmi_handle_sink_scrambling(encoder,
2449 old_conn_state->connector,
2450 false, false);
2451 }
2452
2453 static void intel_disable_ddi(struct intel_encoder *encoder,
2454 const struct intel_crtc_state *old_crtc_state,
2455 const struct drm_connector_state *old_conn_state)
2456 {
2457 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2458 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2459 else
2460 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
2461 }
2462
2463 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2464 const struct intel_crtc_state *pipe_config,
2465 const struct drm_connector_state *conn_state)
2466 {
2467 uint8_t mask = pipe_config->lane_lat_optim_mask;
2468
2469 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2470 }
2471
2472 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2473 {
2474 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2475 struct drm_i915_private *dev_priv =
2476 to_i915(intel_dig_port->base.base.dev);
2477 enum port port = intel_dig_port->base.port;
2478 uint32_t val;
2479 bool wait = false;
2480
2481 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2482 val = I915_READ(DDI_BUF_CTL(port));
2483 if (val & DDI_BUF_CTL_ENABLE) {
2484 val &= ~DDI_BUF_CTL_ENABLE;
2485 I915_WRITE(DDI_BUF_CTL(port), val);
2486 wait = true;
2487 }
2488
2489 val = I915_READ(DP_TP_CTL(port));
2490 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2491 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2492 I915_WRITE(DP_TP_CTL(port), val);
2493 POSTING_READ(DP_TP_CTL(port));
2494
2495 if (wait)
2496 intel_wait_ddi_buf_idle(dev_priv, port);
2497 }
2498
2499 val = DP_TP_CTL_ENABLE |
2500 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2501 if (intel_dp->link_mst)
2502 val |= DP_TP_CTL_MODE_MST;
2503 else {
2504 val |= DP_TP_CTL_MODE_SST;
2505 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2506 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2507 }
2508 I915_WRITE(DP_TP_CTL(port), val);
2509 POSTING_READ(DP_TP_CTL(port));
2510
2511 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2512 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2513 POSTING_READ(DDI_BUF_CTL(port));
2514
2515 udelay(600);
2516 }
2517
2518 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2519 enum transcoder cpu_transcoder)
2520 {
2521 if (cpu_transcoder == TRANSCODER_EDP)
2522 return false;
2523
2524 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
2525 return false;
2526
2527 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
2528 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
2529 }
2530
2531 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
2532 struct intel_crtc_state *crtc_state)
2533 {
2534 if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
2535 crtc_state->min_voltage_level = 2;
2536 }
2537
2538 void intel_ddi_get_config(struct intel_encoder *encoder,
2539 struct intel_crtc_state *pipe_config)
2540 {
2541 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2542 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2543 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2544 struct intel_digital_port *intel_dig_port;
2545 u32 temp, flags = 0;
2546
2547 /* XXX: DSI transcoder paranoia */
2548 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2549 return;
2550
2551 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2552 if (temp & TRANS_DDI_PHSYNC)
2553 flags |= DRM_MODE_FLAG_PHSYNC;
2554 else
2555 flags |= DRM_MODE_FLAG_NHSYNC;
2556 if (temp & TRANS_DDI_PVSYNC)
2557 flags |= DRM_MODE_FLAG_PVSYNC;
2558 else
2559 flags |= DRM_MODE_FLAG_NVSYNC;
2560
2561 pipe_config->base.adjusted_mode.flags |= flags;
2562
2563 switch (temp & TRANS_DDI_BPC_MASK) {
2564 case TRANS_DDI_BPC_6:
2565 pipe_config->pipe_bpp = 18;
2566 break;
2567 case TRANS_DDI_BPC_8:
2568 pipe_config->pipe_bpp = 24;
2569 break;
2570 case TRANS_DDI_BPC_10:
2571 pipe_config->pipe_bpp = 30;
2572 break;
2573 case TRANS_DDI_BPC_12:
2574 pipe_config->pipe_bpp = 36;
2575 break;
2576 default:
2577 break;
2578 }
2579
2580 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2581 case TRANS_DDI_MODE_SELECT_HDMI:
2582 pipe_config->has_hdmi_sink = true;
2583 intel_dig_port = enc_to_dig_port(&encoder->base);
2584
2585 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
2586 pipe_config->has_infoframe = true;
2587
2588 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2589 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2590 pipe_config->hdmi_scrambling = true;
2591 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2592 pipe_config->hdmi_high_tmds_clock_ratio = true;
2593 /* fall through */
2594 case TRANS_DDI_MODE_SELECT_DVI:
2595 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
2596 pipe_config->lane_count = 4;
2597 break;
2598 case TRANS_DDI_MODE_SELECT_FDI:
2599 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
2600 break;
2601 case TRANS_DDI_MODE_SELECT_DP_SST:
2602 if (encoder->type == INTEL_OUTPUT_EDP)
2603 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2604 else
2605 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2606 pipe_config->lane_count =
2607 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2608 intel_dp_get_m_n(intel_crtc, pipe_config);
2609 break;
2610 case TRANS_DDI_MODE_SELECT_DP_MST:
2611 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
2612 pipe_config->lane_count =
2613 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2614 intel_dp_get_m_n(intel_crtc, pipe_config);
2615 break;
2616 default:
2617 break;
2618 }
2619
2620 pipe_config->has_audio =
2621 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
2622
2623 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2624 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2625 /*
2626 * This is a big fat ugly hack.
2627 *
2628 * Some machines in UEFI boot mode provide us a VBT that has 18
2629 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2630 * unknown we fail to light up. Yet the same BIOS boots up with
2631 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2632 * max, not what it tells us to use.
2633 *
2634 * Note: This will still be broken if the eDP panel is not lit
2635 * up by the BIOS, and thus we can't get the mode at module
2636 * load.
2637 */
2638 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2639 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2640 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2641 }
2642
2643 intel_ddi_clock_get(encoder, pipe_config);
2644
2645 if (IS_GEN9_LP(dev_priv))
2646 pipe_config->lane_lat_optim_mask =
2647 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2648
2649 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
2650 }
2651
2652 static enum intel_output_type
2653 intel_ddi_compute_output_type(struct intel_encoder *encoder,
2654 struct intel_crtc_state *crtc_state,
2655 struct drm_connector_state *conn_state)
2656 {
2657 switch (conn_state->connector->connector_type) {
2658 case DRM_MODE_CONNECTOR_HDMIA:
2659 return INTEL_OUTPUT_HDMI;
2660 case DRM_MODE_CONNECTOR_eDP:
2661 return INTEL_OUTPUT_EDP;
2662 case DRM_MODE_CONNECTOR_DisplayPort:
2663 return INTEL_OUTPUT_DP;
2664 default:
2665 MISSING_CASE(conn_state->connector->connector_type);
2666 return INTEL_OUTPUT_UNUSED;
2667 }
2668 }
2669
2670 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2671 struct intel_crtc_state *pipe_config,
2672 struct drm_connector_state *conn_state)
2673 {
2674 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2675 enum port port = encoder->port;
2676 int ret;
2677
2678 if (port == PORT_A)
2679 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2680
2681 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
2682 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2683 else
2684 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2685
2686 if (IS_GEN9_LP(dev_priv) && ret)
2687 pipe_config->lane_lat_optim_mask =
2688 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
2689
2690 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
2691
2692 return ret;
2693
2694 }
2695
2696 static const struct drm_encoder_funcs intel_ddi_funcs = {
2697 .reset = intel_dp_encoder_reset,
2698 .destroy = intel_dp_encoder_destroy,
2699 };
2700
2701 static struct intel_connector *
2702 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2703 {
2704 struct intel_connector *connector;
2705 enum port port = intel_dig_port->base.port;
2706
2707 connector = intel_connector_alloc();
2708 if (!connector)
2709 return NULL;
2710
2711 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2712 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2713 kfree(connector);
2714 return NULL;
2715 }
2716
2717 return connector;
2718 }
2719
2720 static struct intel_connector *
2721 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2722 {
2723 struct intel_connector *connector;
2724 enum port port = intel_dig_port->base.port;
2725
2726 connector = intel_connector_alloc();
2727 if (!connector)
2728 return NULL;
2729
2730 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2731 intel_hdmi_init_connector(intel_dig_port, connector);
2732
2733 return connector;
2734 }
2735
2736 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
2737 {
2738 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2739
2740 if (dport->base.port != PORT_A)
2741 return false;
2742
2743 if (dport->saved_port_bits & DDI_A_4_LANES)
2744 return false;
2745
2746 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
2747 * supported configuration
2748 */
2749 if (IS_GEN9_LP(dev_priv))
2750 return true;
2751
2752 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
2753 * one who does also have a full A/E split called
2754 * DDI_F what makes DDI_E useless. However for this
2755 * case let's trust VBT info.
2756 */
2757 if (IS_CANNONLAKE(dev_priv) &&
2758 !intel_bios_is_port_present(dev_priv, PORT_E))
2759 return true;
2760
2761 return false;
2762 }
2763
2764 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2765 {
2766 struct intel_digital_port *intel_dig_port;
2767 struct intel_encoder *intel_encoder;
2768 struct drm_encoder *encoder;
2769 bool init_hdmi, init_dp, init_lspcon = false;
2770 int max_lanes;
2771
2772 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2773 switch (port) {
2774 case PORT_A:
2775 max_lanes = 4;
2776 break;
2777 case PORT_E:
2778 max_lanes = 0;
2779 break;
2780 default:
2781 max_lanes = 4;
2782 break;
2783 }
2784 } else {
2785 switch (port) {
2786 case PORT_A:
2787 max_lanes = 2;
2788 break;
2789 case PORT_E:
2790 max_lanes = 2;
2791 break;
2792 default:
2793 max_lanes = 4;
2794 break;
2795 }
2796 }
2797
2798 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2799 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2800 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2801
2802 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2803 /*
2804 * Lspcon device needs to be driven with DP connector
2805 * with special detection sequence. So make sure DP
2806 * is initialized before lspcon.
2807 */
2808 init_dp = true;
2809 init_lspcon = true;
2810 init_hdmi = false;
2811 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2812 }
2813
2814 if (!init_dp && !init_hdmi) {
2815 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2816 port_name(port));
2817 return;
2818 }
2819
2820 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2821 if (!intel_dig_port)
2822 return;
2823
2824 intel_encoder = &intel_dig_port->base;
2825 encoder = &intel_encoder->base;
2826
2827 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2828 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2829
2830 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
2831 intel_encoder->compute_config = intel_ddi_compute_config;
2832 intel_encoder->enable = intel_enable_ddi;
2833 if (IS_GEN9_LP(dev_priv))
2834 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2835 intel_encoder->pre_enable = intel_ddi_pre_enable;
2836 intel_encoder->disable = intel_disable_ddi;
2837 intel_encoder->post_disable = intel_ddi_post_disable;
2838 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2839 intel_encoder->get_config = intel_ddi_get_config;
2840 intel_encoder->suspend = intel_dp_encoder_suspend;
2841 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
2842
2843 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2844 (DDI_BUF_PORT_REVERSAL |
2845 DDI_A_4_LANES);
2846
2847 switch (port) {
2848 case PORT_A:
2849 intel_dig_port->ddi_io_power_domain =
2850 POWER_DOMAIN_PORT_DDI_A_IO;
2851 break;
2852 case PORT_B:
2853 intel_dig_port->ddi_io_power_domain =
2854 POWER_DOMAIN_PORT_DDI_B_IO;
2855 break;
2856 case PORT_C:
2857 intel_dig_port->ddi_io_power_domain =
2858 POWER_DOMAIN_PORT_DDI_C_IO;
2859 break;
2860 case PORT_D:
2861 intel_dig_port->ddi_io_power_domain =
2862 POWER_DOMAIN_PORT_DDI_D_IO;
2863 break;
2864 case PORT_E:
2865 intel_dig_port->ddi_io_power_domain =
2866 POWER_DOMAIN_PORT_DDI_E_IO;
2867 break;
2868 default:
2869 MISSING_CASE(port);
2870 }
2871
2872 /*
2873 * Some BIOS might fail to set this bit on port A if eDP
2874 * wasn't lit up at boot. Force this bit set when needed
2875 * so we use the proper lane count for our calculations.
2876 */
2877 if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
2878 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
2879 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2880 max_lanes = 4;
2881 }
2882
2883 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2884 intel_dig_port->max_lanes = max_lanes;
2885
2886 intel_encoder->type = INTEL_OUTPUT_DDI;
2887 intel_encoder->power_domain = intel_port_to_power_domain(port);
2888 intel_encoder->port = port;
2889 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2890 intel_encoder->cloneable = 0;
2891
2892 intel_infoframe_init(intel_dig_port);
2893
2894 if (init_dp) {
2895 if (!intel_ddi_init_dp_connector(intel_dig_port))
2896 goto err;
2897
2898 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2899 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2900 }
2901
2902 /* In theory we don't need the encoder->type check, but leave it just in
2903 * case we have some really bad VBTs... */
2904 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2905 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2906 goto err;
2907 }
2908
2909 if (init_lspcon) {
2910 if (lspcon_init(intel_dig_port))
2911 /* TODO: handle hdmi info frame part */
2912 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2913 port_name(port));
2914 else
2915 /*
2916 * LSPCON init faied, but DP init was success, so
2917 * lets try to drive as DP++ port.
2918 */
2919 DRM_ERROR("LSPCON init failed on port %c\n",
2920 port_name(port));
2921 }
2922
2923 return;
2924
2925 err:
2926 drm_encoder_cleanup(encoder);
2927 kfree(intel_dig_port);
2928 }
Linux with added FPC-III support