drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47
  48         struct notifier_block lid_notifier;
  49 };
  50
  51 struct intel_lvds_pps {
  52         /* 100us units */
  53         int t1_t2;
  54         int t3;
  55         int t4;
  56         int t5;
  57         int tx;
  58
  59         int divider;
  60
  61         int port;
  62         bool powerdown_on_reset;
  63 };
  64
  65 struct intel_lvds_encoder {
  66         struct intel_encoder base;
  67
  68         bool is_dual_link;
  69         i915_reg_t reg;
  70         u32 a3_power;
  71
  72         struct intel_lvds_pps init_pps;
  73         u32 init_lvds_val;
  74
  75         struct intel_lvds_connector *attached_connector;
  76 };
  77
  78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  79 {
  80         return container_of(encoder, struct intel_lvds_encoder, base.base);
  81 }
  82
  83 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  84 {
  85         return container_of(connector, struct intel_lvds_connector, base.base);
  86 }
  87
  88 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  89                                     enum pipe *pipe)
  90 {
  91         struct drm_device *dev = encoder->base.dev;
  92         struct drm_i915_private *dev_priv = to_i915(dev);
  93         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  94         u32 tmp;
  95         bool ret;
  96
  97         if (!intel_display_power_get_if_enabled(dev_priv,
  98                                                 encoder->power_domain))
  99                 return false;
 100
 101         ret = false;
 102
 103         tmp = I915_READ(lvds_encoder->reg);
 104
 105         if (!(tmp & LVDS_PORT_EN))
 106                 goto out;
 107
 108         if (HAS_PCH_CPT(dev_priv))
 109                 *pipe = PORT_TO_PIPE_CPT(tmp);
 110         else
 111                 *pipe = PORT_TO_PIPE(tmp);
 112
 113         ret = true;
 114
 115 out:
 116         intel_display_power_put(dev_priv, encoder->power_domain);
 117
 118         return ret;
 119 }
 120
 121 static void intel_lvds_get_config(struct intel_encoder *encoder,
 122                                   struct intel_crtc_state *pipe_config)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 125         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 126         u32 tmp, flags = 0;
 127
 128         pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 129
 130         tmp = I915_READ(lvds_encoder->reg);
 131         if (tmp & LVDS_HSYNC_POLARITY)
 132                 flags |= DRM_MODE_FLAG_NHSYNC;
 133         else
 134                 flags |= DRM_MODE_FLAG_PHSYNC;
 135         if (tmp & LVDS_VSYNC_POLARITY)
 136                 flags |= DRM_MODE_FLAG_NVSYNC;
 137         else
 138                 flags |= DRM_MODE_FLAG_PVSYNC;
 139
 140         pipe_config->base.adjusted_mode.flags |= flags;
 141
 142         if (INTEL_GEN(dev_priv) < 5)
 143                 pipe_config->gmch_pfit.lvds_border_bits =
 144                         tmp & LVDS_BORDER_ENABLE;
 145
 146         /* gen2/3 store dither state in pfit control, needs to match */
 147         if (INTEL_GEN(dev_priv) < 4) {
 148                 tmp = I915_READ(PFIT_CONTROL);
 149
 150                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 151         }
 152
 153         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 154 }
 155
 156 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 157                                         struct intel_lvds_pps *pps)
 158 {
 159         u32 val;
 160
 161         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 162
 163         val = I915_READ(PP_ON_DELAYS(0));
 164         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 165                     PANEL_PORT_SELECT_SHIFT;
 166         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 167                      PANEL_POWER_UP_DELAY_SHIFT;
 168         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 169                   PANEL_LIGHT_ON_DELAY_SHIFT;
 170
 171         val = I915_READ(PP_OFF_DELAYS(0));
 172         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 173                   PANEL_POWER_DOWN_DELAY_SHIFT;
 174         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 175                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 176
 177         val = I915_READ(PP_DIVISOR(0));
 178         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 179                        PP_REFERENCE_DIVIDER_SHIFT;
 180         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 181               PANEL_POWER_CYCLE_DELAY_SHIFT;
 182         /*
 183          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 184          * too short power-cycle delay due to the asynchronous programming of
 185          * the register.
 186          */
 187         if (val)
 188                 val--;
 189         /* Convert from 100ms to 100us units */
 190         pps->t4 = val * 1000;
 191
 192         if (INTEL_INFO(dev_priv)->gen <= 4 &&
 193             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 194                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 195                               "setting defaults\n");
 196                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 197                 pps->t1_t2 = 40 * 10;
 198                 pps->t5 = 200 * 10;
 199                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 200                 pps->t3 = 35 * 10;
 201                 pps->tx = 200 * 10;
 202         }
 203
 204         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 205                          "divider %d port %d powerdown_on_reset %d\n",
 206                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 207                          pps->divider, pps->port, pps->powerdown_on_reset);
 208 }
 209
 210 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 211                                    struct intel_lvds_pps *pps)
 212 {
 213         u32 val;
 214
 215         val = I915_READ(PP_CONTROL(0));
 216         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 217         if (pps->powerdown_on_reset)
 218                 val |= PANEL_POWER_RESET;
 219         I915_WRITE(PP_CONTROL(0), val);
 220
 221         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 222                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 223                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 224         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 225                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 226
 227         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 228         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 229                PANEL_POWER_CYCLE_DELAY_SHIFT;
 230         I915_WRITE(PP_DIVISOR(0), val);
 231 }
 232
 233 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 234                                   const struct intel_crtc_state *pipe_config,
 235                                   const struct drm_connector_state *conn_state)
 236 {
 237         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 239         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 240         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 241         int pipe = crtc->pipe;
 242         u32 temp;
 243
 244         if (HAS_PCH_SPLIT(dev_priv)) {
 245                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 246                 assert_shared_dpll_disabled(dev_priv,
 247                                             pipe_config->shared_dpll);
 248         } else {
 249                 assert_pll_disabled(dev_priv, pipe);
 250         }
 251
 252         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 253
 254         temp = lvds_encoder->init_lvds_val;
 255         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 256
 257         if (HAS_PCH_CPT(dev_priv)) {
 258                 temp &= ~PORT_TRANS_SEL_MASK;
 259                 temp |= PORT_TRANS_SEL_CPT(pipe);
 260         } else {
 261                 if (pipe == 1) {
 262                         temp |= LVDS_PIPEB_SELECT;
 263                 } else {
 264                         temp &= ~LVDS_PIPEB_SELECT;
 265                 }
 266         }
 267
 268         /* set the corresponsding LVDS_BORDER bit */
 269         temp &= ~LVDS_BORDER_ENABLE;
 270         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 271         /* Set the B0-B3 data pairs corresponding to whether we're going to
 272          * set the DPLLs for dual-channel mode or not.
 273          */
 274         if (lvds_encoder->is_dual_link)
 275                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 276         else
 277                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 278
 279         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 280          * appropriately here, but we need to look more thoroughly into how
 281          * panels behave in the two modes. For now, let's just maintain the
 282          * value we got from the BIOS.
 283          */
 284         temp &= ~LVDS_A3_POWER_MASK;
 285         temp |= lvds_encoder->a3_power;
 286
 287         /* Set the dithering flag on LVDS as needed, note that there is no
 288          * special lvds dither control bit on pch-split platforms, dithering is
 289          * only controlled through the PIPECONF reg. */
 290         if (IS_GEN4(dev_priv)) {
 291                 /* Bspec wording suggests that LVDS port dithering only exists
 292                  * for 18bpp panels. */
 293                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 294                         temp |= LVDS_ENABLE_DITHER;
 295                 else
 296                         temp &= ~LVDS_ENABLE_DITHER;
 297         }
 298         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 299         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 300                 temp |= LVDS_HSYNC_POLARITY;
 301         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 302                 temp |= LVDS_VSYNC_POLARITY;
 303
 304         I915_WRITE(lvds_encoder->reg, temp);
 305 }
 306
 307 /**
 308  * Sets the power state for the panel.
 309  */
 310 static void intel_enable_lvds(struct intel_encoder *encoder,
 311                               const struct intel_crtc_state *pipe_config,
 312                               const struct drm_connector_state *conn_state)
 313 {
 314         struct drm_device *dev = encoder->base.dev;
 315         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 316         struct drm_i915_private *dev_priv = to_i915(dev);
 317
 318         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 319
 320         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 321         POSTING_READ(lvds_encoder->reg);
 322
 323         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
 324                 DRM_ERROR("timed out waiting for panel to power on\n");
 325
 326         intel_panel_enable_backlight(pipe_config, conn_state);
 327 }
 328
 329 static void intel_disable_lvds(struct intel_encoder *encoder,
 330                                const struct intel_crtc_state *old_crtc_state,
 331                                const struct drm_connector_state *old_conn_state)
 332 {
 333         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 334         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 335
 336         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 337         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 338                 DRM_ERROR("timed out waiting for panel to power off\n");
 339
 340         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 341         POSTING_READ(lvds_encoder->reg);
 342 }
 343
 344 static void gmch_disable_lvds(struct intel_encoder *encoder,
 345                               const struct intel_crtc_state *old_crtc_state,
 346                               const struct drm_connector_state *old_conn_state)
 347
 348 {
 349         intel_panel_disable_backlight(old_conn_state);
 350
 351         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 352 }
 353
 354 static void pch_disable_lvds(struct intel_encoder *encoder,
 355                              const struct intel_crtc_state *old_crtc_state,
 356                              const struct drm_connector_state *old_conn_state)
 357 {
 358         intel_panel_disable_backlight(old_conn_state);
 359 }
 360
 361 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 362                                   const struct intel_crtc_state *old_crtc_state,
 363                                   const struct drm_connector_state *old_conn_state)
 364 {
 365         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 366 }
 367
 368 static enum drm_mode_status
 369 intel_lvds_mode_valid(struct drm_connector *connector,
 370                       struct drm_display_mode *mode)
 371 {
 372         struct intel_connector *intel_connector = to_intel_connector(connector);
 373         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 374         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 375
 376         if (mode->hdisplay > fixed_mode->hdisplay)
 377                 return MODE_PANEL;
 378         if (mode->vdisplay > fixed_mode->vdisplay)
 379                 return MODE_PANEL;
 380         if (fixed_mode->clock > max_pixclk)
 381                 return MODE_CLOCK_HIGH;
 382
 383         return MODE_OK;
 384 }
 385
 386 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 387                                       struct intel_crtc_state *pipe_config,
 388                                       struct drm_connector_state *conn_state)
 389 {
 390         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 391         struct intel_lvds_encoder *lvds_encoder =
 392                 to_lvds_encoder(&intel_encoder->base);
 393         struct intel_connector *intel_connector =
 394                 &lvds_encoder->attached_connector->base;
 395         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 396         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 397         unsigned int lvds_bpp;
 398
 399         /* Should never happen!! */
 400         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 401                 DRM_ERROR("Can't support LVDS on pipe A\n");
 402                 return false;
 403         }
 404
 405         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 406                 lvds_bpp = 8*3;
 407         else
 408                 lvds_bpp = 6*3;
 409
 410         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 411                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 412                               pipe_config->pipe_bpp, lvds_bpp);
 413                 pipe_config->pipe_bpp = lvds_bpp;
 414         }
 415
 416         /*
 417          * We have timings from the BIOS for the panel, put them in
 418          * to the adjusted mode.  The CRTC will be set up for this mode,
 419          * with the panel scaling set up to source from the H/VDisplay
 420          * of the original mode.
 421          */
 422         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 423                                adjusted_mode);
 424
 425         if (HAS_PCH_SPLIT(dev_priv)) {
 426                 pipe_config->has_pch_encoder = true;
 427
 428                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 429                                         conn_state->scaling_mode);
 430         } else {
 431                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 432                                          conn_state->scaling_mode);
 433
 434         }
 435
 436         /*
 437          * XXX: It would be nice to support lower refresh rates on the
 438          * panels to reduce power consumption, and perhaps match the
 439          * user's requested refresh rate.
 440          */
 441
 442         return true;
 443 }
 444
 445 /**
 446  * Detect the LVDS connection.
 447  *
 448  * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means
 449  * connected and closed means disconnected.  We also send hotplug events as
 450  * needed, using lid status notification from the input layer.
 451  */
 452 static enum drm_connector_status
 453 intel_lvds_detect(struct drm_connector *connector, bool force)
 454 {
 455         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 456         enum drm_connector_status status;
 457
 458         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 459                       connector->base.id, connector->name);
 460
 461         status = intel_panel_detect(dev_priv);
 462         if (status != connector_status_unknown)
 463                 return status;
 464
 465         return connector_status_connected;
 466 }
 467
 468 /**
 469  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 470  */
 471 static int intel_lvds_get_modes(struct drm_connector *connector)
 472 {
 473         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 474         struct drm_device *dev = connector->dev;
 475         struct drm_display_mode *mode;
 476
 477         /* use cached edid if we have one */
 478         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 479                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 480
 481         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 482         if (mode == NULL)
 483                 return 0;
 484
 485         drm_mode_probed_add(connector, mode);
 486         return 1;
 487 }
 488
 489 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
 490 {
 491         DRM_INFO("Skipping forced modeset for %s\n", id->ident);
 492         return 1;
 493 }
 494
 495 /* The GPU hangs up on these systems if modeset is performed on LID open */
 496 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
 497         {
 498                 .callback = intel_no_modeset_on_lid_dmi_callback,
 499                 .ident = "Toshiba Tecra A11",
 500                 .matches = {
 501                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 502                         DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
 503                 },
 504         },
 505
 506         { }     /* terminating entry */
 507 };
 508
 509 /*
 510  * Lid events. Note the use of 'modeset':
 511  *  - we set it to MODESET_ON_LID_OPEN on lid close,
 512  *    and set it to MODESET_DONE on open
 513  *  - we use it as a "only once" bit (ie we ignore
 514  *    duplicate events where it was already properly set)
 515  *  - the suspend/resume paths will set it to
 516  *    MODESET_SUSPENDED and ignore the lid open event,
 517  *    because they restore the mode ("lid open").
 518  */
 519 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
 520                             void *unused)
 521 {
 522         struct intel_lvds_connector *lvds_connector =
 523                 container_of(nb, struct intel_lvds_connector, lid_notifier);
 524         struct drm_connector *connector = &lvds_connector->base.base;
 525         struct drm_device *dev = connector->dev;
 526         struct drm_i915_private *dev_priv = to_i915(dev);
 527
 528         if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
 529                 return NOTIFY_OK;
 530
 531         mutex_lock(&dev_priv->modeset_restore_lock);
 532         if (dev_priv->modeset_restore == MODESET_SUSPENDED)
 533                 goto exit;
 534         /*
 535          * check and update the status of LVDS connector after receiving
 536          * the LID nofication event.
 537          */
 538         connector->status = connector->funcs->detect(connector, false);
 539
 540         /* Don't force modeset on machines where it causes a GPU lockup */
 541         if (dmi_check_system(intel_no_modeset_on_lid))
 542                 goto exit;
 543         if (!acpi_lid_open()) {
 544                 /* do modeset on next lid open event */
 545                 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
 546                 goto exit;
 547         }
 548
 549         if (dev_priv->modeset_restore == MODESET_DONE)
 550                 goto exit;
 551
 552         /*
 553          * Some old platform's BIOS love to wreak havoc while the lid is closed.
 554          * We try to detect this here and undo any damage. The split for PCH
 555          * platforms is rather conservative and a bit arbitrary expect that on
 556          * those platforms VGA disabling requires actual legacy VGA I/O access,
 557          * and as part of the cleanup in the hw state restore we also redisable
 558          * the vga plane.
 559          */
 560         if (!HAS_PCH_SPLIT(dev_priv))
 561                 intel_display_resume(dev);
 562
 563         dev_priv->modeset_restore = MODESET_DONE;
 564
 565 exit:
 566         mutex_unlock(&dev_priv->modeset_restore_lock);
 567         return NOTIFY_OK;
 568 }
 569
 570 /**
 571  * intel_lvds_destroy - unregister and free LVDS structures
 572  * @connector: connector to free
 573  *
 574  * Unregister the DDC bus for this connector then free the driver private
 575  * structure.
 576  */
 577 static void intel_lvds_destroy(struct drm_connector *connector)
 578 {
 579         struct intel_lvds_connector *lvds_connector =
 580                 to_lvds_connector(connector);
 581
 582         if (lvds_connector->lid_notifier.notifier_call)
 583                 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
 584
 585         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 586                 kfree(lvds_connector->base.edid);
 587
 588         intel_panel_fini(&lvds_connector->base.panel);
 589
 590         drm_connector_cleanup(connector);
 591         kfree(connector);
 592 }
 593
 594 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 595         .get_modes = intel_lvds_get_modes,
 596         .mode_valid = intel_lvds_mode_valid,
 597         .atomic_check = intel_digital_connector_atomic_check,
 598 };
 599
 600 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 601         .detect = intel_lvds_detect,
 602         .fill_modes = drm_helper_probe_single_connector_modes,
 603         .atomic_get_property = intel_digital_connector_atomic_get_property,
 604         .atomic_set_property = intel_digital_connector_atomic_set_property,
 605         .late_register = intel_connector_register,
 606         .early_unregister = intel_connector_unregister,
 607         .destroy = intel_lvds_destroy,
 608         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 609         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 610 };
 611
 612 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 613         .destroy = intel_encoder_destroy,
 614 };
 615
 616 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 617 {
 618         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 619         return 1;
 620 }
 621
 622 /* These systems claim to have LVDS, but really don't */
 623 static const struct dmi_system_id intel_no_lvds[] = {
 624         {
 625                 .callback = intel_no_lvds_dmi_callback,
 626                 .ident = "Apple Mac Mini (Core series)",
 627                 .matches = {
 628                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 629                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 630                 },
 631         },
 632         {
 633                 .callback = intel_no_lvds_dmi_callback,
 634                 .ident = "Apple Mac Mini (Core 2 series)",
 635                 .matches = {
 636                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 637                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 638                 },
 639         },
 640         {
 641                 .callback = intel_no_lvds_dmi_callback,
 642                 .ident = "MSI IM-945GSE-A",
 643                 .matches = {
 644                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 645                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 646                 },
 647         },
 648         {
 649                 .callback = intel_no_lvds_dmi_callback,
 650                 .ident = "Dell Studio Hybrid",
 651                 .matches = {
 652                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 653                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 654                 },
 655         },
 656         {
 657                 .callback = intel_no_lvds_dmi_callback,
 658                 .ident = "Dell OptiPlex FX170",
 659                 .matches = {
 660                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 661                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 662                 },
 663         },
 664         {
 665                 .callback = intel_no_lvds_dmi_callback,
 666                 .ident = "AOpen Mini PC",
 667                 .matches = {
 668                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 669                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 670                 },
 671         },
 672         {
 673                 .callback = intel_no_lvds_dmi_callback,
 674                 .ident = "AOpen Mini PC MP915",
 675                 .matches = {
 676                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 677                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 678                 },
 679         },
 680         {
 681                 .callback = intel_no_lvds_dmi_callback,
 682                 .ident = "AOpen i915GMm-HFS",
 683                 .matches = {
 684                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 685                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 686                 },
 687         },
 688         {
 689                 .callback = intel_no_lvds_dmi_callback,
 690                 .ident = "AOpen i45GMx-I",
 691                 .matches = {
 692                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 693                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 694                 },
 695         },
 696         {
 697                 .callback = intel_no_lvds_dmi_callback,
 698                 .ident = "Aopen i945GTt-VFA",
 699                 .matches = {
 700                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 701                 },
 702         },
 703         {
 704                 .callback = intel_no_lvds_dmi_callback,
 705                 .ident = "Clientron U800",
 706                 .matches = {
 707                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 708                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 709                 },
 710         },
 711         {
 712                 .callback = intel_no_lvds_dmi_callback,
 713                 .ident = "Clientron E830",
 714                 .matches = {
 715                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 716                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 717                 },
 718         },
 719         {
 720                 .callback = intel_no_lvds_dmi_callback,
 721                 .ident = "Asus EeeBox PC EB1007",
 722                 .matches = {
 723                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 724                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 725                 },
 726         },
 727         {
 728                 .callback = intel_no_lvds_dmi_callback,
 729                 .ident = "Asus AT5NM10T-I",
 730                 .matches = {
 731                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 732                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 733                 },
 734         },
 735         {
 736                 .callback = intel_no_lvds_dmi_callback,
 737                 .ident = "Hewlett-Packard HP t5740",
 738                 .matches = {
 739                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 740                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 741                 },
 742         },
 743         {
 744                 .callback = intel_no_lvds_dmi_callback,
 745                 .ident = "Hewlett-Packard t5745",
 746                 .matches = {
 747                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 748                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 749                 },
 750         },
 751         {
 752                 .callback = intel_no_lvds_dmi_callback,
 753                 .ident = "Hewlett-Packard st5747",
 754                 .matches = {
 755                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 756                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 757                 },
 758         },
 759         {
 760                 .callback = intel_no_lvds_dmi_callback,
 761                 .ident = "MSI Wind Box DC500",
 762                 .matches = {
 763                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 764                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 765                 },
 766         },
 767         {
 768                 .callback = intel_no_lvds_dmi_callback,
 769                 .ident = "Gigabyte GA-D525TUD",
 770                 .matches = {
 771                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 772                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 773                 },
 774         },
 775         {
 776                 .callback = intel_no_lvds_dmi_callback,
 777                 .ident = "Supermicro X7SPA-H",
 778                 .matches = {
 779                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 780                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 781                 },
 782         },
 783         {
 784                 .callback = intel_no_lvds_dmi_callback,
 785                 .ident = "Fujitsu Esprimo Q900",
 786                 .matches = {
 787                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 788                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 789                 },
 790         },
 791         {
 792                 .callback = intel_no_lvds_dmi_callback,
 793                 .ident = "Intel D410PT",
 794                 .matches = {
 795                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 796                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 797                 },
 798         },
 799         {
 800                 .callback = intel_no_lvds_dmi_callback,
 801                 .ident = "Intel D425KT",
 802                 .matches = {
 803                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 804                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 805                 },
 806         },
 807         {
 808                 .callback = intel_no_lvds_dmi_callback,
 809                 .ident = "Intel D510MO",
 810                 .matches = {
 811                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 812                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 813                 },
 814         },
 815         {
 816                 .callback = intel_no_lvds_dmi_callback,
 817                 .ident = "Intel D525MW",
 818                 .matches = {
 819                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 820                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 821                 },
 822         },
 823
 824         { }     /* terminating entry */
 825 };
 826
 827 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 828 {
 829         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 830         return 1;
 831 }
 832
 833 static const struct dmi_system_id intel_dual_link_lvds[] = {
 834         {
 835                 .callback = intel_dual_link_lvds_callback,
 836                 .ident = "Apple MacBook Pro 15\" (2010)",
 837                 .matches = {
 838                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 839                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 840                 },
 841         },
 842         {
 843                 .callback = intel_dual_link_lvds_callback,
 844                 .ident = "Apple MacBook Pro 15\" (2011)",
 845                 .matches = {
 846                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 847                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 848                 },
 849         },
 850         {
 851                 .callback = intel_dual_link_lvds_callback,
 852                 .ident = "Apple MacBook Pro 15\" (2012)",
 853                 .matches = {
 854                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 855                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 856                 },
 857         },
 858         { }     /* terminating entry */
 859 };
 860
 861 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 862 {
 863         struct intel_encoder *intel_encoder;
 864
 865         for_each_intel_encoder(dev, intel_encoder)
 866                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 867                         return intel_encoder;
 868
 869         return NULL;
 870 }
 871
 872 bool intel_is_dual_link_lvds(struct drm_device *dev)
 873 {
 874         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 875
 876         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 877 }
 878
 879 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 880 {
 881         struct drm_device *dev = lvds_encoder->base.base.dev;
 882         unsigned int val;
 883         struct drm_i915_private *dev_priv = to_i915(dev);
 884
 885         /* use the module option value if specified */
 886         if (i915_modparams.lvds_channel_mode > 0)
 887                 return i915_modparams.lvds_channel_mode == 2;
 888
 889         /* single channel LVDS is limited to 112 MHz */
 890         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 891             > 112999)
 892                 return true;
 893
 894         if (dmi_check_system(intel_dual_link_lvds))
 895                 return true;
 896
 897         /* BIOS should set the proper LVDS register value at boot, but
 898          * in reality, it doesn't set the value when the lid is closed;
 899          * we need to check "the value to be set" in VBT when LVDS
 900          * register is uninitialized.
 901          */
 902         val = I915_READ(lvds_encoder->reg);
 903         if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 904                 val = dev_priv->vbt.bios_lvds_val;
 905
 906         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 907 }
 908
 909 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 910 {
 911         /* With the introduction of the PCH we gained a dedicated
 912          * LVDS presence pin, use it. */
 913         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 914                 return true;
 915
 916         /* Otherwise LVDS was only attached to mobile products,
 917          * except for the inglorious 830gm */
 918         if (INTEL_GEN(dev_priv) <= 4 &&
 919             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 920                 return true;
 921
 922         return false;
 923 }
 924
 925 /**
 926  * intel_lvds_init - setup LVDS connectors on this device
 927  * @dev: drm device
 928  *
 929  * Create the connector, register the LVDS DDC bus, and try to figure out what
 930  * modes we can display on the LVDS panel (if present).
 931  */
 932 void intel_lvds_init(struct drm_i915_private *dev_priv)
 933 {
 934         struct drm_device *dev = &dev_priv->drm;
 935         struct intel_lvds_encoder *lvds_encoder;
 936         struct intel_encoder *intel_encoder;
 937         struct intel_lvds_connector *lvds_connector;
 938         struct intel_connector *intel_connector;
 939         struct drm_connector *connector;
 940         struct drm_encoder *encoder;
 941         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 942         struct drm_display_mode *fixed_mode = NULL;
 943         struct drm_display_mode *downclock_mode = NULL;
 944         struct edid *edid;
 945         i915_reg_t lvds_reg;
 946         u32 lvds;
 947         u8 pin;
 948         u32 allowed_scalers;
 949
 950         if (!intel_lvds_supported(dev_priv))
 951                 return;
 952
 953         /* Skip init on machines we know falsely report LVDS */
 954         if (dmi_check_system(intel_no_lvds))
 955                 return;
 956
 957         if (HAS_PCH_SPLIT(dev_priv))
 958                 lvds_reg = PCH_LVDS;
 959         else
 960                 lvds_reg = LVDS;
 961
 962         lvds = I915_READ(lvds_reg);
 963
 964         if (HAS_PCH_SPLIT(dev_priv)) {
 965                 if ((lvds & LVDS_DETECTED) == 0)
 966                         return;
 967                 if (dev_priv->vbt.edp.support) {
 968                         DRM_DEBUG_KMS("disable LVDS for eDP support\n");
 969                         return;
 970                 }
 971         }
 972
 973         pin = GMBUS_PIN_PANEL;
 974         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 975                 if ((lvds & LVDS_PORT_EN) == 0) {
 976                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 977                         return;
 978                 }
 979                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
 980         }
 981
 982         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 983         if (!lvds_encoder)
 984                 return;
 985
 986         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
 987         if (!lvds_connector) {
 988                 kfree(lvds_encoder);
 989                 return;
 990         }
 991
 992         if (intel_connector_init(&lvds_connector->base) < 0) {
 993                 kfree(lvds_connector);
 994                 kfree(lvds_encoder);
 995                 return;
 996         }
 997
 998         lvds_encoder->attached_connector = lvds_connector;
 999
1000         intel_encoder = &lvds_encoder->base;
1001         encoder = &intel_encoder->base;
1002         intel_connector = &lvds_connector->base;
1003         connector = &intel_connector->base;
1004         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1005                            DRM_MODE_CONNECTOR_LVDS);
1006
1007         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1008                          DRM_MODE_ENCODER_LVDS, "LVDS");
1009
1010         intel_encoder->enable = intel_enable_lvds;
1011         intel_encoder->pre_enable = intel_pre_enable_lvds;
1012         intel_encoder->compute_config = intel_lvds_compute_config;
1013         if (HAS_PCH_SPLIT(dev_priv)) {
1014                 intel_encoder->disable = pch_disable_lvds;
1015                 intel_encoder->post_disable = pch_post_disable_lvds;
1016         } else {
1017                 intel_encoder->disable = gmch_disable_lvds;
1018         }
1019         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1020         intel_encoder->get_config = intel_lvds_get_config;
1021         intel_connector->get_hw_state = intel_connector_get_hw_state;
1022
1023         intel_connector_attach_encoder(intel_connector, intel_encoder);
1024
1025         intel_encoder->type = INTEL_OUTPUT_LVDS;
1026         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1027         intel_encoder->port = PORT_NONE;
1028         intel_encoder->cloneable = 0;
1029         if (HAS_PCH_SPLIT(dev_priv))
1030                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1031         else if (IS_GEN4(dev_priv))
1032                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1033         else
1034                 intel_encoder->crtc_mask = (1 << 1);
1035
1036         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1037         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1038         connector->interlace_allowed = false;
1039         connector->doublescan_allowed = false;
1040
1041         lvds_encoder->reg = lvds_reg;
1042
1043         /* create the scaling mode property */
1044         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
1045         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
1046         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1047         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
1048         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1049
1050         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
1051         lvds_encoder->init_lvds_val = lvds;
1052
1053         /*
1054          * LVDS discovery:
1055          * 1) check for EDID on DDC
1056          * 2) check for VBT data
1057          * 3) check to see if LVDS is already on
1058          *    if none of the above, no panel
1059          * 4) make sure lid is open
1060          *    if closed, act like it's not there for now
1061          */
1062
1063         /*
1064          * Attempt to get the fixed panel mode from DDC.  Assume that the
1065          * preferred mode is the right one.
1066          */
1067         mutex_lock(&dev->mode_config.mutex);
1068         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1069                 edid = drm_get_edid_switcheroo(connector,
1070                                     intel_gmbus_get_adapter(dev_priv, pin));
1071         else
1072                 edid = drm_get_edid(connector,
1073                                     intel_gmbus_get_adapter(dev_priv, pin));
1074         if (edid) {
1075                 if (drm_add_edid_modes(connector, edid)) {
1076                         drm_mode_connector_update_edid_property(connector,
1077                                                                 edid);
1078                 } else {
1079                         kfree(edid);
1080                         edid = ERR_PTR(-EINVAL);
1081                 }
1082         } else {
1083                 edid = ERR_PTR(-ENOENT);
1084         }
1085         lvds_connector->base.edid = edid;
1086
1087         list_for_each_entry(scan, &connector->probed_modes, head) {
1088                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1089                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
1090                         drm_mode_debug_printmodeline(scan);
1091
1092                         fixed_mode = drm_mode_duplicate(dev, scan);
1093                         if (fixed_mode)
1094                                 goto out;
1095                 }
1096         }
1097
1098         /* Failed to get EDID, what about VBT? */
1099         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1100                 DRM_DEBUG_KMS("using mode from VBT: ");
1101                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1102
1103                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1104                 if (fixed_mode) {
1105                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1106                         connector->display_info.width_mm = fixed_mode->width_mm;
1107                         connector->display_info.height_mm = fixed_mode->height_mm;
1108                         goto out;
1109                 }
1110         }
1111
1112         /*
1113          * If we didn't get EDID, try checking if the panel is already turned
1114          * on.  If so, assume that whatever is currently programmed is the
1115          * correct mode.
1116          */
1117         fixed_mode = intel_encoder_current_mode(intel_encoder);
1118         if (fixed_mode) {
1119                 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1120                 drm_mode_debug_printmodeline(fixed_mode);
1121                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1122         }
1123
1124         /* If we still don't have a mode after all that, give up. */
1125         if (!fixed_mode)
1126                 goto failed;
1127
1128 out:
1129         mutex_unlock(&dev->mode_config.mutex);
1130
1131         intel_panel_init(&intel_connector->panel, fixed_mode, NULL,
1132                          downclock_mode);
1133         intel_panel_setup_backlight(connector, INVALID_PIPE);
1134
1135         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1136         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1137                       lvds_encoder->is_dual_link ? "dual" : "single");
1138
1139         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1140
1141         lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1142         if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
1143                 DRM_DEBUG_KMS("lid notifier registration failed\n");
1144                 lvds_connector->lid_notifier.notifier_call = NULL;
1145         }
1146
1147         return;
1148
1149 failed:
1150         mutex_unlock(&dev->mode_config.mutex);
1151
1152         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1153         drm_connector_cleanup(connector);
1154         drm_encoder_cleanup(encoder);
1155         kfree(lvds_encoder);
1156         kfree(lvds_connector);
1157         return;
1158 }