bpf: Prevent memory disambiguation attack
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
blob9faee4875ddf8becf4a43decee49bbe8c2248e9e
1 /*
2 * Copyright © 2012-2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
32 #include "i915_drv.h"
33 #include "intel_drv.h"
35 /**
36 * DOC: runtime pm
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
53 enum i915_power_well_id power_well_id);
55 static struct i915_power_well *
56 lookup_power_well(struct drm_i915_private *dev_priv,
57 enum i915_power_well_id power_well_id);
59 const char *
60 intel_display_power_domain_str(enum intel_display_power_domain domain)
62 switch (domain) {
63 case POWER_DOMAIN_PIPE_A:
64 return "PIPE_A";
65 case POWER_DOMAIN_PIPE_B:
66 return "PIPE_B";
67 case POWER_DOMAIN_PIPE_C:
68 return "PIPE_C";
69 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
70 return "PIPE_A_PANEL_FITTER";
71 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
72 return "PIPE_B_PANEL_FITTER";
73 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
74 return "PIPE_C_PANEL_FITTER";
75 case POWER_DOMAIN_TRANSCODER_A:
76 return "TRANSCODER_A";
77 case POWER_DOMAIN_TRANSCODER_B:
78 return "TRANSCODER_B";
79 case POWER_DOMAIN_TRANSCODER_C:
80 return "TRANSCODER_C";
81 case POWER_DOMAIN_TRANSCODER_EDP:
82 return "TRANSCODER_EDP";
83 case POWER_DOMAIN_TRANSCODER_DSI_A:
84 return "TRANSCODER_DSI_A";
85 case POWER_DOMAIN_TRANSCODER_DSI_C:
86 return "TRANSCODER_DSI_C";
87 case POWER_DOMAIN_PORT_DDI_A_LANES:
88 return "PORT_DDI_A_LANES";
89 case POWER_DOMAIN_PORT_DDI_B_LANES:
90 return "PORT_DDI_B_LANES";
91 case POWER_DOMAIN_PORT_DDI_C_LANES:
92 return "PORT_DDI_C_LANES";
93 case POWER_DOMAIN_PORT_DDI_D_LANES:
94 return "PORT_DDI_D_LANES";
95 case POWER_DOMAIN_PORT_DDI_E_LANES:
96 return "PORT_DDI_E_LANES";
97 case POWER_DOMAIN_PORT_DDI_A_IO:
98 return "PORT_DDI_A_IO";
99 case POWER_DOMAIN_PORT_DDI_B_IO:
100 return "PORT_DDI_B_IO";
101 case POWER_DOMAIN_PORT_DDI_C_IO:
102 return "PORT_DDI_C_IO";
103 case POWER_DOMAIN_PORT_DDI_D_IO:
104 return "PORT_DDI_D_IO";
105 case POWER_DOMAIN_PORT_DDI_E_IO:
106 return "PORT_DDI_E_IO";
107 case POWER_DOMAIN_PORT_DSI:
108 return "PORT_DSI";
109 case POWER_DOMAIN_PORT_CRT:
110 return "PORT_CRT";
111 case POWER_DOMAIN_PORT_OTHER:
112 return "PORT_OTHER";
113 case POWER_DOMAIN_VGA:
114 return "VGA";
115 case POWER_DOMAIN_AUDIO:
116 return "AUDIO";
117 case POWER_DOMAIN_PLLS:
118 return "PLLS";
119 case POWER_DOMAIN_AUX_A:
120 return "AUX_A";
121 case POWER_DOMAIN_AUX_B:
122 return "AUX_B";
123 case POWER_DOMAIN_AUX_C:
124 return "AUX_C";
125 case POWER_DOMAIN_AUX_D:
126 return "AUX_D";
127 case POWER_DOMAIN_GMBUS:
128 return "GMBUS";
129 case POWER_DOMAIN_INIT:
130 return "INIT";
131 case POWER_DOMAIN_MODESET:
132 return "MODESET";
133 case POWER_DOMAIN_GT_IRQ:
134 return "GT_IRQ";
135 default:
136 MISSING_CASE(domain);
137 return "?";
141 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
142 struct i915_power_well *power_well)
144 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
145 power_well->ops->enable(dev_priv, power_well);
146 power_well->hw_enabled = true;
149 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
150 struct i915_power_well *power_well)
152 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
153 power_well->hw_enabled = false;
154 power_well->ops->disable(dev_priv, power_well);
157 static void intel_power_well_get(struct drm_i915_private *dev_priv,
158 struct i915_power_well *power_well)
160 if (!power_well->count++)
161 intel_power_well_enable(dev_priv, power_well);
164 static void intel_power_well_put(struct drm_i915_private *dev_priv,
165 struct i915_power_well *power_well)
167 WARN(!power_well->count, "Use count on power well %s is already zero",
168 power_well->name);
170 if (!--power_well->count)
171 intel_power_well_disable(dev_priv, power_well);
175 * __intel_display_power_is_enabled - unlocked check for a power domain
176 * @dev_priv: i915 device instance
177 * @domain: power domain to check
179 * This is the unlocked version of intel_display_power_is_enabled() and should
180 * only be used from error capture and recovery code where deadlocks are
181 * possible.
183 * Returns:
184 * True when the power domain is enabled, false otherwise.
186 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
187 enum intel_display_power_domain domain)
189 struct i915_power_well *power_well;
190 bool is_enabled;
192 if (dev_priv->runtime_pm.suspended)
193 return false;
195 is_enabled = true;
197 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
198 if (power_well->always_on)
199 continue;
201 if (!power_well->hw_enabled) {
202 is_enabled = false;
203 break;
207 return is_enabled;
211 * intel_display_power_is_enabled - check for a power domain
212 * @dev_priv: i915 device instance
213 * @domain: power domain to check
215 * This function can be used to check the hw power domain state. It is mostly
216 * used in hardware state readout functions. Everywhere else code should rely
217 * upon explicit power domain reference counting to ensure that the hardware
218 * block is powered up before accessing it.
220 * Callers must hold the relevant modesetting locks to ensure that concurrent
221 * threads can't disable the power well while the caller tries to read a few
222 * registers.
224 * Returns:
225 * True when the power domain is enabled, false otherwise.
227 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
228 enum intel_display_power_domain domain)
230 struct i915_power_domains *power_domains;
231 bool ret;
233 power_domains = &dev_priv->power_domains;
235 mutex_lock(&power_domains->lock);
236 ret = __intel_display_power_is_enabled(dev_priv, domain);
237 mutex_unlock(&power_domains->lock);
239 return ret;
243 * intel_display_set_init_power - set the initial power domain state
244 * @dev_priv: i915 device instance
245 * @enable: whether to enable or disable the initial power domain state
247 * For simplicity our driver load/unload and system suspend/resume code assumes
248 * that all power domains are always enabled. This functions controls the state
249 * of this little hack. While the initial power domain state is enabled runtime
250 * pm is effectively disabled.
252 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
253 bool enable)
255 if (dev_priv->power_domains.init_power_on == enable)
256 return;
258 if (enable)
259 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
260 else
261 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
263 dev_priv->power_domains.init_power_on = enable;
267 * Starting with Haswell, we have a "Power Down Well" that can be turned off
268 * when not needed anymore. We have 4 registers that can request the power well
269 * to be enabled, and it will only be disabled if none of the registers is
270 * requesting it to be enabled.
272 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
273 u8 irq_pipe_mask, bool has_vga)
275 struct pci_dev *pdev = dev_priv->drm.pdev;
278 * After we re-enable the power well, if we touch VGA register 0x3d5
279 * we'll get unclaimed register interrupts. This stops after we write
280 * anything to the VGA MSR register. The vgacon module uses this
281 * register all the time, so if we unbind our driver and, as a
282 * consequence, bind vgacon, we'll get stuck in an infinite loop at
283 * console_unlock(). So make here we touch the VGA MSR register, making
284 * sure vgacon can keep working normally without triggering interrupts
285 * and error messages.
287 if (has_vga) {
288 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
289 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
290 vga_put(pdev, VGA_RSRC_LEGACY_IO);
293 if (irq_pipe_mask)
294 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
297 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
298 u8 irq_pipe_mask)
300 if (irq_pipe_mask)
301 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
305 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
306 struct i915_power_well *power_well)
308 enum i915_power_well_id id = power_well->id;
310 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
311 WARN_ON(intel_wait_for_register(dev_priv,
312 HSW_PWR_WELL_CTL_DRIVER(id),
313 HSW_PWR_WELL_CTL_STATE(id),
314 HSW_PWR_WELL_CTL_STATE(id),
315 1));
318 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
319 enum i915_power_well_id id)
321 u32 req_mask = HSW_PWR_WELL_CTL_REQ(id);
322 u32 ret;
324 ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0;
325 ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0;
326 ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0;
327 ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0;
329 return ret;
332 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
333 struct i915_power_well *power_well)
335 enum i915_power_well_id id = power_well->id;
336 bool disabled;
337 u32 reqs;
340 * Bspec doesn't require waiting for PWs to get disabled, but still do
341 * this for paranoia. The known cases where a PW will be forced on:
342 * - a KVMR request on any power well via the KVMR request register
343 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
344 * DEBUG request registers
345 * Skip the wait in case any of the request bits are set and print a
346 * diagnostic message.
348 wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &
349 HSW_PWR_WELL_CTL_STATE(id))) ||
350 (reqs = hsw_power_well_requesters(dev_priv, id)), 1);
351 if (disabled)
352 return;
354 DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
355 power_well->name,
356 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
359 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
360 enum skl_power_gate pg)
362 /* Timeout 5us for PG#0, for other PGs 1us */
363 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
364 SKL_FUSE_PG_DIST_STATUS(pg),
365 SKL_FUSE_PG_DIST_STATUS(pg), 1));
368 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
369 struct i915_power_well *power_well)
371 enum i915_power_well_id id = power_well->id;
372 bool wait_fuses = power_well->hsw.has_fuses;
373 enum skl_power_gate uninitialized_var(pg);
374 u32 val;
376 if (wait_fuses) {
377 pg = SKL_PW_TO_PG(id);
379 * For PW1 we have to wait both for the PW0/PG0 fuse state
380 * before enabling the power well and PW1/PG1's own fuse
381 * state after the enabling. For all other power wells with
382 * fuses we only have to wait for that PW/PG's fuse state
383 * after the enabling.
385 if (pg == SKL_PG1)
386 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
389 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
390 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
391 hsw_wait_for_power_well_enable(dev_priv, power_well);
393 if (wait_fuses)
394 gen9_wait_for_power_well_fuses(dev_priv, pg);
396 hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
397 power_well->hsw.has_vga);
400 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
401 struct i915_power_well *power_well)
403 enum i915_power_well_id id = power_well->id;
404 u32 val;
406 hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
408 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
409 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),
410 val & ~HSW_PWR_WELL_CTL_REQ(id));
411 hsw_wait_for_power_well_disable(dev_priv, power_well);
415 * We should only use the power well if we explicitly asked the hardware to
416 * enable it, so check if it's enabled and also check if we've requested it to
417 * be enabled.
419 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
420 struct i915_power_well *power_well)
422 enum i915_power_well_id id = power_well->id;
423 u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id);
425 return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask;
428 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
430 enum i915_power_well_id id = SKL_DISP_PW_2;
432 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
433 "DC9 already programmed to be enabled.\n");
434 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
435 "DC5 still not disabled to enable DC9.\n");
436 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &
437 HSW_PWR_WELL_CTL_REQ(id),
438 "Power well 2 on.\n");
439 WARN_ONCE(intel_irqs_enabled(dev_priv),
440 "Interrupts not disabled yet.\n");
443 * TODO: check for the following to verify the conditions to enter DC9
444 * state are satisfied:
445 * 1] Check relevant display engine registers to verify if mode set
446 * disable sequence was followed.
447 * 2] Check if display uninitialize sequence is initialized.
451 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
453 WARN_ONCE(intel_irqs_enabled(dev_priv),
454 "Interrupts not disabled yet.\n");
455 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
456 "DC5 still not disabled.\n");
459 * TODO: check for the following to verify DC9 state was indeed
460 * entered before programming to disable it:
461 * 1] Check relevant display engine registers to verify if mode
462 * set disable sequence was followed.
463 * 2] Check if display uninitialize sequence is initialized.
467 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
468 u32 state)
470 int rewrites = 0;
471 int rereads = 0;
472 u32 v;
474 I915_WRITE(DC_STATE_EN, state);
476 /* It has been observed that disabling the dc6 state sometimes
477 * doesn't stick and dmc keeps returning old value. Make sure
478 * the write really sticks enough times and also force rewrite until
479 * we are confident that state is exactly what we want.
481 do {
482 v = I915_READ(DC_STATE_EN);
484 if (v != state) {
485 I915_WRITE(DC_STATE_EN, state);
486 rewrites++;
487 rereads = 0;
488 } else if (rereads++ > 5) {
489 break;
492 } while (rewrites < 100);
494 if (v != state)
495 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
496 state, v);
498 /* Most of the times we need one retry, avoid spam */
499 if (rewrites > 1)
500 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
501 state, rewrites);
504 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
506 u32 mask;
508 mask = DC_STATE_EN_UPTO_DC5;
509 if (IS_GEN9_LP(dev_priv))
510 mask |= DC_STATE_EN_DC9;
511 else
512 mask |= DC_STATE_EN_UPTO_DC6;
514 return mask;
517 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
519 u32 val;
521 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
523 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
524 dev_priv->csr.dc_state, val);
525 dev_priv->csr.dc_state = val;
528 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
530 uint32_t val;
531 uint32_t mask;
533 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
534 state &= dev_priv->csr.allowed_dc_mask;
536 val = I915_READ(DC_STATE_EN);
537 mask = gen9_dc_mask(dev_priv);
538 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
539 val & mask, state);
541 /* Check if DMC is ignoring our DC state requests */
542 if ((val & mask) != dev_priv->csr.dc_state)
543 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
544 dev_priv->csr.dc_state, val & mask);
546 val &= ~mask;
547 val |= state;
549 gen9_write_dc_state(dev_priv, val);
551 dev_priv->csr.dc_state = val & mask;
554 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
556 assert_can_enable_dc9(dev_priv);
558 DRM_DEBUG_KMS("Enabling DC9\n");
560 intel_power_sequencer_reset(dev_priv);
561 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
564 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
566 assert_can_disable_dc9(dev_priv);
568 DRM_DEBUG_KMS("Disabling DC9\n");
570 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
572 intel_pps_unlock_regs_wa(dev_priv);
575 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
577 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
578 "CSR program storage start is NULL\n");
579 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
580 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
583 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
585 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
586 SKL_DISP_PW_2);
588 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
590 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
591 "DC5 already programmed to be enabled.\n");
592 assert_rpm_wakelock_held(dev_priv);
594 assert_csr_loaded(dev_priv);
597 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
599 assert_can_enable_dc5(dev_priv);
601 DRM_DEBUG_KMS("Enabling DC5\n");
603 /* Wa Display #1183: skl,kbl,cfl */
604 if (IS_GEN9_BC(dev_priv))
605 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
606 SKL_SELECT_ALTERNATE_DC_EXIT);
608 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
611 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
613 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
614 "Backlight is not disabled.\n");
615 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
616 "DC6 already programmed to be enabled.\n");
618 assert_csr_loaded(dev_priv);
621 void skl_enable_dc6(struct drm_i915_private *dev_priv)
623 assert_can_enable_dc6(dev_priv);
625 DRM_DEBUG_KMS("Enabling DC6\n");
627 /* Wa Display #1183: skl,kbl,cfl */
628 if (IS_GEN9_BC(dev_priv))
629 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
630 SKL_SELECT_ALTERNATE_DC_EXIT);
632 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
635 void skl_disable_dc6(struct drm_i915_private *dev_priv)
637 DRM_DEBUG_KMS("Disabling DC6\n");
639 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
642 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
643 struct i915_power_well *power_well)
645 enum i915_power_well_id id = power_well->id;
646 u32 mask = HSW_PWR_WELL_CTL_REQ(id);
647 u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id));
649 /* Take over the request bit if set by BIOS. */
650 if (bios_req & mask) {
651 u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
653 if (!(drv_req & mask))
654 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask);
655 I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask);
659 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
660 struct i915_power_well *power_well)
662 bxt_ddi_phy_init(dev_priv, power_well->bxt.phy);
665 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
666 struct i915_power_well *power_well)
668 bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy);
671 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
672 struct i915_power_well *power_well)
674 return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy);
677 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
679 struct i915_power_well *power_well;
681 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
682 if (power_well->count > 0)
683 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
685 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
686 if (power_well->count > 0)
687 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
689 if (IS_GEMINILAKE(dev_priv)) {
690 power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
691 if (power_well->count > 0)
692 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
696 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
697 struct i915_power_well *power_well)
699 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
702 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
704 u32 tmp = I915_READ(DBUF_CTL);
706 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
707 (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
708 "Unexpected DBuf power power state (0x%08x)\n", tmp);
711 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
712 struct i915_power_well *power_well)
714 struct intel_cdclk_state cdclk_state = {};
716 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
718 dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
719 /* Can't read out voltage_level so can't use intel_cdclk_changed() */
720 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
722 gen9_assert_dbuf_enabled(dev_priv);
724 if (IS_GEN9_LP(dev_priv))
725 bxt_verify_ddi_phy_power_wells(dev_priv);
728 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
729 struct i915_power_well *power_well)
731 if (!dev_priv->csr.dmc_payload)
732 return;
734 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
735 skl_enable_dc6(dev_priv);
736 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
737 gen9_enable_dc5(dev_priv);
740 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
741 struct i915_power_well *power_well)
745 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
746 struct i915_power_well *power_well)
750 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
751 struct i915_power_well *power_well)
753 return true;
756 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
757 struct i915_power_well *power_well)
759 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
760 i830_enable_pipe(dev_priv, PIPE_A);
761 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
762 i830_enable_pipe(dev_priv, PIPE_B);
765 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
766 struct i915_power_well *power_well)
768 i830_disable_pipe(dev_priv, PIPE_B);
769 i830_disable_pipe(dev_priv, PIPE_A);
772 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
773 struct i915_power_well *power_well)
775 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
776 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
779 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
780 struct i915_power_well *power_well)
782 if (power_well->count > 0)
783 i830_pipes_power_well_enable(dev_priv, power_well);
784 else
785 i830_pipes_power_well_disable(dev_priv, power_well);
788 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
789 struct i915_power_well *power_well, bool enable)
791 enum i915_power_well_id power_well_id = power_well->id;
792 u32 mask;
793 u32 state;
794 u32 ctrl;
796 mask = PUNIT_PWRGT_MASK(power_well_id);
797 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
798 PUNIT_PWRGT_PWR_GATE(power_well_id);
800 mutex_lock(&dev_priv->pcu_lock);
802 #define COND \
803 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
805 if (COND)
806 goto out;
808 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
809 ctrl &= ~mask;
810 ctrl |= state;
811 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
813 if (wait_for(COND, 100))
814 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
815 state,
816 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
818 #undef COND
820 out:
821 mutex_unlock(&dev_priv->pcu_lock);
824 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
825 struct i915_power_well *power_well)
827 vlv_set_power_well(dev_priv, power_well, true);
830 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
831 struct i915_power_well *power_well)
833 vlv_set_power_well(dev_priv, power_well, false);
836 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
837 struct i915_power_well *power_well)
839 enum i915_power_well_id power_well_id = power_well->id;
840 bool enabled = false;
841 u32 mask;
842 u32 state;
843 u32 ctrl;
845 mask = PUNIT_PWRGT_MASK(power_well_id);
846 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
848 mutex_lock(&dev_priv->pcu_lock);
850 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
852 * We only ever set the power-on and power-gate states, anything
853 * else is unexpected.
855 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
856 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
857 if (state == ctrl)
858 enabled = true;
861 * A transient state at this point would mean some unexpected party
862 * is poking at the power controls too.
864 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
865 WARN_ON(ctrl != state);
867 mutex_unlock(&dev_priv->pcu_lock);
869 return enabled;
872 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
874 u32 val;
877 * On driver load, a pipe may be active and driving a DSI display.
878 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
879 * (and never recovering) in this case. intel_dsi_post_disable() will
880 * clear it when we turn off the display.
882 val = I915_READ(DSPCLK_GATE_D);
883 val &= DPOUNIT_CLOCK_GATE_DISABLE;
884 val |= VRHUNIT_CLOCK_GATE_DISABLE;
885 I915_WRITE(DSPCLK_GATE_D, val);
888 * Disable trickle feed and enable pnd deadline calculation
890 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
891 I915_WRITE(CBR1_VLV, 0);
893 WARN_ON(dev_priv->rawclk_freq == 0);
895 I915_WRITE(RAWCLK_FREQ_VLV,
896 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
899 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
901 struct intel_encoder *encoder;
902 enum pipe pipe;
905 * Enable the CRI clock source so we can get at the
906 * display and the reference clock for VGA
907 * hotplug / manual detection. Supposedly DSI also
908 * needs the ref clock up and running.
910 * CHV DPLL B/C have some issues if VGA mode is enabled.
912 for_each_pipe(dev_priv, pipe) {
913 u32 val = I915_READ(DPLL(pipe));
915 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
916 if (pipe != PIPE_A)
917 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
919 I915_WRITE(DPLL(pipe), val);
922 vlv_init_display_clock_gating(dev_priv);
924 spin_lock_irq(&dev_priv->irq_lock);
925 valleyview_enable_display_irqs(dev_priv);
926 spin_unlock_irq(&dev_priv->irq_lock);
929 * During driver initialization/resume we can avoid restoring the
930 * part of the HW/SW state that will be inited anyway explicitly.
932 if (dev_priv->power_domains.initializing)
933 return;
935 intel_hpd_init(dev_priv);
937 /* Re-enable the ADPA, if we have one */
938 for_each_intel_encoder(&dev_priv->drm, encoder) {
939 if (encoder->type == INTEL_OUTPUT_ANALOG)
940 intel_crt_reset(&encoder->base);
943 i915_redisable_vga_power_on(dev_priv);
945 intel_pps_unlock_regs_wa(dev_priv);
948 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
950 spin_lock_irq(&dev_priv->irq_lock);
951 valleyview_disable_display_irqs(dev_priv);
952 spin_unlock_irq(&dev_priv->irq_lock);
954 /* make sure we're done processing display irqs */
955 synchronize_irq(dev_priv->drm.irq);
957 intel_power_sequencer_reset(dev_priv);
959 /* Prevent us from re-enabling polling on accident in late suspend */
960 if (!dev_priv->drm.dev->power.is_suspended)
961 intel_hpd_poll_init(dev_priv);
964 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
965 struct i915_power_well *power_well)
967 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
969 vlv_set_power_well(dev_priv, power_well, true);
971 vlv_display_power_well_init(dev_priv);
974 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
975 struct i915_power_well *power_well)
977 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
979 vlv_display_power_well_deinit(dev_priv);
981 vlv_set_power_well(dev_priv, power_well, false);
984 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
985 struct i915_power_well *power_well)
987 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
989 /* since ref/cri clock was enabled */
990 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
992 vlv_set_power_well(dev_priv, power_well, true);
995 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
996 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
997 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
998 * b. The other bits such as sfr settings / modesel may all
999 * be set to 0.
1001 * This should only be done on init and resume from S3 with
1002 * both PLLs disabled, or we risk losing DPIO and PLL
1003 * synchronization.
1005 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1008 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1009 struct i915_power_well *power_well)
1011 enum pipe pipe;
1013 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
1015 for_each_pipe(dev_priv, pipe)
1016 assert_pll_disabled(dev_priv, pipe);
1018 /* Assert common reset */
1019 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1021 vlv_set_power_well(dev_priv, power_well, false);
1024 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
1026 static struct i915_power_well *
1027 lookup_power_well(struct drm_i915_private *dev_priv,
1028 enum i915_power_well_id power_well_id)
1030 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1031 int i;
1033 for (i = 0; i < power_domains->power_well_count; i++) {
1034 struct i915_power_well *power_well;
1036 power_well = &power_domains->power_wells[i];
1037 if (power_well->id == power_well_id)
1038 return power_well;
1041 return NULL;
1044 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1046 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1048 struct i915_power_well *cmn_bc =
1049 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1050 struct i915_power_well *cmn_d =
1051 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1052 u32 phy_control = dev_priv->chv_phy_control;
1053 u32 phy_status = 0;
1054 u32 phy_status_mask = 0xffffffff;
1057 * The BIOS can leave the PHY is some weird state
1058 * where it doesn't fully power down some parts.
1059 * Disable the asserts until the PHY has been fully
1060 * reset (ie. the power well has been disabled at
1061 * least once).
1063 if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1064 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1065 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1066 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1067 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1068 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1069 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1071 if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1072 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1073 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1074 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1076 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1077 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1079 /* this assumes override is only used to enable lanes */
1080 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1081 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1083 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1084 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1086 /* CL1 is on whenever anything is on in either channel */
1087 if (BITS_SET(phy_control,
1088 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1089 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1090 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1093 * The DPLLB check accounts for the pipe B + port A usage
1094 * with CL2 powered up but all the lanes in the second channel
1095 * powered down.
1097 if (BITS_SET(phy_control,
1098 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1099 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1100 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1102 if (BITS_SET(phy_control,
1103 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1104 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1105 if (BITS_SET(phy_control,
1106 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1107 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1109 if (BITS_SET(phy_control,
1110 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1111 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1112 if (BITS_SET(phy_control,
1113 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1114 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1117 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1118 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1120 /* this assumes override is only used to enable lanes */
1121 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1122 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1124 if (BITS_SET(phy_control,
1125 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1126 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1128 if (BITS_SET(phy_control,
1129 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1130 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1131 if (BITS_SET(phy_control,
1132 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1133 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1136 phy_status &= phy_status_mask;
1139 * The PHY may be busy with some initial calibration and whatnot,
1140 * so the power state can take a while to actually change.
1142 if (intel_wait_for_register(dev_priv,
1143 DISPLAY_PHY_STATUS,
1144 phy_status_mask,
1145 phy_status,
1146 10))
1147 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1148 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
1149 phy_status, dev_priv->chv_phy_control);
1152 #undef BITS_SET
1154 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1155 struct i915_power_well *power_well)
1157 enum dpio_phy phy;
1158 enum pipe pipe;
1159 uint32_t tmp;
1161 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1162 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
1164 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1165 pipe = PIPE_A;
1166 phy = DPIO_PHY0;
1167 } else {
1168 pipe = PIPE_C;
1169 phy = DPIO_PHY1;
1172 /* since ref/cri clock was enabled */
1173 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1174 vlv_set_power_well(dev_priv, power_well, true);
1176 /* Poll for phypwrgood signal */
1177 if (intel_wait_for_register(dev_priv,
1178 DISPLAY_PHY_STATUS,
1179 PHY_POWERGOOD(phy),
1180 PHY_POWERGOOD(phy),
1182 DRM_ERROR("Display PHY %d is not power up\n", phy);
1184 mutex_lock(&dev_priv->sb_lock);
1186 /* Enable dynamic power down */
1187 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1188 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1189 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1190 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1192 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1193 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1194 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1195 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1196 } else {
1198 * Force the non-existing CL2 off. BXT does this
1199 * too, so maybe it saves some power even though
1200 * CL2 doesn't exist?
1202 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1203 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1204 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1207 mutex_unlock(&dev_priv->sb_lock);
1209 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1210 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1212 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1213 phy, dev_priv->chv_phy_control);
1215 assert_chv_phy_status(dev_priv);
1218 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1219 struct i915_power_well *power_well)
1221 enum dpio_phy phy;
1223 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1224 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
1226 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1227 phy = DPIO_PHY0;
1228 assert_pll_disabled(dev_priv, PIPE_A);
1229 assert_pll_disabled(dev_priv, PIPE_B);
1230 } else {
1231 phy = DPIO_PHY1;
1232 assert_pll_disabled(dev_priv, PIPE_C);
1235 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1236 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1238 vlv_set_power_well(dev_priv, power_well, false);
1240 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1241 phy, dev_priv->chv_phy_control);
1243 /* PHY is fully reset now, so we can enable the PHY state asserts */
1244 dev_priv->chv_phy_assert[phy] = true;
1246 assert_chv_phy_status(dev_priv);
1249 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1250 enum dpio_channel ch, bool override, unsigned int mask)
1252 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1253 u32 reg, val, expected, actual;
1256 * The BIOS can leave the PHY is some weird state
1257 * where it doesn't fully power down some parts.
1258 * Disable the asserts until the PHY has been fully
1259 * reset (ie. the power well has been disabled at
1260 * least once).
1262 if (!dev_priv->chv_phy_assert[phy])
1263 return;
1265 if (ch == DPIO_CH0)
1266 reg = _CHV_CMN_DW0_CH0;
1267 else
1268 reg = _CHV_CMN_DW6_CH1;
1270 mutex_lock(&dev_priv->sb_lock);
1271 val = vlv_dpio_read(dev_priv, pipe, reg);
1272 mutex_unlock(&dev_priv->sb_lock);
1275 * This assumes !override is only used when the port is disabled.
1276 * All lanes should power down even without the override when
1277 * the port is disabled.
1279 if (!override || mask == 0xf) {
1280 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1282 * If CH1 common lane is not active anymore
1283 * (eg. for pipe B DPLL) the entire channel will
1284 * shut down, which causes the common lane registers
1285 * to read as 0. That means we can't actually check
1286 * the lane power down status bits, but as the entire
1287 * register reads as 0 it's a good indication that the
1288 * channel is indeed entirely powered down.
1290 if (ch == DPIO_CH1 && val == 0)
1291 expected = 0;
1292 } else if (mask != 0x0) {
1293 expected = DPIO_ANYDL_POWERDOWN;
1294 } else {
1295 expected = 0;
1298 if (ch == DPIO_CH0)
1299 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1300 else
1301 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1302 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1304 WARN(actual != expected,
1305 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1306 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1307 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1308 reg, val);
1311 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1312 enum dpio_channel ch, bool override)
1314 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1315 bool was_override;
1317 mutex_lock(&power_domains->lock);
1319 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1321 if (override == was_override)
1322 goto out;
1324 if (override)
1325 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1326 else
1327 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1329 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1331 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1332 phy, ch, dev_priv->chv_phy_control);
1334 assert_chv_phy_status(dev_priv);
1336 out:
1337 mutex_unlock(&power_domains->lock);
1339 return was_override;
1342 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1343 bool override, unsigned int mask)
1345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1346 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1347 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1348 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1350 mutex_lock(&power_domains->lock);
1352 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1353 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1355 if (override)
1356 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1357 else
1358 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1360 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1362 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1363 phy, ch, mask, dev_priv->chv_phy_control);
1365 assert_chv_phy_status(dev_priv);
1367 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1369 mutex_unlock(&power_domains->lock);
1372 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1373 struct i915_power_well *power_well)
1375 enum pipe pipe = PIPE_A;
1376 bool enabled;
1377 u32 state, ctrl;
1379 mutex_lock(&dev_priv->pcu_lock);
1381 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1383 * We only ever set the power-on and power-gate states, anything
1384 * else is unexpected.
1386 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1387 enabled = state == DP_SSS_PWR_ON(pipe);
1390 * A transient state at this point would mean some unexpected party
1391 * is poking at the power controls too.
1393 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1394 WARN_ON(ctrl << 16 != state);
1396 mutex_unlock(&dev_priv->pcu_lock);
1398 return enabled;
1401 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1402 struct i915_power_well *power_well,
1403 bool enable)
1405 enum pipe pipe = PIPE_A;
1406 u32 state;
1407 u32 ctrl;
1409 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1411 mutex_lock(&dev_priv->pcu_lock);
1413 #define COND \
1414 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1416 if (COND)
1417 goto out;
1419 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1420 ctrl &= ~DP_SSC_MASK(pipe);
1421 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1422 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1424 if (wait_for(COND, 100))
1425 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1426 state,
1427 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1429 #undef COND
1431 out:
1432 mutex_unlock(&dev_priv->pcu_lock);
1435 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1436 struct i915_power_well *power_well)
1438 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
1440 chv_set_pipe_power_well(dev_priv, power_well, true);
1442 vlv_display_power_well_init(dev_priv);
1445 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1446 struct i915_power_well *power_well)
1448 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
1450 vlv_display_power_well_deinit(dev_priv);
1452 chv_set_pipe_power_well(dev_priv, power_well, false);
1455 static void
1456 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1457 enum intel_display_power_domain domain)
1459 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1460 struct i915_power_well *power_well;
1462 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
1463 intel_power_well_get(dev_priv, power_well);
1465 power_domains->domain_use_count[domain]++;
1469 * intel_display_power_get - grab a power domain reference
1470 * @dev_priv: i915 device instance
1471 * @domain: power domain to reference
1473 * This function grabs a power domain reference for @domain and ensures that the
1474 * power domain and all its parents are powered up. Therefore users should only
1475 * grab a reference to the innermost power domain they need.
1477 * Any power domain reference obtained by this function must have a symmetric
1478 * call to intel_display_power_put() to release the reference again.
1480 void intel_display_power_get(struct drm_i915_private *dev_priv,
1481 enum intel_display_power_domain domain)
1483 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1485 intel_runtime_pm_get(dev_priv);
1487 mutex_lock(&power_domains->lock);
1489 __intel_display_power_get_domain(dev_priv, domain);
1491 mutex_unlock(&power_domains->lock);
1495 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1496 * @dev_priv: i915 device instance
1497 * @domain: power domain to reference
1499 * This function grabs a power domain reference for @domain and ensures that the
1500 * power domain and all its parents are powered up. Therefore users should only
1501 * grab a reference to the innermost power domain they need.
1503 * Any power domain reference obtained by this function must have a symmetric
1504 * call to intel_display_power_put() to release the reference again.
1506 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1507 enum intel_display_power_domain domain)
1509 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1510 bool is_enabled;
1512 if (!intel_runtime_pm_get_if_in_use(dev_priv))
1513 return false;
1515 mutex_lock(&power_domains->lock);
1517 if (__intel_display_power_is_enabled(dev_priv, domain)) {
1518 __intel_display_power_get_domain(dev_priv, domain);
1519 is_enabled = true;
1520 } else {
1521 is_enabled = false;
1524 mutex_unlock(&power_domains->lock);
1526 if (!is_enabled)
1527 intel_runtime_pm_put(dev_priv);
1529 return is_enabled;
1533 * intel_display_power_put - release a power domain reference
1534 * @dev_priv: i915 device instance
1535 * @domain: power domain to reference
1537 * This function drops the power domain reference obtained by
1538 * intel_display_power_get() and might power down the corresponding hardware
1539 * block right away if this is the last reference.
1541 void intel_display_power_put(struct drm_i915_private *dev_priv,
1542 enum intel_display_power_domain domain)
1544 struct i915_power_domains *power_domains;
1545 struct i915_power_well *power_well;
1547 power_domains = &dev_priv->power_domains;
1549 mutex_lock(&power_domains->lock);
1551 WARN(!power_domains->domain_use_count[domain],
1552 "Use count on domain %s is already zero\n",
1553 intel_display_power_domain_str(domain));
1554 power_domains->domain_use_count[domain]--;
1556 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
1557 intel_power_well_put(dev_priv, power_well);
1559 mutex_unlock(&power_domains->lock);
1561 intel_runtime_pm_put(dev_priv);
1564 #define I830_PIPES_POWER_DOMAINS ( \
1565 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
1566 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1567 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1568 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1569 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1570 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1571 BIT_ULL(POWER_DOMAIN_INIT))
1573 #define VLV_DISPLAY_POWER_DOMAINS ( \
1574 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
1575 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1576 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1577 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1578 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1579 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1580 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1581 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1582 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
1583 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
1584 BIT_ULL(POWER_DOMAIN_VGA) | \
1585 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1586 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1587 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1588 BIT_ULL(POWER_DOMAIN_GMBUS) | \
1589 BIT_ULL(POWER_DOMAIN_INIT))
1591 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1592 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1593 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1594 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
1595 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1596 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1597 BIT_ULL(POWER_DOMAIN_INIT))
1599 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1600 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1601 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1602 BIT_ULL(POWER_DOMAIN_INIT))
1604 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1605 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1606 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1607 BIT_ULL(POWER_DOMAIN_INIT))
1609 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1610 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1611 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1612 BIT_ULL(POWER_DOMAIN_INIT))
1614 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1615 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1616 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1617 BIT_ULL(POWER_DOMAIN_INIT))
1619 #define CHV_DISPLAY_POWER_DOMAINS ( \
1620 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
1621 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1622 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1623 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1624 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1625 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1626 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1627 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1628 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1629 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1630 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1631 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1632 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
1633 BIT_ULL(POWER_DOMAIN_VGA) | \
1634 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1635 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1636 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1637 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1638 BIT_ULL(POWER_DOMAIN_GMBUS) | \
1639 BIT_ULL(POWER_DOMAIN_INIT))
1641 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1642 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1643 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1644 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1645 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1646 BIT_ULL(POWER_DOMAIN_INIT))
1648 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1649 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1650 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1651 BIT_ULL(POWER_DOMAIN_INIT))
1653 #define HSW_DISPLAY_POWER_DOMAINS ( \
1654 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1655 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1656 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1657 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1658 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1659 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1660 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1661 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1662 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1663 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1664 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1665 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
1666 BIT_ULL(POWER_DOMAIN_VGA) | \
1667 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1668 BIT_ULL(POWER_DOMAIN_INIT))
1670 #define BDW_DISPLAY_POWER_DOMAINS ( \
1671 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1672 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1673 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1674 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1675 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1676 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1677 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1678 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1679 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1680 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1681 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
1682 BIT_ULL(POWER_DOMAIN_VGA) | \
1683 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1684 BIT_ULL(POWER_DOMAIN_INIT))
1686 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
1687 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1688 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1689 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1690 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1691 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1692 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1693 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1694 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1695 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1696 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1697 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
1698 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1699 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1700 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1701 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1702 BIT_ULL(POWER_DOMAIN_VGA) | \
1703 BIT_ULL(POWER_DOMAIN_INIT))
1704 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
1705 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
1706 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
1707 BIT_ULL(POWER_DOMAIN_INIT))
1708 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
1709 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
1710 BIT_ULL(POWER_DOMAIN_INIT))
1711 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
1712 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
1713 BIT_ULL(POWER_DOMAIN_INIT))
1714 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
1715 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
1716 BIT_ULL(POWER_DOMAIN_INIT))
1717 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1718 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
1719 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
1720 BIT_ULL(POWER_DOMAIN_MODESET) | \
1721 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1722 BIT_ULL(POWER_DOMAIN_INIT))
1724 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
1725 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1726 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1727 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1728 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1729 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1730 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1731 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1732 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1733 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1734 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1735 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1736 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1737 BIT_ULL(POWER_DOMAIN_VGA) | \
1738 BIT_ULL(POWER_DOMAIN_INIT))
1739 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1740 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
1741 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
1742 BIT_ULL(POWER_DOMAIN_MODESET) | \
1743 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1744 BIT_ULL(POWER_DOMAIN_GMBUS) | \
1745 BIT_ULL(POWER_DOMAIN_INIT))
1746 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
1747 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1748 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1749 BIT_ULL(POWER_DOMAIN_INIT))
1750 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
1751 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1752 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1753 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1754 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1755 BIT_ULL(POWER_DOMAIN_INIT))
1757 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
1758 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1759 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1760 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1761 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1762 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1763 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1764 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1765 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1766 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1767 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1768 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1769 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1770 BIT_ULL(POWER_DOMAIN_VGA) | \
1771 BIT_ULL(POWER_DOMAIN_INIT))
1772 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
1773 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
1774 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
1775 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
1776 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
1777 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
1778 #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
1779 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1780 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1781 BIT_ULL(POWER_DOMAIN_INIT))
1782 #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
1783 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1784 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1785 BIT_ULL(POWER_DOMAIN_INIT))
1786 #define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
1787 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1788 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1789 BIT_ULL(POWER_DOMAIN_INIT))
1790 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
1791 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1792 BIT_ULL(POWER_DOMAIN_INIT))
1793 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
1794 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1795 BIT_ULL(POWER_DOMAIN_INIT))
1796 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
1797 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1798 BIT_ULL(POWER_DOMAIN_INIT))
1799 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1800 GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
1801 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
1802 BIT_ULL(POWER_DOMAIN_MODESET) | \
1803 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1804 BIT_ULL(POWER_DOMAIN_GMBUS) | \
1805 BIT_ULL(POWER_DOMAIN_INIT))
1807 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
1808 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
1809 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
1810 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
1811 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
1812 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
1813 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1814 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1815 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1816 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1817 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1818 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1819 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1820 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1821 BIT_ULL(POWER_DOMAIN_AUDIO) | \
1822 BIT_ULL(POWER_DOMAIN_VGA) | \
1823 BIT_ULL(POWER_DOMAIN_INIT))
1824 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
1825 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
1826 BIT_ULL(POWER_DOMAIN_INIT))
1827 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
1828 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
1829 BIT_ULL(POWER_DOMAIN_INIT))
1830 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
1831 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
1832 BIT_ULL(POWER_DOMAIN_INIT))
1833 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
1834 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
1835 BIT_ULL(POWER_DOMAIN_INIT))
1836 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
1837 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1838 BIT_ULL(POWER_DOMAIN_INIT))
1839 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
1840 BIT_ULL(POWER_DOMAIN_AUX_B) | \
1841 BIT_ULL(POWER_DOMAIN_INIT))
1842 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \
1843 BIT_ULL(POWER_DOMAIN_AUX_C) | \
1844 BIT_ULL(POWER_DOMAIN_INIT))
1845 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
1846 BIT_ULL(POWER_DOMAIN_AUX_D) | \
1847 BIT_ULL(POWER_DOMAIN_INIT))
1848 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
1849 CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
1850 BIT_ULL(POWER_DOMAIN_MODESET) | \
1851 BIT_ULL(POWER_DOMAIN_AUX_A) | \
1852 BIT_ULL(POWER_DOMAIN_INIT))
1854 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1855 .sync_hw = i9xx_power_well_sync_hw_noop,
1856 .enable = i9xx_always_on_power_well_noop,
1857 .disable = i9xx_always_on_power_well_noop,
1858 .is_enabled = i9xx_always_on_power_well_enabled,
1861 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1862 .sync_hw = i9xx_power_well_sync_hw_noop,
1863 .enable = chv_pipe_power_well_enable,
1864 .disable = chv_pipe_power_well_disable,
1865 .is_enabled = chv_pipe_power_well_enabled,
1868 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1869 .sync_hw = i9xx_power_well_sync_hw_noop,
1870 .enable = chv_dpio_cmn_power_well_enable,
1871 .disable = chv_dpio_cmn_power_well_disable,
1872 .is_enabled = vlv_power_well_enabled,
1875 static struct i915_power_well i9xx_always_on_power_well[] = {
1877 .name = "always-on",
1878 .always_on = 1,
1879 .domains = POWER_DOMAIN_MASK,
1880 .ops = &i9xx_always_on_power_well_ops,
1881 .id = I915_DISP_PW_ALWAYS_ON,
1885 static const struct i915_power_well_ops i830_pipes_power_well_ops = {
1886 .sync_hw = i830_pipes_power_well_sync_hw,
1887 .enable = i830_pipes_power_well_enable,
1888 .disable = i830_pipes_power_well_disable,
1889 .is_enabled = i830_pipes_power_well_enabled,
1892 static struct i915_power_well i830_power_wells[] = {
1894 .name = "always-on",
1895 .always_on = 1,
1896 .domains = POWER_DOMAIN_MASK,
1897 .ops = &i9xx_always_on_power_well_ops,
1898 .id = I915_DISP_PW_ALWAYS_ON,
1901 .name = "pipes",
1902 .domains = I830_PIPES_POWER_DOMAINS,
1903 .ops = &i830_pipes_power_well_ops,
1904 .id = I830_DISP_PW_PIPES,
1908 static const struct i915_power_well_ops hsw_power_well_ops = {
1909 .sync_hw = hsw_power_well_sync_hw,
1910 .enable = hsw_power_well_enable,
1911 .disable = hsw_power_well_disable,
1912 .is_enabled = hsw_power_well_enabled,
1915 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1916 .sync_hw = i9xx_power_well_sync_hw_noop,
1917 .enable = gen9_dc_off_power_well_enable,
1918 .disable = gen9_dc_off_power_well_disable,
1919 .is_enabled = gen9_dc_off_power_well_enabled,
1922 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1923 .sync_hw = i9xx_power_well_sync_hw_noop,
1924 .enable = bxt_dpio_cmn_power_well_enable,
1925 .disable = bxt_dpio_cmn_power_well_disable,
1926 .is_enabled = bxt_dpio_cmn_power_well_enabled,
1929 static struct i915_power_well hsw_power_wells[] = {
1931 .name = "always-on",
1932 .always_on = 1,
1933 .domains = POWER_DOMAIN_MASK,
1934 .ops = &i9xx_always_on_power_well_ops,
1935 .id = I915_DISP_PW_ALWAYS_ON,
1938 .name = "display",
1939 .domains = HSW_DISPLAY_POWER_DOMAINS,
1940 .ops = &hsw_power_well_ops,
1941 .id = HSW_DISP_PW_GLOBAL,
1943 .hsw.has_vga = true,
1948 static struct i915_power_well bdw_power_wells[] = {
1950 .name = "always-on",
1951 .always_on = 1,
1952 .domains = POWER_DOMAIN_MASK,
1953 .ops = &i9xx_always_on_power_well_ops,
1954 .id = I915_DISP_PW_ALWAYS_ON,
1957 .name = "display",
1958 .domains = BDW_DISPLAY_POWER_DOMAINS,
1959 .ops = &hsw_power_well_ops,
1960 .id = HSW_DISP_PW_GLOBAL,
1962 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
1963 .hsw.has_vga = true,
1968 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1969 .sync_hw = i9xx_power_well_sync_hw_noop,
1970 .enable = vlv_display_power_well_enable,
1971 .disable = vlv_display_power_well_disable,
1972 .is_enabled = vlv_power_well_enabled,
1975 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1976 .sync_hw = i9xx_power_well_sync_hw_noop,
1977 .enable = vlv_dpio_cmn_power_well_enable,
1978 .disable = vlv_dpio_cmn_power_well_disable,
1979 .is_enabled = vlv_power_well_enabled,
1982 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1983 .sync_hw = i9xx_power_well_sync_hw_noop,
1984 .enable = vlv_power_well_enable,
1985 .disable = vlv_power_well_disable,
1986 .is_enabled = vlv_power_well_enabled,
1989 static struct i915_power_well vlv_power_wells[] = {
1991 .name = "always-on",
1992 .always_on = 1,
1993 .domains = POWER_DOMAIN_MASK,
1994 .ops = &i9xx_always_on_power_well_ops,
1995 .id = I915_DISP_PW_ALWAYS_ON,
1998 .name = "display",
1999 .domains = VLV_DISPLAY_POWER_DOMAINS,
2000 .id = PUNIT_POWER_WELL_DISP2D,
2001 .ops = &vlv_display_power_well_ops,
2004 .name = "dpio-tx-b-01",
2005 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2006 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2007 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2008 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2009 .ops = &vlv_dpio_power_well_ops,
2010 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
2013 .name = "dpio-tx-b-23",
2014 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2015 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2016 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2017 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2018 .ops = &vlv_dpio_power_well_ops,
2019 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
2022 .name = "dpio-tx-c-01",
2023 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2024 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2025 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2026 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2027 .ops = &vlv_dpio_power_well_ops,
2028 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
2031 .name = "dpio-tx-c-23",
2032 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2033 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2034 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2035 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2036 .ops = &vlv_dpio_power_well_ops,
2037 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
2040 .name = "dpio-common",
2041 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2042 .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
2043 .ops = &vlv_dpio_cmn_power_well_ops,
2047 static struct i915_power_well chv_power_wells[] = {
2049 .name = "always-on",
2050 .always_on = 1,
2051 .domains = POWER_DOMAIN_MASK,
2052 .ops = &i9xx_always_on_power_well_ops,
2053 .id = I915_DISP_PW_ALWAYS_ON,
2056 .name = "display",
2058 * Pipe A power well is the new disp2d well. Pipe B and C
2059 * power wells don't actually exist. Pipe A power well is
2060 * required for any pipe to work.
2062 .domains = CHV_DISPLAY_POWER_DOMAINS,
2063 .id = CHV_DISP_PW_PIPE_A,
2064 .ops = &chv_pipe_power_well_ops,
2067 .name = "dpio-common-bc",
2068 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2069 .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
2070 .ops = &chv_dpio_cmn_power_well_ops,
2073 .name = "dpio-common-d",
2074 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2075 .id = PUNIT_POWER_WELL_DPIO_CMN_D,
2076 .ops = &chv_dpio_cmn_power_well_ops,
2080 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2081 enum i915_power_well_id power_well_id)
2083 struct i915_power_well *power_well;
2084 bool ret;
2086 power_well = lookup_power_well(dev_priv, power_well_id);
2087 ret = power_well->ops->is_enabled(dev_priv, power_well);
2089 return ret;
2092 static struct i915_power_well skl_power_wells[] = {
2094 .name = "always-on",
2095 .always_on = 1,
2096 .domains = POWER_DOMAIN_MASK,
2097 .ops = &i9xx_always_on_power_well_ops,
2098 .id = I915_DISP_PW_ALWAYS_ON,
2101 .name = "power well 1",
2102 /* Handled by the DMC firmware */
2103 .domains = 0,
2104 .ops = &hsw_power_well_ops,
2105 .id = SKL_DISP_PW_1,
2107 .hsw.has_fuses = true,
2111 .name = "MISC IO power well",
2112 /* Handled by the DMC firmware */
2113 .domains = 0,
2114 .ops = &hsw_power_well_ops,
2115 .id = SKL_DISP_PW_MISC_IO,
2118 .name = "DC off",
2119 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2120 .ops = &gen9_dc_off_power_well_ops,
2121 .id = SKL_DISP_PW_DC_OFF,
2124 .name = "power well 2",
2125 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2126 .ops = &hsw_power_well_ops,
2127 .id = SKL_DISP_PW_2,
2129 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2130 .hsw.has_vga = true,
2131 .hsw.has_fuses = true,
2135 .name = "DDI A/E IO power well",
2136 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
2137 .ops = &hsw_power_well_ops,
2138 .id = SKL_DISP_PW_DDI_A_E,
2141 .name = "DDI B IO power well",
2142 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2143 .ops = &hsw_power_well_ops,
2144 .id = SKL_DISP_PW_DDI_B,
2147 .name = "DDI C IO power well",
2148 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2149 .ops = &hsw_power_well_ops,
2150 .id = SKL_DISP_PW_DDI_C,
2153 .name = "DDI D IO power well",
2154 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
2155 .ops = &hsw_power_well_ops,
2156 .id = SKL_DISP_PW_DDI_D,
2160 static struct i915_power_well bxt_power_wells[] = {
2162 .name = "always-on",
2163 .always_on = 1,
2164 .domains = POWER_DOMAIN_MASK,
2165 .ops = &i9xx_always_on_power_well_ops,
2166 .id = I915_DISP_PW_ALWAYS_ON,
2169 .name = "power well 1",
2170 .domains = 0,
2171 .ops = &hsw_power_well_ops,
2172 .id = SKL_DISP_PW_1,
2174 .hsw.has_fuses = true,
2178 .name = "DC off",
2179 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2180 .ops = &gen9_dc_off_power_well_ops,
2181 .id = SKL_DISP_PW_DC_OFF,
2184 .name = "power well 2",
2185 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2186 .ops = &hsw_power_well_ops,
2187 .id = SKL_DISP_PW_2,
2189 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2190 .hsw.has_vga = true,
2191 .hsw.has_fuses = true,
2195 .name = "dpio-common-a",
2196 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2197 .ops = &bxt_dpio_cmn_power_well_ops,
2198 .id = BXT_DPIO_CMN_A,
2200 .bxt.phy = DPIO_PHY1,
2204 .name = "dpio-common-bc",
2205 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2206 .ops = &bxt_dpio_cmn_power_well_ops,
2207 .id = BXT_DPIO_CMN_BC,
2209 .bxt.phy = DPIO_PHY0,
2214 static struct i915_power_well glk_power_wells[] = {
2216 .name = "always-on",
2217 .always_on = 1,
2218 .domains = POWER_DOMAIN_MASK,
2219 .ops = &i9xx_always_on_power_well_ops,
2220 .id = I915_DISP_PW_ALWAYS_ON,
2223 .name = "power well 1",
2224 /* Handled by the DMC firmware */
2225 .domains = 0,
2226 .ops = &hsw_power_well_ops,
2227 .id = SKL_DISP_PW_1,
2229 .hsw.has_fuses = true,
2233 .name = "DC off",
2234 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
2235 .ops = &gen9_dc_off_power_well_ops,
2236 .id = SKL_DISP_PW_DC_OFF,
2239 .name = "power well 2",
2240 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2241 .ops = &hsw_power_well_ops,
2242 .id = SKL_DISP_PW_2,
2244 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2245 .hsw.has_vga = true,
2246 .hsw.has_fuses = true,
2250 .name = "dpio-common-a",
2251 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
2252 .ops = &bxt_dpio_cmn_power_well_ops,
2253 .id = BXT_DPIO_CMN_A,
2255 .bxt.phy = DPIO_PHY1,
2259 .name = "dpio-common-b",
2260 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
2261 .ops = &bxt_dpio_cmn_power_well_ops,
2262 .id = BXT_DPIO_CMN_BC,
2264 .bxt.phy = DPIO_PHY0,
2268 .name = "dpio-common-c",
2269 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
2270 .ops = &bxt_dpio_cmn_power_well_ops,
2271 .id = GLK_DPIO_CMN_C,
2273 .bxt.phy = DPIO_PHY2,
2277 .name = "AUX A",
2278 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
2279 .ops = &hsw_power_well_ops,
2280 .id = GLK_DISP_PW_AUX_A,
2283 .name = "AUX B",
2284 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
2285 .ops = &hsw_power_well_ops,
2286 .id = GLK_DISP_PW_AUX_B,
2289 .name = "AUX C",
2290 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
2291 .ops = &hsw_power_well_ops,
2292 .id = GLK_DISP_PW_AUX_C,
2295 .name = "DDI A IO power well",
2296 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
2297 .ops = &hsw_power_well_ops,
2298 .id = GLK_DISP_PW_DDI_A,
2301 .name = "DDI B IO power well",
2302 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2303 .ops = &hsw_power_well_ops,
2304 .id = SKL_DISP_PW_DDI_B,
2307 .name = "DDI C IO power well",
2308 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2309 .ops = &hsw_power_well_ops,
2310 .id = SKL_DISP_PW_DDI_C,
2314 static struct i915_power_well cnl_power_wells[] = {
2316 .name = "always-on",
2317 .always_on = 1,
2318 .domains = POWER_DOMAIN_MASK,
2319 .ops = &i9xx_always_on_power_well_ops,
2320 .id = I915_DISP_PW_ALWAYS_ON,
2323 .name = "power well 1",
2324 /* Handled by the DMC firmware */
2325 .domains = 0,
2326 .ops = &hsw_power_well_ops,
2327 .id = SKL_DISP_PW_1,
2329 .hsw.has_fuses = true,
2333 .name = "AUX A",
2334 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
2335 .ops = &hsw_power_well_ops,
2336 .id = CNL_DISP_PW_AUX_A,
2339 .name = "AUX B",
2340 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
2341 .ops = &hsw_power_well_ops,
2342 .id = CNL_DISP_PW_AUX_B,
2345 .name = "AUX C",
2346 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
2347 .ops = &hsw_power_well_ops,
2348 .id = CNL_DISP_PW_AUX_C,
2351 .name = "AUX D",
2352 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
2353 .ops = &hsw_power_well_ops,
2354 .id = CNL_DISP_PW_AUX_D,
2357 .name = "DC off",
2358 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
2359 .ops = &gen9_dc_off_power_well_ops,
2360 .id = SKL_DISP_PW_DC_OFF,
2363 .name = "power well 2",
2364 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2365 .ops = &hsw_power_well_ops,
2366 .id = SKL_DISP_PW_2,
2368 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2369 .hsw.has_vga = true,
2370 .hsw.has_fuses = true,
2374 .name = "DDI A IO power well",
2375 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
2376 .ops = &hsw_power_well_ops,
2377 .id = CNL_DISP_PW_DDI_A,
2380 .name = "DDI B IO power well",
2381 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
2382 .ops = &hsw_power_well_ops,
2383 .id = SKL_DISP_PW_DDI_B,
2386 .name = "DDI C IO power well",
2387 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
2388 .ops = &hsw_power_well_ops,
2389 .id = SKL_DISP_PW_DDI_C,
2392 .name = "DDI D IO power well",
2393 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
2394 .ops = &hsw_power_well_ops,
2395 .id = SKL_DISP_PW_DDI_D,
2399 static int
2400 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2401 int disable_power_well)
2403 if (disable_power_well >= 0)
2404 return !!disable_power_well;
2406 return 1;
2409 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2410 int enable_dc)
2412 uint32_t mask;
2413 int requested_dc;
2414 int max_dc;
2416 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
2417 max_dc = 2;
2418 mask = 0;
2419 } else if (IS_GEN9_LP(dev_priv)) {
2420 max_dc = 1;
2422 * DC9 has a separate HW flow from the rest of the DC states,
2423 * not depending on the DMC firmware. It's needed by system
2424 * suspend/resume, so allow it unconditionally.
2426 mask = DC_STATE_EN_DC9;
2427 } else {
2428 max_dc = 0;
2429 mask = 0;
2432 if (!i915_modparams.disable_power_well)
2433 max_dc = 0;
2435 if (enable_dc >= 0 && enable_dc <= max_dc) {
2436 requested_dc = enable_dc;
2437 } else if (enable_dc == -1) {
2438 requested_dc = max_dc;
2439 } else if (enable_dc > max_dc && enable_dc <= 2) {
2440 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2441 enable_dc, max_dc);
2442 requested_dc = max_dc;
2443 } else {
2444 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2445 requested_dc = max_dc;
2448 if (requested_dc > 1)
2449 mask |= DC_STATE_EN_UPTO_DC6;
2450 if (requested_dc > 0)
2451 mask |= DC_STATE_EN_UPTO_DC5;
2453 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2455 return mask;
2458 static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv)
2460 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2461 u64 power_well_ids;
2462 int i;
2464 power_well_ids = 0;
2465 for (i = 0; i < power_domains->power_well_count; i++) {
2466 enum i915_power_well_id id = power_domains->power_wells[i].id;
2468 WARN_ON(id >= sizeof(power_well_ids) * 8);
2469 WARN_ON(power_well_ids & BIT_ULL(id));
2470 power_well_ids |= BIT_ULL(id);
2474 #define set_power_wells(power_domains, __power_wells) ({ \
2475 (power_domains)->power_wells = (__power_wells); \
2476 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
2480 * intel_power_domains_init - initializes the power domain structures
2481 * @dev_priv: i915 device instance
2483 * Initializes the power domain structures for @dev_priv depending upon the
2484 * supported platform.
2486 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2488 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2490 i915_modparams.disable_power_well =
2491 sanitize_disable_power_well_option(dev_priv,
2492 i915_modparams.disable_power_well);
2493 dev_priv->csr.allowed_dc_mask =
2494 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);
2496 BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
2498 mutex_init(&power_domains->lock);
2501 * The enabling order will be from lower to higher indexed wells,
2502 * the disabling order is reversed.
2504 if (IS_HASWELL(dev_priv)) {
2505 set_power_wells(power_domains, hsw_power_wells);
2506 } else if (IS_BROADWELL(dev_priv)) {
2507 set_power_wells(power_domains, bdw_power_wells);
2508 } else if (IS_GEN9_BC(dev_priv)) {
2509 set_power_wells(power_domains, skl_power_wells);
2510 } else if (IS_CANNONLAKE(dev_priv)) {
2511 set_power_wells(power_domains, cnl_power_wells);
2512 } else if (IS_BROXTON(dev_priv)) {
2513 set_power_wells(power_domains, bxt_power_wells);
2514 } else if (IS_GEMINILAKE(dev_priv)) {
2515 set_power_wells(power_domains, glk_power_wells);
2516 } else if (IS_CHERRYVIEW(dev_priv)) {
2517 set_power_wells(power_domains, chv_power_wells);
2518 } else if (IS_VALLEYVIEW(dev_priv)) {
2519 set_power_wells(power_domains, vlv_power_wells);
2520 } else if (IS_I830(dev_priv)) {
2521 set_power_wells(power_domains, i830_power_wells);
2522 } else {
2523 set_power_wells(power_domains, i9xx_always_on_power_well);
2526 assert_power_well_ids_unique(dev_priv);
2528 return 0;
2532 * intel_power_domains_fini - finalizes the power domain structures
2533 * @dev_priv: i915 device instance
2535 * Finalizes the power domain structures for @dev_priv depending upon the
2536 * supported platform. This function also disables runtime pm and ensures that
2537 * the device stays powered up so that the driver can be reloaded.
2539 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2541 struct device *kdev = &dev_priv->drm.pdev->dev;
2544 * The i915.ko module is still not prepared to be loaded when
2545 * the power well is not enabled, so just enable it in case
2546 * we're going to unload/reload.
2547 * The following also reacquires the RPM reference the core passed
2548 * to the driver during loading, which is dropped in
2549 * intel_runtime_pm_enable(). We have to hand back the control of the
2550 * device to the core with this reference held.
2552 intel_display_set_init_power(dev_priv, true);
2554 /* Remove the refcount we took to keep power well support disabled. */
2555 if (!i915_modparams.disable_power_well)
2556 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2559 * Remove the refcount we took in intel_runtime_pm_enable() in case
2560 * the platform doesn't support runtime PM.
2562 if (!HAS_RUNTIME_PM(dev_priv))
2563 pm_runtime_put(kdev);
2566 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2568 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2569 struct i915_power_well *power_well;
2571 mutex_lock(&power_domains->lock);
2572 for_each_power_well(dev_priv, power_well) {
2573 power_well->ops->sync_hw(dev_priv, power_well);
2574 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2575 power_well);
2577 mutex_unlock(&power_domains->lock);
2580 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2582 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2583 POSTING_READ(DBUF_CTL);
2585 udelay(10);
2587 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2588 DRM_ERROR("DBuf power enable timeout\n");
2591 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2593 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2594 POSTING_READ(DBUF_CTL);
2596 udelay(10);
2598 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2599 DRM_ERROR("DBuf power disable timeout!\n");
2602 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2603 bool resume)
2605 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2606 struct i915_power_well *well;
2607 uint32_t val;
2609 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2611 /* enable PCH reset handshake */
2612 val = I915_READ(HSW_NDE_RSTWRN_OPT);
2613 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2615 /* enable PG1 and Misc I/O */
2616 mutex_lock(&power_domains->lock);
2618 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2619 intel_power_well_enable(dev_priv, well);
2621 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2622 intel_power_well_enable(dev_priv, well);
2624 mutex_unlock(&power_domains->lock);
2626 skl_init_cdclk(dev_priv);
2628 gen9_dbuf_enable(dev_priv);
2630 if (resume && dev_priv->csr.dmc_payload)
2631 intel_csr_load_program(dev_priv);
2634 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2636 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2637 struct i915_power_well *well;
2639 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2641 gen9_dbuf_disable(dev_priv);
2643 skl_uninit_cdclk(dev_priv);
2645 /* The spec doesn't call for removing the reset handshake flag */
2646 /* disable PG1 and Misc I/O */
2648 mutex_lock(&power_domains->lock);
2651 * BSpec says to keep the MISC IO power well enabled here, only
2652 * remove our request for power well 1.
2653 * Note that even though the driver's request is removed power well 1
2654 * may stay enabled after this due to DMC's own request on it.
2656 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2657 intel_power_well_disable(dev_priv, well);
2659 mutex_unlock(&power_domains->lock);
2661 usleep_range(10, 30); /* 10 us delay per Bspec */
2664 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2665 bool resume)
2667 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2668 struct i915_power_well *well;
2669 uint32_t val;
2671 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2674 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2675 * or else the reset will hang because there is no PCH to respond.
2676 * Move the handshake programming to initialization sequence.
2677 * Previously was left up to BIOS.
2679 val = I915_READ(HSW_NDE_RSTWRN_OPT);
2680 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2681 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2683 /* Enable PG1 */
2684 mutex_lock(&power_domains->lock);
2686 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2687 intel_power_well_enable(dev_priv, well);
2689 mutex_unlock(&power_domains->lock);
2691 bxt_init_cdclk(dev_priv);
2693 gen9_dbuf_enable(dev_priv);
2695 if (resume && dev_priv->csr.dmc_payload)
2696 intel_csr_load_program(dev_priv);
2699 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2701 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2702 struct i915_power_well *well;
2704 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2706 gen9_dbuf_disable(dev_priv);
2708 bxt_uninit_cdclk(dev_priv);
2710 /* The spec doesn't call for removing the reset handshake flag */
2713 * Disable PW1 (PG1).
2714 * Note that even though the driver's request is removed power well 1
2715 * may stay enabled after this due to DMC's own request on it.
2717 mutex_lock(&power_domains->lock);
2719 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2720 intel_power_well_disable(dev_priv, well);
2722 mutex_unlock(&power_domains->lock);
2724 usleep_range(10, 30); /* 10 us delay per Bspec */
2727 enum {
2728 PROCMON_0_85V_DOT_0,
2729 PROCMON_0_95V_DOT_0,
2730 PROCMON_0_95V_DOT_1,
2731 PROCMON_1_05V_DOT_0,
2732 PROCMON_1_05V_DOT_1,
2735 static const struct cnl_procmon {
2736 u32 dw1, dw9, dw10;
2737 } cnl_procmon_values[] = {
2738 [PROCMON_0_85V_DOT_0] =
2739 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
2740 [PROCMON_0_95V_DOT_0] =
2741 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
2742 [PROCMON_0_95V_DOT_1] =
2743 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
2744 [PROCMON_1_05V_DOT_0] =
2745 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
2746 [PROCMON_1_05V_DOT_1] =
2747 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
2750 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
2752 const struct cnl_procmon *procmon;
2753 u32 val;
2755 val = I915_READ(CNL_PORT_COMP_DW3);
2756 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
2757 default:
2758 MISSING_CASE(val);
2759 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
2760 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
2761 break;
2762 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
2763 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
2764 break;
2765 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
2766 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
2767 break;
2768 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
2769 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
2770 break;
2771 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
2772 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
2773 break;
2776 val = I915_READ(CNL_PORT_COMP_DW1);
2777 val &= ~((0xff << 16) | 0xff);
2778 val |= procmon->dw1;
2779 I915_WRITE(CNL_PORT_COMP_DW1, val);
2781 I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
2782 I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
2785 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
2787 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2788 struct i915_power_well *well;
2789 u32 val;
2791 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2793 /* 1. Enable PCH Reset Handshake */
2794 val = I915_READ(HSW_NDE_RSTWRN_OPT);
2795 val |= RESET_PCH_HANDSHAKE_ENABLE;
2796 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2798 /* 2. Enable Comp */
2799 val = I915_READ(CHICKEN_MISC_2);
2800 val &= ~CNL_COMP_PWR_DOWN;
2801 I915_WRITE(CHICKEN_MISC_2, val);
2803 cnl_set_procmon_ref_values(dev_priv);
2805 val = I915_READ(CNL_PORT_COMP_DW0);
2806 val |= COMP_INIT;
2807 I915_WRITE(CNL_PORT_COMP_DW0, val);
2809 /* 3. */
2810 val = I915_READ(CNL_PORT_CL1CM_DW5);
2811 val |= CL_POWER_DOWN_ENABLE;
2812 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2815 * 4. Enable Power Well 1 (PG1).
2816 * The AUX IO power wells will be enabled on demand.
2818 mutex_lock(&power_domains->lock);
2819 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2820 intel_power_well_enable(dev_priv, well);
2821 mutex_unlock(&power_domains->lock);
2823 /* 5. Enable CD clock */
2824 cnl_init_cdclk(dev_priv);
2826 /* 6. Enable DBUF */
2827 gen9_dbuf_enable(dev_priv);
2829 if (resume && dev_priv->csr.dmc_payload)
2830 intel_csr_load_program(dev_priv);
2833 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
2835 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2836 struct i915_power_well *well;
2837 u32 val;
2839 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2841 /* 1. Disable all display engine functions -> aready done */
2843 /* 2. Disable DBUF */
2844 gen9_dbuf_disable(dev_priv);
2846 /* 3. Disable CD clock */
2847 cnl_uninit_cdclk(dev_priv);
2850 * 4. Disable Power Well 1 (PG1).
2851 * The AUX IO power wells are toggled on demand, so they are already
2852 * disabled at this point.
2854 mutex_lock(&power_domains->lock);
2855 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2856 intel_power_well_disable(dev_priv, well);
2857 mutex_unlock(&power_domains->lock);
2859 usleep_range(10, 30); /* 10 us delay per Bspec */
2861 /* 5. Disable Comp */
2862 val = I915_READ(CHICKEN_MISC_2);
2863 val |= CNL_COMP_PWR_DOWN;
2864 I915_WRITE(CHICKEN_MISC_2, val);
2867 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2869 struct i915_power_well *cmn_bc =
2870 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2871 struct i915_power_well *cmn_d =
2872 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2875 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2876 * workaround never ever read DISPLAY_PHY_CONTROL, and
2877 * instead maintain a shadow copy ourselves. Use the actual
2878 * power well state and lane status to reconstruct the
2879 * expected initial value.
2881 dev_priv->chv_phy_control =
2882 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2883 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2884 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2885 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2886 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2889 * If all lanes are disabled we leave the override disabled
2890 * with all power down bits cleared to match the state we
2891 * would use after disabling the port. Otherwise enable the
2892 * override and set the lane powerdown bits accding to the
2893 * current lane status.
2895 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2896 uint32_t status = I915_READ(DPLL(PIPE_A));
2897 unsigned int mask;
2899 mask = status & DPLL_PORTB_READY_MASK;
2900 if (mask == 0xf)
2901 mask = 0x0;
2902 else
2903 dev_priv->chv_phy_control |=
2904 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2906 dev_priv->chv_phy_control |=
2907 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2909 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2910 if (mask == 0xf)
2911 mask = 0x0;
2912 else
2913 dev_priv->chv_phy_control |=
2914 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2916 dev_priv->chv_phy_control |=
2917 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2919 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2921 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2922 } else {
2923 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2926 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2927 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2928 unsigned int mask;
2930 mask = status & DPLL_PORTD_READY_MASK;
2932 if (mask == 0xf)
2933 mask = 0x0;
2934 else
2935 dev_priv->chv_phy_control |=
2936 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2938 dev_priv->chv_phy_control |=
2939 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2941 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2943 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2944 } else {
2945 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2948 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2950 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2951 dev_priv->chv_phy_control);
2954 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2956 struct i915_power_well *cmn =
2957 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2958 struct i915_power_well *disp2d =
2959 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2961 /* If the display might be already active skip this */
2962 if (cmn->ops->is_enabled(dev_priv, cmn) &&
2963 disp2d->ops->is_enabled(dev_priv, disp2d) &&
2964 I915_READ(DPIO_CTL) & DPIO_CMNRST)
2965 return;
2967 DRM_DEBUG_KMS("toggling display PHY side reset\n");
2969 /* cmnlane needs DPLL registers */
2970 disp2d->ops->enable(dev_priv, disp2d);
2973 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2974 * Need to assert and de-assert PHY SB reset by gating the
2975 * common lane power, then un-gating it.
2976 * Simply ungating isn't enough to reset the PHY enough to get
2977 * ports and lanes running.
2979 cmn->ops->disable(dev_priv, cmn);
2983 * intel_power_domains_init_hw - initialize hardware power domain state
2984 * @dev_priv: i915 device instance
2985 * @resume: Called from resume code paths or not
2987 * This function initializes the hardware power domain state and enables all
2988 * power wells belonging to the INIT power domain. Power wells in other
2989 * domains (and not in the INIT domain) are referenced or disabled during the
2990 * modeset state HW readout. After that the reference count of each power well
2991 * must match its HW enabled state, see intel_power_domains_verify_state().
2993 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2995 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2997 power_domains->initializing = true;
2999 if (IS_CANNONLAKE(dev_priv)) {
3000 cnl_display_core_init(dev_priv, resume);
3001 } else if (IS_GEN9_BC(dev_priv)) {
3002 skl_display_core_init(dev_priv, resume);
3003 } else if (IS_GEN9_LP(dev_priv)) {
3004 bxt_display_core_init(dev_priv, resume);
3005 } else if (IS_CHERRYVIEW(dev_priv)) {
3006 mutex_lock(&power_domains->lock);
3007 chv_phy_control_init(dev_priv);
3008 mutex_unlock(&power_domains->lock);
3009 } else if (IS_VALLEYVIEW(dev_priv)) {
3010 mutex_lock(&power_domains->lock);
3011 vlv_cmnlane_wa(dev_priv);
3012 mutex_unlock(&power_domains->lock);
3015 /* For now, we need the power well to be always enabled. */
3016 intel_display_set_init_power(dev_priv, true);
3017 /* Disable power support if the user asked so. */
3018 if (!i915_modparams.disable_power_well)
3019 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
3020 intel_power_domains_sync_hw(dev_priv);
3021 power_domains->initializing = false;
3025 * intel_power_domains_suspend - suspend power domain state
3026 * @dev_priv: i915 device instance
3028 * This function prepares the hardware power domain state before entering
3029 * system suspend. It must be paired with intel_power_domains_init_hw().
3031 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
3034 * Even if power well support was disabled we still want to disable
3035 * power wells while we are system suspended.
3037 if (!i915_modparams.disable_power_well)
3038 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3040 if (IS_CANNONLAKE(dev_priv))
3041 cnl_display_core_uninit(dev_priv);
3042 else if (IS_GEN9_BC(dev_priv))
3043 skl_display_core_uninit(dev_priv);
3044 else if (IS_GEN9_LP(dev_priv))
3045 bxt_display_core_uninit(dev_priv);
3048 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
3050 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3051 struct i915_power_well *power_well;
3053 for_each_power_well(dev_priv, power_well) {
3054 enum intel_display_power_domain domain;
3056 DRM_DEBUG_DRIVER("%-25s %d\n",
3057 power_well->name, power_well->count);
3059 for_each_power_domain(domain, power_well->domains)
3060 DRM_DEBUG_DRIVER(" %-23s %d\n",
3061 intel_display_power_domain_str(domain),
3062 power_domains->domain_use_count[domain]);
3067 * intel_power_domains_verify_state - verify the HW/SW state for all power wells
3068 * @dev_priv: i915 device instance
3070 * Verify if the reference count of each power well matches its HW enabled
3071 * state and the total refcount of the domains it belongs to. This must be
3072 * called after modeset HW state sanitization, which is responsible for
3073 * acquiring reference counts for any power wells in use and disabling the
3074 * ones left on by BIOS but not required by any active output.
3076 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
3078 struct i915_power_domains *power_domains = &dev_priv->power_domains;
3079 struct i915_power_well *power_well;
3080 bool dump_domain_info;
3082 mutex_lock(&power_domains->lock);
3084 dump_domain_info = false;
3085 for_each_power_well(dev_priv, power_well) {
3086 enum intel_display_power_domain domain;
3087 int domains_count;
3088 bool enabled;
3091 * Power wells not belonging to any domain (like the MISC_IO
3092 * and PW1 power wells) are under FW control, so ignore them,
3093 * since their state can change asynchronously.
3095 if (!power_well->domains)
3096 continue;
3098 enabled = power_well->ops->is_enabled(dev_priv, power_well);
3099 if ((power_well->count || power_well->always_on) != enabled)
3100 DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)",
3101 power_well->name, power_well->count, enabled);
3103 domains_count = 0;
3104 for_each_power_domain(domain, power_well->domains)
3105 domains_count += power_domains->domain_use_count[domain];
3107 if (power_well->count != domains_count) {
3108 DRM_ERROR("power well %s refcount/domain refcount mismatch "
3109 "(refcount %d/domains refcount %d)\n",
3110 power_well->name, power_well->count,
3111 domains_count);
3112 dump_domain_info = true;
3116 if (dump_domain_info) {
3117 static bool dumped;
3119 if (!dumped) {
3120 intel_power_domains_dump_info(dev_priv);
3121 dumped = true;
3125 mutex_unlock(&power_domains->lock);
3129 * intel_runtime_pm_get - grab a runtime pm reference
3130 * @dev_priv: i915 device instance
3132 * This function grabs a device-level runtime pm reference (mostly used for GEM
3133 * code to ensure the GTT or GT is on) and ensures that it is powered up.
3135 * Any runtime pm reference obtained by this function must have a symmetric
3136 * call to intel_runtime_pm_put() to release the reference again.
3138 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
3140 struct pci_dev *pdev = dev_priv->drm.pdev;
3141 struct device *kdev = &pdev->dev;
3142 int ret;
3144 ret = pm_runtime_get_sync(kdev);
3145 WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
3147 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
3148 assert_rpm_wakelock_held(dev_priv);
3152 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
3153 * @dev_priv: i915 device instance
3155 * This function grabs a device-level runtime pm reference if the device is
3156 * already in use and ensures that it is powered up.
3158 * Any runtime pm reference obtained by this function must have a symmetric
3159 * call to intel_runtime_pm_put() to release the reference again.
3161 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
3163 struct pci_dev *pdev = dev_priv->drm.pdev;
3164 struct device *kdev = &pdev->dev;
3166 if (IS_ENABLED(CONFIG_PM)) {
3167 int ret = pm_runtime_get_if_in_use(kdev);
3170 * In cases runtime PM is disabled by the RPM core and we get
3171 * an -EINVAL return value we are not supposed to call this
3172 * function, since the power state is undefined. This applies
3173 * atm to the late/early system suspend/resume handlers.
3175 WARN_ONCE(ret < 0,
3176 "pm_runtime_get_if_in_use() failed: %d\n", ret);
3177 if (ret <= 0)
3178 return false;
3181 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
3182 assert_rpm_wakelock_held(dev_priv);
3184 return true;
3188 * intel_runtime_pm_get_noresume - grab a runtime pm reference
3189 * @dev_priv: i915 device instance
3191 * This function grabs a device-level runtime pm reference (mostly used for GEM
3192 * code to ensure the GTT or GT is on).
3194 * It will _not_ power up the device but instead only check that it's powered
3195 * on. Therefore it is only valid to call this functions from contexts where
3196 * the device is known to be powered up and where trying to power it up would
3197 * result in hilarity and deadlocks. That pretty much means only the system
3198 * suspend/resume code where this is used to grab runtime pm references for
3199 * delayed setup down in work items.
3201 * Any runtime pm reference obtained by this function must have a symmetric
3202 * call to intel_runtime_pm_put() to release the reference again.
3204 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
3206 struct pci_dev *pdev = dev_priv->drm.pdev;
3207 struct device *kdev = &pdev->dev;
3209 assert_rpm_wakelock_held(dev_priv);
3210 pm_runtime_get_noresume(kdev);
3212 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
3216 * intel_runtime_pm_put - release a runtime pm reference
3217 * @dev_priv: i915 device instance
3219 * This function drops the device-level runtime pm reference obtained by
3220 * intel_runtime_pm_get() and might power down the corresponding
3221 * hardware block right away if this is the last reference.
3223 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
3225 struct pci_dev *pdev = dev_priv->drm.pdev;
3226 struct device *kdev = &pdev->dev;
3228 assert_rpm_wakelock_held(dev_priv);
3229 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
3231 pm_runtime_mark_last_busy(kdev);
3232 pm_runtime_put_autosuspend(kdev);
3236 * intel_runtime_pm_enable - enable runtime pm
3237 * @dev_priv: i915 device instance
3239 * This function enables runtime pm at the end of the driver load sequence.
3241 * Note that this function does currently not enable runtime pm for the
3242 * subordinate display power domains. That is only done on the first modeset
3243 * using intel_display_set_init_power().
3245 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
3247 struct pci_dev *pdev = dev_priv->drm.pdev;
3248 struct device *kdev = &pdev->dev;
3250 pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
3251 pm_runtime_mark_last_busy(kdev);
3254 * Take a permanent reference to disable the RPM functionality and drop
3255 * it only when unloading the driver. Use the low level get/put helpers,
3256 * so the driver's own RPM reference tracking asserts also work on
3257 * platforms without RPM support.
3259 if (!HAS_RUNTIME_PM(dev_priv)) {
3260 int ret;
3262 pm_runtime_dont_use_autosuspend(kdev);
3263 ret = pm_runtime_get_sync(kdev);
3264 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
3265 } else {
3266 pm_runtime_use_autosuspend(kdev);
3270 * The core calls the driver load handler with an RPM reference held.
3271 * We drop that here and will reacquire it during unloading in
3272 * intel_power_domains_fini().
3274 pm_runtime_put_autosuspend(kdev);