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bpf: Prevent memory disambiguation attack
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_sprite.c
blobfb95074a67ff4801eef91f4980c24dc94bf309f7
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32 #include <drm/drmP.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_rect.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_plane_helper.h>
39 #include "intel_drv.h"
40 #include "intel_frontbuffer.h"
41 #include <drm/i915_drm.h>
42 #include "i915_drv.h"
43
44 static bool
45 format_is_yuv(uint32_t format)
46 {
47 switch (format) {
48 case DRM_FORMAT_YUYV:
49 case DRM_FORMAT_UYVY:
50 case DRM_FORMAT_VYUY:
51 case DRM_FORMAT_YVYU:
52 return true;
53 default:
54 return false;
55 }
56 }
57
58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
59 int usecs)
60 {
61 /* paranoia */
62 if (!adjusted_mode->crtc_htotal)
63 return 1;
64
65 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
66 1000 * adjusted_mode->crtc_htotal);
67 }
68
69 /* FIXME: We should instead only take spinlocks once for the entire update
70 * instead of once per mmio. */
71 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
72 #define VBLANK_EVASION_TIME_US 250
73 #else
74 #define VBLANK_EVASION_TIME_US 100
75 #endif
76
77 /**
78 * intel_pipe_update_start() - start update of a set of display registers
79 * @new_crtc_state: the new crtc state
80 *
81 * Mark the start of an update to pipe registers that should be updated
82 * atomically regarding vblank. If the next vblank will happens within
83 * the next 100 us, this function waits until the vblank passes.
84 *
85 * After a successful call to this function, interrupts will be disabled
86 * until a subsequent call to intel_pipe_update_end(). That is done to
87 * avoid random delays.
88 */
89 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
90 {
91 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
92 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
93 const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
94 long timeout = msecs_to_jiffies_timeout(1);
95 int scanline, min, max, vblank_start;
96 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
97 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
98 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
99 DEFINE_WAIT(wait);
100
101 vblank_start = adjusted_mode->crtc_vblank_start;
102 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
103 vblank_start = DIV_ROUND_UP(vblank_start, 2);
104
105 /* FIXME needs to be calibrated sensibly */
106 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
107 VBLANK_EVASION_TIME_US);
108 max = vblank_start - 1;
109
110 local_irq_disable();
111
112 if (min <= 0 || max <= 0)
113 return;
114
115 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
116 return;
117
118 crtc->debug.min_vbl = min;
119 crtc->debug.max_vbl = max;
120 trace_i915_pipe_update_start(crtc);
121
122 for (;;) {
123 /*
124 * prepare_to_wait() has a memory barrier, which guarantees
125 * other CPUs can see the task state update by the time we
126 * read the scanline.
127 */
128 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
129
130 scanline = intel_get_crtc_scanline(crtc);
131 if (scanline < min || scanline > max)
132 break;
133
134 if (timeout <= 0) {
135 DRM_ERROR("Potential atomic update failure on pipe %c\n",
136 pipe_name(crtc->pipe));
137 break;
138 }
139
140 local_irq_enable();
141
142 timeout = schedule_timeout(timeout);
143
144 local_irq_disable();
145 }
146
147 finish_wait(wq, &wait);
148
149 drm_crtc_vblank_put(&crtc->base);
150
151 /*
152 * On VLV/CHV DSI the scanline counter would appear to
153 * increment approx. 1/3 of a scanline before start of vblank.
154 * The registers still get latched at start of vblank however.
155 * This means we must not write any registers on the first
156 * line of vblank (since not the whole line is actually in
157 * vblank). And unfortunately we can't use the interrupt to
158 * wait here since it will fire too soon. We could use the
159 * frame start interrupt instead since it will fire after the
160 * critical scanline, but that would require more changes
161 * in the interrupt code. So for now we'll just do the nasty
162 * thing and poll for the bad scanline to pass us by.
163 *
164 * FIXME figure out if BXT+ DSI suffers from this as well
165 */
166 while (need_vlv_dsi_wa && scanline == vblank_start)
167 scanline = intel_get_crtc_scanline(crtc);
168
169 crtc->debug.scanline_start = scanline;
170 crtc->debug.start_vbl_time = ktime_get();
171 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
172
173 trace_i915_pipe_update_vblank_evaded(crtc);
174 }
175
176 /**
177 * intel_pipe_update_end() - end update of a set of display registers
178 * @new_crtc_state: the new crtc state
179 *
180 * Mark the end of an update started with intel_pipe_update_start(). This
181 * re-enables interrupts and verifies the update was actually completed
182 * before a vblank.
183 */
184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
185 {
186 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
187 enum pipe pipe = crtc->pipe;
188 int scanline_end = intel_get_crtc_scanline(crtc);
189 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
190 ktime_t end_vbl_time = ktime_get();
191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
192
193 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
194
195 /* We're still in the vblank-evade critical section, this can't race.
196 * Would be slightly nice to just grab the vblank count and arm the
197 * event outside of the critical section - the spinlock might spin for a
198 * while ... */
199 if (new_crtc_state->base.event) {
200 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
201
202 spin_lock(&crtc->base.dev->event_lock);
203 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
204 spin_unlock(&crtc->base.dev->event_lock);
205
206 new_crtc_state->base.event = NULL;
207 }
208
209 local_irq_enable();
210
211 if (intel_vgpu_active(dev_priv))
212 return;
213
214 if (crtc->debug.start_vbl_count &&
215 crtc->debug.start_vbl_count != end_vbl_count) {
216 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
217 pipe_name(pipe), crtc->debug.start_vbl_count,
218 end_vbl_count,
219 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
220 crtc->debug.min_vbl, crtc->debug.max_vbl,
221 crtc->debug.scanline_start, scanline_end);
222 }
223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
224 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
225 VBLANK_EVASION_TIME_US)
226 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
227 pipe_name(pipe),
228 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
229 VBLANK_EVASION_TIME_US);
230 #endif
231 }
232
233 void
234 skl_update_plane(struct intel_plane *plane,
235 const struct intel_crtc_state *crtc_state,
236 const struct intel_plane_state *plane_state)
237 {
238 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
239 const struct drm_framebuffer *fb = plane_state->base.fb;
240 enum plane_id plane_id = plane->id;
241 enum pipe pipe = plane->pipe;
242 u32 plane_ctl = plane_state->ctl;
243 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
244 u32 surf_addr = plane_state->main.offset;
245 unsigned int rotation = plane_state->base.rotation;
246 u32 stride = skl_plane_stride(fb, 0, rotation);
247 u32 aux_stride = skl_plane_stride(fb, 1, rotation);
248 int crtc_x = plane_state->base.dst.x1;
249 int crtc_y = plane_state->base.dst.y1;
250 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
251 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
252 uint32_t x = plane_state->main.x;
253 uint32_t y = plane_state->main.y;
254 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
255 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
256 unsigned long irqflags;
257
258 /* Sizes are 0 based */
259 src_w--;
260 src_h--;
261 crtc_w--;
262 crtc_h--;
263
264 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
265
266 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
267 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
268 plane_state->color_ctl);
269 if (key->flags) {
270 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
271 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
272 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
273 }
274
275 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
276 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
277 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
278 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
279 (plane_state->aux.offset - surf_addr) | aux_stride);
280 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
281 (plane_state->aux.y << 16) | plane_state->aux.x);
282
283 /* program plane scaler */
284 if (plane_state->scaler_id >= 0) {
285 int scaler_id = plane_state->scaler_id;
286 const struct intel_scaler *scaler;
287
288 scaler = &crtc_state->scaler_state.scalers[scaler_id];
289
290 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
291 PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
292 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
293 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
294 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
295 ((crtc_w + 1) << 16)|(crtc_h + 1));
296
297 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
298 } else {
299 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
300 }
301
302 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
303 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
304 intel_plane_ggtt_offset(plane_state) + surf_addr);
305 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
306
307 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
308 }
309
310 void
311 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
312 {
313 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
314 enum plane_id plane_id = plane->id;
315 enum pipe pipe = plane->pipe;
316 unsigned long irqflags;
317
318 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
319
320 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
321
322 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
323 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
324
325 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
326 }
327
328 bool
329 skl_plane_get_hw_state(struct intel_plane *plane)
330 {
331 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
332 enum intel_display_power_domain power_domain;
333 enum plane_id plane_id = plane->id;
334 enum pipe pipe = plane->pipe;
335 bool ret;
336
337 power_domain = POWER_DOMAIN_PIPE(pipe);
338 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
339 return false;
340
341 ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
342
343 intel_display_power_put(dev_priv, power_domain);
344
345 return ret;
346 }
347
348 static void
349 chv_update_csc(const struct intel_plane_state *plane_state)
350 {
351 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
352 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
353 const struct drm_framebuffer *fb = plane_state->base.fb;
354 enum plane_id plane_id = plane->id;
355
356 /* Seems RGB data bypasses the CSC always */
357 if (!format_is_yuv(fb->format->format))
358 return;
359
360 /*
361 * BT.601 full range YCbCr -> full range RGB
362 *
363 * |r| | 5743 4096 0| |cr|
364 * |g| = |-2925 4096 -1410| x |y |
365 * |b| | 0 4096 7258| |cb|
366 *
367 * Cb and Cr apparently come in as signed already,
368 * and we get full range data in on account of CLRC0/1
369 */
370 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
371 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
372 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
373
374 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4096) | SPCSC_C0(5743));
375 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-2925) | SPCSC_C0(0));
376 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1410) | SPCSC_C0(4096));
377 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4096) | SPCSC_C0(0));
378 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(7258));
379
380 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
381 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
382 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
383
384 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
385 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
386 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
387 }
388
389 #define SIN_0 0
390 #define COS_0 1
391
392 static void
393 vlv_update_clrc(const struct intel_plane_state *plane_state)
394 {
395 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
396 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
397 const struct drm_framebuffer *fb = plane_state->base.fb;
398 enum pipe pipe = plane->pipe;
399 enum plane_id plane_id = plane->id;
400 int contrast, brightness, sh_scale, sh_sin, sh_cos;
401
402 if (format_is_yuv(fb->format->format)) {
403 /*
404 * Expand limited range to full range:
405 * Contrast is applied first and is used to expand Y range.
406 * Brightness is applied second and is used to remove the
407 * offset from Y. Saturation/hue is used to expand CbCr range.
408 */
409 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
410 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
411 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
412 sh_sin = SIN_0 * sh_scale;
413 sh_cos = COS_0 * sh_scale;
414 } else {
415 /* Pass-through everything. */
416 contrast = 1 << 6;
417 brightness = 0;
418 sh_scale = 1 << 7;
419 sh_sin = SIN_0 * sh_scale;
420 sh_cos = COS_0 * sh_scale;
421 }
422
423 /* FIXME these register are single buffered :( */
424 I915_WRITE_FW(SPCLRC0(pipe, plane_id),
425 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
426 I915_WRITE_FW(SPCLRC1(pipe, plane_id),
427 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
428 }
429
430 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
431 const struct intel_plane_state *plane_state)
432 {
433 const struct drm_framebuffer *fb = plane_state->base.fb;
434 unsigned int rotation = plane_state->base.rotation;
435 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
436 u32 sprctl;
437
438 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
439
440 switch (fb->format->format) {
441 case DRM_FORMAT_YUYV:
442 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
443 break;
444 case DRM_FORMAT_YVYU:
445 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
446 break;
447 case DRM_FORMAT_UYVY:
448 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
449 break;
450 case DRM_FORMAT_VYUY:
451 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
452 break;
453 case DRM_FORMAT_RGB565:
454 sprctl |= SP_FORMAT_BGR565;
455 break;
456 case DRM_FORMAT_XRGB8888:
457 sprctl |= SP_FORMAT_BGRX8888;
458 break;
459 case DRM_FORMAT_ARGB8888:
460 sprctl |= SP_FORMAT_BGRA8888;
461 break;
462 case DRM_FORMAT_XBGR2101010:
463 sprctl |= SP_FORMAT_RGBX1010102;
464 break;
465 case DRM_FORMAT_ABGR2101010:
466 sprctl |= SP_FORMAT_RGBA1010102;
467 break;
468 case DRM_FORMAT_XBGR8888:
469 sprctl |= SP_FORMAT_RGBX8888;
470 break;
471 case DRM_FORMAT_ABGR8888:
472 sprctl |= SP_FORMAT_RGBA8888;
473 break;
474 default:
475 MISSING_CASE(fb->format->format);
476 return 0;
477 }
478
479 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
480 sprctl |= SP_TILED;
481
482 if (rotation & DRM_MODE_ROTATE_180)
483 sprctl |= SP_ROTATE_180;
484
485 if (rotation & DRM_MODE_REFLECT_X)
486 sprctl |= SP_MIRROR;
487
488 if (key->flags & I915_SET_COLORKEY_SOURCE)
489 sprctl |= SP_SOURCE_KEY;
490
491 return sprctl;
492 }
493
494 static void
495 vlv_update_plane(struct intel_plane *plane,
496 const struct intel_crtc_state *crtc_state,
497 const struct intel_plane_state *plane_state)
498 {
499 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
500 const struct drm_framebuffer *fb = plane_state->base.fb;
501 enum pipe pipe = plane->pipe;
502 enum plane_id plane_id = plane->id;
503 u32 sprctl = plane_state->ctl;
504 u32 sprsurf_offset = plane_state->main.offset;
505 u32 linear_offset;
506 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
507 int crtc_x = plane_state->base.dst.x1;
508 int crtc_y = plane_state->base.dst.y1;
509 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
510 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
511 uint32_t x = plane_state->main.x;
512 uint32_t y = plane_state->main.y;
513 unsigned long irqflags;
514
515 /* Sizes are 0 based */
516 crtc_w--;
517 crtc_h--;
518
519 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
520
521 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
522
523 vlv_update_clrc(plane_state);
524
525 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
526 chv_update_csc(plane_state);
527
528 if (key->flags) {
529 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
530 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
531 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
532 }
533 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
534 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
535
536 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
537 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
538 else
539 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
540
541 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
542
543 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
544 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
545 I915_WRITE_FW(SPSURF(pipe, plane_id),
546 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
547 POSTING_READ_FW(SPSURF(pipe, plane_id));
548
549 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
550 }
551
552 static void
553 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
554 {
555 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
556 enum pipe pipe = plane->pipe;
557 enum plane_id plane_id = plane->id;
558 unsigned long irqflags;
559
560 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
561
562 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
563
564 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
565 POSTING_READ_FW(SPSURF(pipe, plane_id));
566
567 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
568 }
569
570 static bool
571 vlv_plane_get_hw_state(struct intel_plane *plane)
572 {
573 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
574 enum intel_display_power_domain power_domain;
575 enum plane_id plane_id = plane->id;
576 enum pipe pipe = plane->pipe;
577 bool ret;
578
579 power_domain = POWER_DOMAIN_PIPE(pipe);
580 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
581 return false;
582
583 ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
584
585 intel_display_power_put(dev_priv, power_domain);
586
587 return ret;
588 }
589
590 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
591 const struct intel_plane_state *plane_state)
592 {
593 struct drm_i915_private *dev_priv =
594 to_i915(plane_state->base.plane->dev);
595 const struct drm_framebuffer *fb = plane_state->base.fb;
596 unsigned int rotation = plane_state->base.rotation;
597 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
598 u32 sprctl;
599
600 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
601
602 if (IS_IVYBRIDGE(dev_priv))
603 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
604
605 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
606 sprctl |= SPRITE_PIPE_CSC_ENABLE;
607
608 switch (fb->format->format) {
609 case DRM_FORMAT_XBGR8888:
610 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
611 break;
612 case DRM_FORMAT_XRGB8888:
613 sprctl |= SPRITE_FORMAT_RGBX888;
614 break;
615 case DRM_FORMAT_YUYV:
616 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
617 break;
618 case DRM_FORMAT_YVYU:
619 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
620 break;
621 case DRM_FORMAT_UYVY:
622 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
623 break;
624 case DRM_FORMAT_VYUY:
625 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
626 break;
627 default:
628 MISSING_CASE(fb->format->format);
629 return 0;
630 }
631
632 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
633 sprctl |= SPRITE_TILED;
634
635 if (rotation & DRM_MODE_ROTATE_180)
636 sprctl |= SPRITE_ROTATE_180;
637
638 if (key->flags & I915_SET_COLORKEY_DESTINATION)
639 sprctl |= SPRITE_DEST_KEY;
640 else if (key->flags & I915_SET_COLORKEY_SOURCE)
641 sprctl |= SPRITE_SOURCE_KEY;
642
643 return sprctl;
644 }
645
646 static void
647 ivb_update_plane(struct intel_plane *plane,
648 const struct intel_crtc_state *crtc_state,
649 const struct intel_plane_state *plane_state)
650 {
651 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
652 const struct drm_framebuffer *fb = plane_state->base.fb;
653 enum pipe pipe = plane->pipe;
654 u32 sprctl = plane_state->ctl, sprscale = 0;
655 u32 sprsurf_offset = plane_state->main.offset;
656 u32 linear_offset;
657 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
658 int crtc_x = plane_state->base.dst.x1;
659 int crtc_y = plane_state->base.dst.y1;
660 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
661 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
662 uint32_t x = plane_state->main.x;
663 uint32_t y = plane_state->main.y;
664 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
665 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
666 unsigned long irqflags;
667
668 /* Sizes are 0 based */
669 src_w--;
670 src_h--;
671 crtc_w--;
672 crtc_h--;
673
674 if (crtc_w != src_w || crtc_h != src_h)
675 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
676
677 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
678
679 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
680
681 if (key->flags) {
682 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
683 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
684 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
685 }
686
687 I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
688 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
689
690 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
691 * register */
692 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
693 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
694 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
695 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
696 else
697 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
698
699 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
700 if (plane->can_scale)
701 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
702 I915_WRITE_FW(SPRCTL(pipe), sprctl);
703 I915_WRITE_FW(SPRSURF(pipe),
704 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
705 POSTING_READ_FW(SPRSURF(pipe));
706
707 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
708 }
709
710 static void
711 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
712 {
713 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
714 enum pipe pipe = plane->pipe;
715 unsigned long irqflags;
716
717 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
718
719 I915_WRITE_FW(SPRCTL(pipe), 0);
720 /* Can't leave the scaler enabled... */
721 if (plane->can_scale)
722 I915_WRITE_FW(SPRSCALE(pipe), 0);
723
724 I915_WRITE_FW(SPRSURF(pipe), 0);
725 POSTING_READ_FW(SPRSURF(pipe));
726
727 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
728 }
729
730 static bool
731 ivb_plane_get_hw_state(struct intel_plane *plane)
732 {
733 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
734 enum intel_display_power_domain power_domain;
735 enum pipe pipe = plane->pipe;
736 bool ret;
737
738 power_domain = POWER_DOMAIN_PIPE(pipe);
739 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
740 return false;
741
742 ret = I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
743
744 intel_display_power_put(dev_priv, power_domain);
745
746 return ret;
747 }
748
749 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
750 const struct intel_plane_state *plane_state)
751 {
752 struct drm_i915_private *dev_priv =
753 to_i915(plane_state->base.plane->dev);
754 const struct drm_framebuffer *fb = plane_state->base.fb;
755 unsigned int rotation = plane_state->base.rotation;
756 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
757 u32 dvscntr;
758
759 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
760
761 if (IS_GEN6(dev_priv))
762 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
763
764 switch (fb->format->format) {
765 case DRM_FORMAT_XBGR8888:
766 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
767 break;
768 case DRM_FORMAT_XRGB8888:
769 dvscntr |= DVS_FORMAT_RGBX888;
770 break;
771 case DRM_FORMAT_YUYV:
772 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
773 break;
774 case DRM_FORMAT_YVYU:
775 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
776 break;
777 case DRM_FORMAT_UYVY:
778 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
779 break;
780 case DRM_FORMAT_VYUY:
781 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
782 break;
783 default:
784 MISSING_CASE(fb->format->format);
785 return 0;
786 }
787
788 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
789 dvscntr |= DVS_TILED;
790
791 if (rotation & DRM_MODE_ROTATE_180)
792 dvscntr |= DVS_ROTATE_180;
793
794 if (key->flags & I915_SET_COLORKEY_DESTINATION)
795 dvscntr |= DVS_DEST_KEY;
796 else if (key->flags & I915_SET_COLORKEY_SOURCE)
797 dvscntr |= DVS_SOURCE_KEY;
798
799 return dvscntr;
800 }
801
802 static void
803 g4x_update_plane(struct intel_plane *plane,
804 const struct intel_crtc_state *crtc_state,
805 const struct intel_plane_state *plane_state)
806 {
807 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
808 const struct drm_framebuffer *fb = plane_state->base.fb;
809 enum pipe pipe = plane->pipe;
810 u32 dvscntr = plane_state->ctl, dvsscale = 0;
811 u32 dvssurf_offset = plane_state->main.offset;
812 u32 linear_offset;
813 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
814 int crtc_x = plane_state->base.dst.x1;
815 int crtc_y = plane_state->base.dst.y1;
816 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
817 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
818 uint32_t x = plane_state->main.x;
819 uint32_t y = plane_state->main.y;
820 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
821 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
822 unsigned long irqflags;
823
824 /* Sizes are 0 based */
825 src_w--;
826 src_h--;
827 crtc_w--;
828 crtc_h--;
829
830 if (crtc_w != src_w || crtc_h != src_h)
831 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
832
833 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
834
835 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
836
837 if (key->flags) {
838 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
839 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
840 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
841 }
842
843 I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
844 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
845
846 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
847 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
848 else
849 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
850
851 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
852 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
853 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
854 I915_WRITE_FW(DVSSURF(pipe),
855 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
856 POSTING_READ_FW(DVSSURF(pipe));
857
858 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
859 }
860
861 static void
862 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
863 {
864 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
865 enum pipe pipe = plane->pipe;
866 unsigned long irqflags;
867
868 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
869
870 I915_WRITE_FW(DVSCNTR(pipe), 0);
871 /* Disable the scaler */
872 I915_WRITE_FW(DVSSCALE(pipe), 0);
873
874 I915_WRITE_FW(DVSSURF(pipe), 0);
875 POSTING_READ_FW(DVSSURF(pipe));
876
877 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
878 }
879
880 static bool
881 g4x_plane_get_hw_state(struct intel_plane *plane)
882 {
883 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
884 enum intel_display_power_domain power_domain;
885 enum pipe pipe = plane->pipe;
886 bool ret;
887
888 power_domain = POWER_DOMAIN_PIPE(pipe);
889 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
890 return false;
891
892 ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
893
894 intel_display_power_put(dev_priv, power_domain);
895
896 return ret;
897 }
898
899 static int
900 intel_check_sprite_plane(struct intel_plane *plane,
901 struct intel_crtc_state *crtc_state,
902 struct intel_plane_state *state)
903 {
904 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
905 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
906 struct drm_framebuffer *fb = state->base.fb;
907 int crtc_x, crtc_y;
908 unsigned int crtc_w, crtc_h;
909 uint32_t src_x, src_y, src_w, src_h;
910 struct drm_rect *src = &state->base.src;
911 struct drm_rect *dst = &state->base.dst;
912 const struct drm_rect *clip = &state->clip;
913 int hscale, vscale;
914 int max_scale, min_scale;
915 bool can_scale;
916 int ret;
917
918 *src = drm_plane_state_src(&state->base);
919 *dst = drm_plane_state_dest(&state->base);
920
921 if (!fb) {
922 state->base.visible = false;
923 return 0;
924 }
925
926 /* Don't modify another pipe's plane */
927 if (plane->pipe != crtc->pipe) {
928 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
929 return -EINVAL;
930 }
931
932 /* FIXME check all gen limits */
933 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
934 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
935 return -EINVAL;
936 }
937
938 /* setup can_scale, min_scale, max_scale */
939 if (INTEL_GEN(dev_priv) >= 9) {
940 /* use scaler when colorkey is not required */
941 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
942 can_scale = 1;
943 min_scale = 1;
944 max_scale = skl_max_scale(crtc, crtc_state);
945 } else {
946 can_scale = 0;
947 min_scale = DRM_PLANE_HELPER_NO_SCALING;
948 max_scale = DRM_PLANE_HELPER_NO_SCALING;
949 }
950 } else {
951 can_scale = plane->can_scale;
952 max_scale = plane->max_downscale << 16;
953 min_scale = plane->can_scale ? 1 : (1 << 16);
954 }
955
956 /*
957 * FIXME the following code does a bunch of fuzzy adjustments to the
958 * coordinates and sizes. We probably need some way to decide whether
959 * more strict checking should be done instead.
960 */
961 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
962 state->base.rotation);
963
964 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
965 BUG_ON(hscale < 0);
966
967 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
968 BUG_ON(vscale < 0);
969
970 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
971
972 crtc_x = dst->x1;
973 crtc_y = dst->y1;
974 crtc_w = drm_rect_width(dst);
975 crtc_h = drm_rect_height(dst);
976
977 if (state->base.visible) {
978 /* check again in case clipping clamped the results */
979 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
980 if (hscale < 0) {
981 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
982 drm_rect_debug_print("src: ", src, true);
983 drm_rect_debug_print("dst: ", dst, false);
984
985 return hscale;
986 }
987
988 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
989 if (vscale < 0) {
990 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
991 drm_rect_debug_print("src: ", src, true);
992 drm_rect_debug_print("dst: ", dst, false);
993
994 return vscale;
995 }
996
997 /* Make the source viewport size an exact multiple of the scaling factors. */
998 drm_rect_adjust_size(src,
999 drm_rect_width(dst) * hscale - drm_rect_width(src),
1000 drm_rect_height(dst) * vscale - drm_rect_height(src));
1001
1002 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
1003 state->base.rotation);
1004
1005 /* sanity check to make sure the src viewport wasn't enlarged */
1006 WARN_ON(src->x1 < (int) state->base.src_x ||
1007 src->y1 < (int) state->base.src_y ||
1008 src->x2 > (int) state->base.src_x + state->base.src_w ||
1009 src->y2 > (int) state->base.src_y + state->base.src_h);
1010
1011 /*
1012 * Hardware doesn't handle subpixel coordinates.
1013 * Adjust to (macro)pixel boundary, but be careful not to
1014 * increase the source viewport size, because that could
1015 * push the downscaling factor out of bounds.
1016 */
1017 src_x = src->x1 >> 16;
1018 src_w = drm_rect_width(src) >> 16;
1019 src_y = src->y1 >> 16;
1020 src_h = drm_rect_height(src) >> 16;
1021
1022 if (format_is_yuv(fb->format->format)) {
1023 src_x &= ~1;
1024 src_w &= ~1;
1025
1026 /*
1027 * Must keep src and dst the
1028 * same if we can't scale.
1029 */
1030 if (!can_scale)
1031 crtc_w &= ~1;
1032
1033 if (crtc_w == 0)
1034 state->base.visible = false;
1035 }
1036 }
1037
1038 /* Check size restrictions when scaling */
1039 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
1040 unsigned int width_bytes;
1041 int cpp = fb->format->cpp[0];
1042
1043 WARN_ON(!can_scale);
1044
1045 /* FIXME interlacing min height is 6 */
1046
1047 if (crtc_w < 3 || crtc_h < 3)
1048 state->base.visible = false;
1049
1050 if (src_w < 3 || src_h < 3)
1051 state->base.visible = false;
1052
1053 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1054
1055 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
1056 width_bytes > 4096 || fb->pitches[0] > 4096)) {
1057 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1058 return -EINVAL;
1059 }
1060 }
1061
1062 if (state->base.visible) {
1063 src->x1 = src_x << 16;
1064 src->x2 = (src_x + src_w) << 16;
1065 src->y1 = src_y << 16;
1066 src->y2 = (src_y + src_h) << 16;
1067 }
1068
1069 dst->x1 = crtc_x;
1070 dst->x2 = crtc_x + crtc_w;
1071 dst->y1 = crtc_y;
1072 dst->y2 = crtc_y + crtc_h;
1073
1074 if (INTEL_GEN(dev_priv) >= 9) {
1075 ret = skl_check_plane_surface(state);
1076 if (ret)
1077 return ret;
1078
1079 state->ctl = skl_plane_ctl(crtc_state, state);
1080 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1081 ret = i9xx_check_plane_surface(state);
1082 if (ret)
1083 return ret;
1084
1085 state->ctl = vlv_sprite_ctl(crtc_state, state);
1086 } else if (INTEL_GEN(dev_priv) >= 7) {
1087 ret = i9xx_check_plane_surface(state);
1088 if (ret)
1089 return ret;
1090
1091 state->ctl = ivb_sprite_ctl(crtc_state, state);
1092 } else {
1093 ret = i9xx_check_plane_surface(state);
1094 if (ret)
1095 return ret;
1096
1097 state->ctl = g4x_sprite_ctl(crtc_state, state);
1098 }
1099
1100 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1101 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
1102
1103 return 0;
1104 }
1105
1106 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1107 struct drm_file *file_priv)
1108 {
1109 struct drm_i915_private *dev_priv = to_i915(dev);
1110 struct drm_intel_sprite_colorkey *set = data;
1111 struct drm_plane *plane;
1112 struct drm_plane_state *plane_state;
1113 struct drm_atomic_state *state;
1114 struct drm_modeset_acquire_ctx ctx;
1115 int ret = 0;
1116
1117 /* Make sure we don't try to enable both src & dest simultaneously */
1118 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1119 return -EINVAL;
1120
1121 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1122 set->flags & I915_SET_COLORKEY_DESTINATION)
1123 return -EINVAL;
1124
1125 plane = drm_plane_find(dev, file_priv, set->plane_id);
1126 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1127 return -ENOENT;
1128
1129 drm_modeset_acquire_init(&ctx, 0);
1130
1131 state = drm_atomic_state_alloc(plane->dev);
1132 if (!state) {
1133 ret = -ENOMEM;
1134 goto out;
1135 }
1136 state->acquire_ctx = &ctx;
1137
1138 while (1) {
1139 plane_state = drm_atomic_get_plane_state(state, plane);
1140 ret = PTR_ERR_OR_ZERO(plane_state);
1141 if (!ret) {
1142 to_intel_plane_state(plane_state)->ckey = *set;
1143 ret = drm_atomic_commit(state);
1144 }
1145
1146 if (ret != -EDEADLK)
1147 break;
1148
1149 drm_atomic_state_clear(state);
1150 drm_modeset_backoff(&ctx);
1151 }
1152
1153 drm_atomic_state_put(state);
1154 out:
1155 drm_modeset_drop_locks(&ctx);
1156 drm_modeset_acquire_fini(&ctx);
1157 return ret;
1158 }
1159
1160 static const uint32_t g4x_plane_formats[] = {
1161 DRM_FORMAT_XRGB8888,
1162 DRM_FORMAT_YUYV,
1163 DRM_FORMAT_YVYU,
1164 DRM_FORMAT_UYVY,
1165 DRM_FORMAT_VYUY,
1166 };
1167
1168 static const uint64_t i9xx_plane_format_modifiers[] = {
1169 I915_FORMAT_MOD_X_TILED,
1170 DRM_FORMAT_MOD_LINEAR,
1171 DRM_FORMAT_MOD_INVALID
1172 };
1173
1174 static const uint32_t snb_plane_formats[] = {
1175 DRM_FORMAT_XBGR8888,
1176 DRM_FORMAT_XRGB8888,
1177 DRM_FORMAT_YUYV,
1178 DRM_FORMAT_YVYU,
1179 DRM_FORMAT_UYVY,
1180 DRM_FORMAT_VYUY,
1181 };
1182
1183 static const uint32_t vlv_plane_formats[] = {
1184 DRM_FORMAT_RGB565,
1185 DRM_FORMAT_ABGR8888,
1186 DRM_FORMAT_ARGB8888,
1187 DRM_FORMAT_XBGR8888,
1188 DRM_FORMAT_XRGB8888,
1189 DRM_FORMAT_XBGR2101010,
1190 DRM_FORMAT_ABGR2101010,
1191 DRM_FORMAT_YUYV,
1192 DRM_FORMAT_YVYU,
1193 DRM_FORMAT_UYVY,
1194 DRM_FORMAT_VYUY,
1195 };
1196
1197 static uint32_t skl_plane_formats[] = {
1198 DRM_FORMAT_RGB565,
1199 DRM_FORMAT_ABGR8888,
1200 DRM_FORMAT_ARGB8888,
1201 DRM_FORMAT_XBGR8888,
1202 DRM_FORMAT_XRGB8888,
1203 DRM_FORMAT_YUYV,
1204 DRM_FORMAT_YVYU,
1205 DRM_FORMAT_UYVY,
1206 DRM_FORMAT_VYUY,
1207 };
1208
1209 static const uint64_t skl_plane_format_modifiers[] = {
1210 I915_FORMAT_MOD_X_TILED,
1211 DRM_FORMAT_MOD_LINEAR,
1212 DRM_FORMAT_MOD_INVALID
1213 };
1214
1215 static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane,
1216 uint32_t format,
1217 uint64_t modifier)
1218 {
1219 switch (format) {
1220 case DRM_FORMAT_XBGR8888:
1221 case DRM_FORMAT_XRGB8888:
1222 case DRM_FORMAT_YUYV:
1223 case DRM_FORMAT_YVYU:
1224 case DRM_FORMAT_UYVY:
1225 case DRM_FORMAT_VYUY:
1226 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1227 modifier == I915_FORMAT_MOD_X_TILED)
1228 return true;
1229 /* fall through */
1230 default:
1231 return false;
1232 }
1233 }
1234
1235 static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane,
1236 uint32_t format,
1237 uint64_t modifier)
1238 {
1239 switch (format) {
1240 case DRM_FORMAT_YUYV:
1241 case DRM_FORMAT_YVYU:
1242 case DRM_FORMAT_UYVY:
1243 case DRM_FORMAT_VYUY:
1244 case DRM_FORMAT_RGB565:
1245 case DRM_FORMAT_XRGB8888:
1246 case DRM_FORMAT_ARGB8888:
1247 case DRM_FORMAT_XBGR2101010:
1248 case DRM_FORMAT_ABGR2101010:
1249 case DRM_FORMAT_XBGR8888:
1250 case DRM_FORMAT_ABGR8888:
1251 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1252 modifier == I915_FORMAT_MOD_X_TILED)
1253 return true;
1254 /* fall through */
1255 default:
1256 return false;
1257 }
1258 }
1259
1260 static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane,
1261 uint32_t format,
1262 uint64_t modifier)
1263 {
1264 /* This is the same as primary plane since SKL has universal planes */
1265 switch (format) {
1266 case DRM_FORMAT_XRGB8888:
1267 case DRM_FORMAT_XBGR8888:
1268 case DRM_FORMAT_ARGB8888:
1269 case DRM_FORMAT_ABGR8888:
1270 case DRM_FORMAT_RGB565:
1271 case DRM_FORMAT_XRGB2101010:
1272 case DRM_FORMAT_XBGR2101010:
1273 case DRM_FORMAT_YUYV:
1274 case DRM_FORMAT_YVYU:
1275 case DRM_FORMAT_UYVY:
1276 case DRM_FORMAT_VYUY:
1277 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1278 return true;
1279 /* fall through */
1280 case DRM_FORMAT_C8:
1281 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1282 modifier == I915_FORMAT_MOD_X_TILED ||
1283 modifier == I915_FORMAT_MOD_Y_TILED)
1284 return true;
1285 /* fall through */
1286 default:
1287 return false;
1288 }
1289 }
1290
1291 static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1292 uint32_t format,
1293 uint64_t modifier)
1294 {
1295 struct drm_i915_private *dev_priv = to_i915(plane->dev);
1296
1297 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1298 return false;
1299
1300 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1301 modifier != DRM_FORMAT_MOD_LINEAR)
1302 return false;
1303
1304 if (INTEL_GEN(dev_priv) >= 9)
1305 return skl_sprite_plane_format_mod_supported(plane, format, modifier);
1306 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1307 return vlv_sprite_plane_format_mod_supported(plane, format, modifier);
1308 else
1309 return g4x_sprite_plane_format_mod_supported(plane, format, modifier);
1310
1311 unreachable();
1312 }
1313
1314 static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1315 .update_plane = drm_atomic_helper_update_plane,
1316 .disable_plane = drm_atomic_helper_disable_plane,
1317 .destroy = intel_plane_destroy,
1318 .atomic_get_property = intel_plane_atomic_get_property,
1319 .atomic_set_property = intel_plane_atomic_set_property,
1320 .atomic_duplicate_state = intel_plane_duplicate_state,
1321 .atomic_destroy_state = intel_plane_destroy_state,
1322 .format_mod_supported = intel_sprite_plane_format_mod_supported,
1323 };
1324
1325 struct intel_plane *
1326 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, int plane)
1328 {
1329 struct intel_plane *intel_plane = NULL;
1330 struct intel_plane_state *state = NULL;
1331 unsigned long possible_crtcs;
1332 const uint32_t *plane_formats;
1333 const uint64_t *modifiers;
1334 unsigned int supported_rotations;
1335 int num_plane_formats;
1336 int ret;
1337
1338 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1339 if (!intel_plane) {
1340 ret = -ENOMEM;
1341 goto fail;
1342 }
1343
1344 state = intel_create_plane_state(&intel_plane->base);
1345 if (!state) {
1346 ret = -ENOMEM;
1347 goto fail;
1348 }
1349 intel_plane->base.state = &state->base;
1350
1351 if (INTEL_GEN(dev_priv) >= 10) {
1352 intel_plane->can_scale = true;
1353 state->scaler_id = -1;
1354
1355 intel_plane->update_plane = skl_update_plane;
1356 intel_plane->disable_plane = skl_disable_plane;
1357 intel_plane->get_hw_state = skl_plane_get_hw_state;
1358
1359 plane_formats = skl_plane_formats;
1360 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1361 modifiers = skl_plane_format_modifiers;
1362 } else if (INTEL_GEN(dev_priv) >= 9) {
1363 intel_plane->can_scale = true;
1364 state->scaler_id = -1;
1365
1366 intel_plane->update_plane = skl_update_plane;
1367 intel_plane->disable_plane = skl_disable_plane;
1368 intel_plane->get_hw_state = skl_plane_get_hw_state;
1369
1370 plane_formats = skl_plane_formats;
1371 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1372 modifiers = skl_plane_format_modifiers;
1373 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1374 intel_plane->can_scale = false;
1375 intel_plane->max_downscale = 1;
1376
1377 intel_plane->update_plane = vlv_update_plane;
1378 intel_plane->disable_plane = vlv_disable_plane;
1379 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1380
1381 plane_formats = vlv_plane_formats;
1382 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1383 modifiers = i9xx_plane_format_modifiers;
1384 } else if (INTEL_GEN(dev_priv) >= 7) {
1385 if (IS_IVYBRIDGE(dev_priv)) {
1386 intel_plane->can_scale = true;
1387 intel_plane->max_downscale = 2;
1388 } else {
1389 intel_plane->can_scale = false;
1390 intel_plane->max_downscale = 1;
1391 }
1392
1393 intel_plane->update_plane = ivb_update_plane;
1394 intel_plane->disable_plane = ivb_disable_plane;
1395 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1396
1397 plane_formats = snb_plane_formats;
1398 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1399 modifiers = i9xx_plane_format_modifiers;
1400 } else {
1401 intel_plane->can_scale = true;
1402 intel_plane->max_downscale = 16;
1403
1404 intel_plane->update_plane = g4x_update_plane;
1405 intel_plane->disable_plane = g4x_disable_plane;
1406 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1407
1408 modifiers = i9xx_plane_format_modifiers;
1409 if (IS_GEN6(dev_priv)) {
1410 plane_formats = snb_plane_formats;
1411 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1412 } else {
1413 plane_formats = g4x_plane_formats;
1414 num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1415 }
1416 }
1417
1418 if (INTEL_GEN(dev_priv) >= 9) {
1419 supported_rotations =
1420 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1421 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1422 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1423 supported_rotations =
1424 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1425 DRM_MODE_REFLECT_X;
1426 } else {
1427 supported_rotations =
1428 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1429 }
1430
1431 intel_plane->pipe = pipe;
1432 intel_plane->i9xx_plane = plane;
1433 intel_plane->id = PLANE_SPRITE0 + plane;
1434 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1435 intel_plane->check_plane = intel_check_sprite_plane;
1436
1437 possible_crtcs = (1 << pipe);
1438
1439 if (INTEL_GEN(dev_priv) >= 9)
1440 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1441 possible_crtcs, &intel_sprite_plane_funcs,
1442 plane_formats, num_plane_formats,
1443 modifiers,
1444 DRM_PLANE_TYPE_OVERLAY,
1445 "plane %d%c", plane + 2, pipe_name(pipe));
1446 else
1447 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1448 possible_crtcs, &intel_sprite_plane_funcs,
1449 plane_formats, num_plane_formats,
1450 modifiers,
1451 DRM_PLANE_TYPE_OVERLAY,
1452 "sprite %c", sprite_name(pipe, plane));
1453 if (ret)
1454 goto fail;
1455
1456 drm_plane_create_rotation_property(&intel_plane->base,
1457 DRM_MODE_ROTATE_0,
1458 supported_rotations);
1459
1460 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1461
1462 return intel_plane;
1463
1464 fail:
1465 kfree(state);
1466 kfree(intel_plane);
1467
1468 return ERR_PTR(ret);
1469 }
Linux with added FPC-III support