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bpf: Prevent memory disambiguation attack
[linux/fpc-iii.git] / drivers / gpu / drm / sun4i / sun4i_tcon.c
bloba818ca4916051ade239efa0f4789d5c3cab36165
1 /*
2 * Copyright (C) 2015 Free Electrons
3 * Copyright (C) 2015 NextThing Co
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13 #include <drm/drmP.h>
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_crtc_helper.h>
17 #include <drm/drm_encoder.h>
18 #include <drm/drm_modes.h>
19 #include <drm/drm_of.h>
20
21 #include <uapi/drm/drm_mode.h>
22
23 #include <linux/component.h>
24 #include <linux/ioport.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/of_irq.h>
28 #include <linux/regmap.h>
29 #include <linux/reset.h>
30
31 #include "sun4i_crtc.h"
32 #include "sun4i_dotclock.h"
33 #include "sun4i_drv.h"
34 #include "sun4i_lvds.h"
35 #include "sun4i_rgb.h"
36 #include "sun4i_tcon.h"
37 #include "sunxi_engine.h"
38
39 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
40 {
41 struct drm_connector *connector;
42 struct drm_connector_list_iter iter;
43
44 drm_connector_list_iter_begin(encoder->dev, &iter);
45 drm_for_each_connector_iter(connector, &iter)
46 if (connector->encoder == encoder) {
47 drm_connector_list_iter_end(&iter);
48 return connector;
49 }
50 drm_connector_list_iter_end(&iter);
51
52 return NULL;
53 }
54
55 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
56 {
57 struct drm_connector *connector;
58 struct drm_display_info *info;
59
60 connector = sun4i_tcon_get_connector(encoder);
61 if (!connector)
62 return -EINVAL;
63
64 info = &connector->display_info;
65 if (info->num_bus_formats != 1)
66 return -EINVAL;
67
68 switch (info->bus_formats[0]) {
69 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
70 return 18;
71
72 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
73 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
74 return 24;
75 }
76
77 return -EINVAL;
78 }
79
80 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
81 bool enabled)
82 {
83 struct clk *clk;
84
85 switch (channel) {
86 case 0:
87 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
88 SUN4I_TCON0_CTL_TCON_ENABLE,
89 enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
90 clk = tcon->dclk;
91 break;
92 case 1:
93 WARN_ON(!tcon->quirks->has_channel_1);
94 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
95 SUN4I_TCON1_CTL_TCON_ENABLE,
96 enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
97 clk = tcon->sclk1;
98 break;
99 default:
100 DRM_WARN("Unknown channel... doing nothing\n");
101 return;
102 }
103
104 if (enabled) {
105 clk_prepare_enable(clk);
106 clk_rate_exclusive_get(clk);
107 } else {
108 clk_rate_exclusive_put(clk);
109 clk_disable_unprepare(clk);
110 }
111 }
112
113 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
114 const struct drm_encoder *encoder,
115 bool enabled)
116 {
117 if (enabled) {
118 u8 val;
119
120 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
121 SUN4I_TCON0_LVDS_IF_EN,
122 SUN4I_TCON0_LVDS_IF_EN);
123
124 /*
125 * As their name suggest, these values only apply to the A31
126 * and later SoCs. We'll have to rework this when merging
127 * support for the older SoCs.
128 */
129 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
130 SUN6I_TCON0_LVDS_ANA0_C(2) |
131 SUN6I_TCON0_LVDS_ANA0_V(3) |
132 SUN6I_TCON0_LVDS_ANA0_PD(2) |
133 SUN6I_TCON0_LVDS_ANA0_EN_LDO);
134 udelay(2);
135
136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
137 SUN6I_TCON0_LVDS_ANA0_EN_MB,
138 SUN6I_TCON0_LVDS_ANA0_EN_MB);
139 udelay(2);
140
141 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
142 SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
143 SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
144
145 if (sun4i_tcon_get_pixel_depth(encoder) == 18)
146 val = 7;
147 else
148 val = 0xf;
149
150 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
151 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
152 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
153 } else {
154 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
155 SUN4I_TCON0_LVDS_IF_EN, 0);
156 }
157 }
158
159 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
160 const struct drm_encoder *encoder,
161 bool enabled)
162 {
163 bool is_lvds = false;
164 int channel;
165
166 switch (encoder->encoder_type) {
167 case DRM_MODE_ENCODER_LVDS:
168 is_lvds = true;
169 /* Fallthrough */
170 case DRM_MODE_ENCODER_NONE:
171 channel = 0;
172 break;
173 case DRM_MODE_ENCODER_TMDS:
174 case DRM_MODE_ENCODER_TVDAC:
175 channel = 1;
176 break;
177 default:
178 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
179 return;
180 }
181
182 if (is_lvds && !enabled)
183 sun4i_tcon_lvds_set_status(tcon, encoder, false);
184
185 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
186 SUN4I_TCON_GCTL_TCON_ENABLE,
187 enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
188
189 if (is_lvds && enabled)
190 sun4i_tcon_lvds_set_status(tcon, encoder, true);
191
192 sun4i_tcon_channel_set_status(tcon, channel, enabled);
193 }
194
195 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
196 {
197 u32 mask, val = 0;
198
199 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
200
201 mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
202 SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
203
204 if (enable)
205 val = mask;
206
207 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
208 }
209 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
210
211 /*
212 * This function is a helper for TCON output muxing. The TCON output
213 * muxing control register in earlier SoCs (without the TCON TOP block)
214 * are located in TCON0. This helper returns a pointer to TCON0's
215 * sun4i_tcon structure, or NULL if not found.
216 */
217 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
218 {
219 struct sun4i_drv *drv = drm->dev_private;
220 struct sun4i_tcon *tcon;
221
222 list_for_each_entry(tcon, &drv->tcon_list, list)
223 if (tcon->id == 0)
224 return tcon;
225
226 dev_warn(drm->dev,
227 "TCON0 not found, display output muxing may not work\n");
228
229 return NULL;
230 }
231
232 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
233 const struct drm_encoder *encoder)
234 {
235 int ret = -ENOTSUPP;
236
237 if (tcon->quirks->set_mux)
238 ret = tcon->quirks->set_mux(tcon, encoder);
239
240 DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
241 encoder->name, encoder->crtc->name, ret);
242 }
243
244 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
245 int channel)
246 {
247 int delay = mode->vtotal - mode->vdisplay;
248
249 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
250 delay /= 2;
251
252 if (channel == 1)
253 delay -= 2;
254
255 delay = min(delay, 30);
256
257 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
258
259 return delay;
260 }
261
262 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
263 const struct drm_display_mode *mode)
264 {
265 /* Configure the dot clock */
266 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
267
268 /* Set the resolution */
269 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
270 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
271 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
272 }
273
274 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
275 const struct drm_encoder *encoder,
276 const struct drm_display_mode *mode)
277 {
278 unsigned int bp;
279 u8 clk_delay;
280 u32 reg, val = 0;
281
282 tcon->dclk_min_div = 7;
283 tcon->dclk_max_div = 7;
284 sun4i_tcon0_mode_set_common(tcon, mode);
285
286 /* Adjust clock delay */
287 clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
288 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
289 SUN4I_TCON0_CTL_CLK_DELAY_MASK,
290 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
291
292 /*
293 * This is called a backporch in the register documentation,
294 * but it really is the back porch + hsync
295 */
296 bp = mode->crtc_htotal - mode->crtc_hsync_start;
297 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
298 mode->crtc_htotal, bp);
299
300 /* Set horizontal display timings */
301 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
302 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
303 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
304
305 /*
306 * This is called a backporch in the register documentation,
307 * but it really is the back porch + hsync
308 */
309 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
310 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
311 mode->crtc_vtotal, bp);
312
313 /* Set vertical display timings */
314 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
315 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
316 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
317
318 reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
319 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
320 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
321 if (sun4i_tcon_get_pixel_depth(encoder) == 24)
322 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
323 else
324 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
325
326 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
327
328 /* Setup the polarity of the various signals */
329 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
330 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
331
332 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
333 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
334
335 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
336
337 /* Map output pins to channel 0 */
338 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
339 SUN4I_TCON_GCTL_IOMAP_MASK,
340 SUN4I_TCON_GCTL_IOMAP_TCON0);
341
342 /* Enable the output on the pins */
343 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
344 }
345
346 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
347 const struct drm_display_mode *mode)
348 {
349 unsigned int bp, hsync, vsync;
350 u8 clk_delay;
351 u32 val = 0;
352
353 tcon->dclk_min_div = 6;
354 tcon->dclk_max_div = 127;
355 sun4i_tcon0_mode_set_common(tcon, mode);
356
357 /* Adjust clock delay */
358 clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
359 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
360 SUN4I_TCON0_CTL_CLK_DELAY_MASK,
361 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
362
363 /*
364 * This is called a backporch in the register documentation,
365 * but it really is the back porch + hsync
366 */
367 bp = mode->crtc_htotal - mode->crtc_hsync_start;
368 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
369 mode->crtc_htotal, bp);
370
371 /* Set horizontal display timings */
372 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
373 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
374 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
375
376 /*
377 * This is called a backporch in the register documentation,
378 * but it really is the back porch + hsync
379 */
380 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
381 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
382 mode->crtc_vtotal, bp);
383
384 /* Set vertical display timings */
385 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
386 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
387 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
388
389 /* Set Hsync and Vsync length */
390 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
391 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
392 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
393 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
394 SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
395 SUN4I_TCON0_BASIC3_H_SYNC(hsync));
396
397 /* Setup the polarity of the various signals */
398 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
399 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
400
401 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
402 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
403
404 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
405 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
406 val);
407
408 /* Map output pins to channel 0 */
409 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
410 SUN4I_TCON_GCTL_IOMAP_MASK,
411 SUN4I_TCON_GCTL_IOMAP_TCON0);
412
413 /* Enable the output on the pins */
414 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
415 }
416
417 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
418 const struct drm_display_mode *mode)
419 {
420 unsigned int bp, hsync, vsync, vtotal;
421 u8 clk_delay;
422 u32 val;
423
424 WARN_ON(!tcon->quirks->has_channel_1);
425
426 /* Configure the dot clock */
427 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
428
429 /* Adjust clock delay */
430 clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
431 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
432 SUN4I_TCON1_CTL_CLK_DELAY_MASK,
433 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
434
435 /* Set interlaced mode */
436 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
437 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
438 else
439 val = 0;
440 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
441 SUN4I_TCON1_CTL_INTERLACE_ENABLE,
442 val);
443
444 /* Set the input resolution */
445 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
446 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
447 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
448
449 /* Set the upscaling resolution */
450 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
451 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
452 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
453
454 /* Set the output resolution */
455 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
456 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
457 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
458
459 /* Set horizontal display timings */
460 bp = mode->crtc_htotal - mode->crtc_hsync_start;
461 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
462 mode->htotal, bp);
463 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
464 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
465 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
466
467 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
468 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
469 mode->crtc_vtotal, bp);
470
471 /*
472 * The vertical resolution needs to be doubled in all
473 * cases. We could use crtc_vtotal and always multiply by two,
474 * but that leads to a rounding error in interlace when vtotal
475 * is odd.
476 *
477 * This happens with TV's PAL for example, where vtotal will
478 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
479 * 624, which apparently confuses the hardware.
480 *
481 * To work around this, we will always use vtotal, and
482 * multiply by two only if we're not in interlace.
483 */
484 vtotal = mode->vtotal;
485 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
486 vtotal = vtotal * 2;
487
488 /* Set vertical display timings */
489 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
490 SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
491 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
492
493 /* Set Hsync and Vsync length */
494 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
495 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
496 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
497 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
498 SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
499 SUN4I_TCON1_BASIC5_H_SYNC(hsync));
500
501 /* Map output pins to channel 1 */
502 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
503 SUN4I_TCON_GCTL_IOMAP_MASK,
504 SUN4I_TCON_GCTL_IOMAP_TCON1);
505 }
506
507 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
508 const struct drm_encoder *encoder,
509 const struct drm_display_mode *mode)
510 {
511 switch (encoder->encoder_type) {
512 case DRM_MODE_ENCODER_LVDS:
513 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
514 break;
515 case DRM_MODE_ENCODER_NONE:
516 sun4i_tcon0_mode_set_rgb(tcon, mode);
517 sun4i_tcon_set_mux(tcon, 0, encoder);
518 break;
519 case DRM_MODE_ENCODER_TVDAC:
520 case DRM_MODE_ENCODER_TMDS:
521 sun4i_tcon1_mode_set(tcon, mode);
522 sun4i_tcon_set_mux(tcon, 1, encoder);
523 break;
524 default:
525 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
526 }
527 }
528 EXPORT_SYMBOL(sun4i_tcon_mode_set);
529
530 static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
531 struct sun4i_crtc *scrtc)
532 {
533 unsigned long flags;
534
535 spin_lock_irqsave(&dev->event_lock, flags);
536 if (scrtc->event) {
537 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
538 drm_crtc_vblank_put(&scrtc->crtc);
539 scrtc->event = NULL;
540 }
541 spin_unlock_irqrestore(&dev->event_lock, flags);
542 }
543
544 static irqreturn_t sun4i_tcon_handler(int irq, void *private)
545 {
546 struct sun4i_tcon *tcon = private;
547 struct drm_device *drm = tcon->drm;
548 struct sun4i_crtc *scrtc = tcon->crtc;
549 unsigned int status;
550
551 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
552
553 if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
554 SUN4I_TCON_GINT0_VBLANK_INT(1))))
555 return IRQ_NONE;
556
557 drm_crtc_handle_vblank(&scrtc->crtc);
558 sun4i_tcon_finish_page_flip(drm, scrtc);
559
560 /* Acknowledge the interrupt */
561 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
562 SUN4I_TCON_GINT0_VBLANK_INT(0) |
563 SUN4I_TCON_GINT0_VBLANK_INT(1),
564 0);
565
566 return IRQ_HANDLED;
567 }
568
569 static int sun4i_tcon_init_clocks(struct device *dev,
570 struct sun4i_tcon *tcon)
571 {
572 tcon->clk = devm_clk_get(dev, "ahb");
573 if (IS_ERR(tcon->clk)) {
574 dev_err(dev, "Couldn't get the TCON bus clock\n");
575 return PTR_ERR(tcon->clk);
576 }
577 clk_prepare_enable(tcon->clk);
578
579 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
580 if (IS_ERR(tcon->sclk0)) {
581 dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
582 return PTR_ERR(tcon->sclk0);
583 }
584
585 if (tcon->quirks->has_channel_1) {
586 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
587 if (IS_ERR(tcon->sclk1)) {
588 dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
589 return PTR_ERR(tcon->sclk1);
590 }
591 }
592
593 return 0;
594 }
595
596 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
597 {
598 clk_disable_unprepare(tcon->clk);
599 }
600
601 static int sun4i_tcon_init_irq(struct device *dev,
602 struct sun4i_tcon *tcon)
603 {
604 struct platform_device *pdev = to_platform_device(dev);
605 int irq, ret;
606
607 irq = platform_get_irq(pdev, 0);
608 if (irq < 0) {
609 dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
610 return irq;
611 }
612
613 ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
614 dev_name(dev), tcon);
615 if (ret) {
616 dev_err(dev, "Couldn't request the IRQ\n");
617 return ret;
618 }
619
620 return 0;
621 }
622
623 static struct regmap_config sun4i_tcon_regmap_config = {
624 .reg_bits = 32,
625 .val_bits = 32,
626 .reg_stride = 4,
627 .max_register = 0x800,
628 };
629
630 static int sun4i_tcon_init_regmap(struct device *dev,
631 struct sun4i_tcon *tcon)
632 {
633 struct platform_device *pdev = to_platform_device(dev);
634 struct resource *res;
635 void __iomem *regs;
636
637 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
638 regs = devm_ioremap_resource(dev, res);
639 if (IS_ERR(regs))
640 return PTR_ERR(regs);
641
642 tcon->regs = devm_regmap_init_mmio(dev, regs,
643 &sun4i_tcon_regmap_config);
644 if (IS_ERR(tcon->regs)) {
645 dev_err(dev, "Couldn't create the TCON regmap\n");
646 return PTR_ERR(tcon->regs);
647 }
648
649 /* Make sure the TCON is disabled and all IRQs are off */
650 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
651 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
652 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
653
654 /* Disable IO lines and set them to tristate */
655 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
656 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
657
658 return 0;
659 }
660
661 /*
662 * On SoCs with the old display pipeline design (Display Engine 1.0),
663 * the TCON is always tied to just one backend. Hence we can traverse
664 * the of_graph upwards to find the backend our tcon is connected to,
665 * and take its ID as our own.
666 *
667 * We can either identify backends from their compatible strings, which
668 * means maintaining a large list of them. Or, since the backend is
669 * registered and binded before the TCON, we can just go through the
670 * list of registered backends and compare the device node.
671 *
672 * As the structures now store engines instead of backends, here this
673 * function in fact searches the corresponding engine, and the ID is
674 * requested via the get_id function of the engine.
675 */
676 static struct sunxi_engine *
677 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
678 struct device_node *node)
679 {
680 struct device_node *port, *ep, *remote;
681 struct sunxi_engine *engine = ERR_PTR(-EINVAL);
682
683 port = of_graph_get_port_by_id(node, 0);
684 if (!port)
685 return ERR_PTR(-EINVAL);
686
687 /*
688 * This only works if there is only one path from the TCON
689 * to any display engine. Otherwise the probe order of the
690 * TCONs and display engines is not guaranteed. They may
691 * either bind to the wrong one, or worse, bind to the same
692 * one if additional checks are not done.
693 *
694 * Bail out if there are multiple input connections.
695 */
696 if (of_get_available_child_count(port) != 1)
697 goto out_put_port;
698
699 /* Get the first connection without specifying an ID */
700 ep = of_get_next_available_child(port, NULL);
701 if (!ep)
702 goto out_put_port;
703
704 remote = of_graph_get_remote_port_parent(ep);
705 if (!remote)
706 goto out_put_ep;
707
708 /* does this node match any registered engines? */
709 list_for_each_entry(engine, &drv->engine_list, list)
710 if (remote == engine->node)
711 goto out_put_remote;
712
713 /* keep looking through upstream ports */
714 engine = sun4i_tcon_find_engine_traverse(drv, remote);
715
716 out_put_remote:
717 of_node_put(remote);
718 out_put_ep:
719 of_node_put(ep);
720 out_put_port:
721 of_node_put(port);
722
723 return engine;
724 }
725
726 /*
727 * The device tree binding says that the remote endpoint ID of any
728 * connection between components, up to and including the TCON, of
729 * the display pipeline should be equal to the actual ID of the local
730 * component. Thus we can look at any one of the input connections of
731 * the TCONs, and use that connection's remote endpoint ID as our own.
732 *
733 * Since the user of this function already finds the input port,
734 * the port is passed in directly without further checks.
735 */
736 static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
737 {
738 struct device_node *ep;
739 int ret = -EINVAL;
740
741 /* try finding an upstream endpoint */
742 for_each_available_child_of_node(port, ep) {
743 struct device_node *remote;
744 u32 reg;
745
746 remote = of_graph_get_remote_endpoint(ep);
747 if (!remote)
748 continue;
749
750 ret = of_property_read_u32(remote, "reg", &reg);
751 if (ret)
752 continue;
753
754 ret = reg;
755 }
756
757 return ret;
758 }
759
760 /*
761 * Once we know the TCON's id, we can look through the list of
762 * engines to find a matching one. We assume all engines have
763 * been probed and added to the list.
764 */
765 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
766 int id)
767 {
768 struct sunxi_engine *engine;
769
770 list_for_each_entry(engine, &drv->engine_list, list)
771 if (engine->id == id)
772 return engine;
773
774 return ERR_PTR(-EINVAL);
775 }
776
777 /*
778 * On SoCs with the old display pipeline design (Display Engine 1.0),
779 * we assumed the TCON was always tied to just one backend. However
780 * this proved not to be the case. On the A31, the TCON can select
781 * either backend as its source. On the A20 (and likely on the A10),
782 * the backend can choose which TCON to output to.
783 *
784 * The device tree binding says that the remote endpoint ID of any
785 * connection between components, up to and including the TCON, of
786 * the display pipeline should be equal to the actual ID of the local
787 * component. Thus we should be able to look at any one of the input
788 * connections of the TCONs, and use that connection's remote endpoint
789 * ID as our own.
790 *
791 * However the connections between the backend and TCON were assumed
792 * to be always singular, and their endpoit IDs were all incorrectly
793 * set to 0. This means for these old device trees, we cannot just look
794 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
795 * incorrectly identified as TCON0.
796 *
797 * This function first checks if the TCON node has 2 input endpoints.
798 * If so, then the device tree is a corrected version, and it will use
799 * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
800 * to fetch the ID and engine directly. If not, then it is likely an
801 * old device trees, where the endpoint IDs were incorrect, but did not
802 * have endpoint connections between the backend and TCON across
803 * different display pipelines. It will fall back to the old method of
804 * traversing the of_graph to try and find a matching engine by device
805 * node.
806 *
807 * In the case of single display pipeline device trees, either method
808 * works.
809 */
810 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
811 struct device_node *node)
812 {
813 struct device_node *port;
814 struct sunxi_engine *engine;
815
816 port = of_graph_get_port_by_id(node, 0);
817 if (!port)
818 return ERR_PTR(-EINVAL);
819
820 /*
821 * Is this a corrected device tree with cross pipeline
822 * connections between the backend and TCON?
823 */
824 if (of_get_child_count(port) > 1) {
825 /* Get our ID directly from an upstream endpoint */
826 int id = sun4i_tcon_of_get_id_from_port(port);
827
828 /* Get our engine by matching our ID */
829 engine = sun4i_tcon_get_engine_by_id(drv, id);
830
831 of_node_put(port);
832 return engine;
833 }
834
835 /* Fallback to old method by traversing input endpoints */
836 of_node_put(port);
837 return sun4i_tcon_find_engine_traverse(drv, node);
838 }
839
840 static int sun4i_tcon_bind(struct device *dev, struct device *master,
841 void *data)
842 {
843 struct drm_device *drm = data;
844 struct sun4i_drv *drv = drm->dev_private;
845 struct sunxi_engine *engine;
846 struct device_node *remote;
847 struct sun4i_tcon *tcon;
848 bool has_lvds_rst, has_lvds_alt, can_lvds;
849 int ret;
850
851 engine = sun4i_tcon_find_engine(drv, dev->of_node);
852 if (IS_ERR(engine)) {
853 dev_err(dev, "Couldn't find matching engine\n");
854 return -EPROBE_DEFER;
855 }
856
857 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
858 if (!tcon)
859 return -ENOMEM;
860 dev_set_drvdata(dev, tcon);
861 tcon->drm = drm;
862 tcon->dev = dev;
863 tcon->id = engine->id;
864 tcon->quirks = of_device_get_match_data(dev);
865
866 tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
867 if (IS_ERR(tcon->lcd_rst)) {
868 dev_err(dev, "Couldn't get our reset line\n");
869 return PTR_ERR(tcon->lcd_rst);
870 }
871
872 /* Make sure our TCON is reset */
873 ret = reset_control_reset(tcon->lcd_rst);
874 if (ret) {
875 dev_err(dev, "Couldn't deassert our reset line\n");
876 return ret;
877 }
878
879 if (tcon->quirks->supports_lvds) {
880 /*
881 * This can only be made optional since we've had DT
882 * nodes without the LVDS reset properties.
883 *
884 * If the property is missing, just disable LVDS, and
885 * print a warning.
886 */
887 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
888 if (IS_ERR(tcon->lvds_rst)) {
889 dev_err(dev, "Couldn't get our reset line\n");
890 return PTR_ERR(tcon->lvds_rst);
891 } else if (tcon->lvds_rst) {
892 has_lvds_rst = true;
893 reset_control_reset(tcon->lvds_rst);
894 } else {
895 has_lvds_rst = false;
896 }
897
898 /*
899 * This can only be made optional since we've had DT
900 * nodes without the LVDS reset properties.
901 *
902 * If the property is missing, just disable LVDS, and
903 * print a warning.
904 */
905 if (tcon->quirks->has_lvds_alt) {
906 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
907 if (IS_ERR(tcon->lvds_pll)) {
908 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
909 has_lvds_alt = false;
910 } else {
911 dev_err(dev, "Couldn't get the LVDS PLL\n");
912 return PTR_ERR(tcon->lvds_pll);
913 }
914 } else {
915 has_lvds_alt = true;
916 }
917 }
918
919 if (!has_lvds_rst ||
920 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
921 dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n");
922 dev_warn(dev, "LVDS output disabled\n");
923 can_lvds = false;
924 } else {
925 can_lvds = true;
926 }
927 } else {
928 can_lvds = false;
929 }
930
931 ret = sun4i_tcon_init_clocks(dev, tcon);
932 if (ret) {
933 dev_err(dev, "Couldn't init our TCON clocks\n");
934 goto err_assert_reset;
935 }
936
937 ret = sun4i_tcon_init_regmap(dev, tcon);
938 if (ret) {
939 dev_err(dev, "Couldn't init our TCON regmap\n");
940 goto err_free_clocks;
941 }
942
943 ret = sun4i_dclk_create(dev, tcon);
944 if (ret) {
945 dev_err(dev, "Couldn't create our TCON dot clock\n");
946 goto err_free_clocks;
947 }
948
949 ret = sun4i_tcon_init_irq(dev, tcon);
950 if (ret) {
951 dev_err(dev, "Couldn't init our TCON interrupts\n");
952 goto err_free_dotclock;
953 }
954
955 tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
956 if (IS_ERR(tcon->crtc)) {
957 dev_err(dev, "Couldn't create our CRTC\n");
958 ret = PTR_ERR(tcon->crtc);
959 goto err_free_dotclock;
960 }
961
962 /*
963 * If we have an LVDS panel connected to the TCON, we should
964 * just probe the LVDS connector. Otherwise, just probe RGB as
965 * we used to.
966 */
967 remote = of_graph_get_remote_node(dev->of_node, 1, 0);
968 if (of_device_is_compatible(remote, "panel-lvds"))
969 if (can_lvds)
970 ret = sun4i_lvds_init(drm, tcon);
971 else
972 ret = -EINVAL;
973 else
974 ret = sun4i_rgb_init(drm, tcon);
975 of_node_put(remote);
976
977 if (ret < 0)
978 goto err_free_dotclock;
979
980 if (tcon->quirks->needs_de_be_mux) {
981 /*
982 * We assume there is no dynamic muxing of backends
983 * and TCONs, so we select the backend with same ID.
984 *
985 * While dynamic selection might be interesting, since
986 * the CRTC is tied to the TCON, while the layers are
987 * tied to the backends, this means, we will need to
988 * switch between groups of layers. There might not be
989 * a way to represent this constraint in DRM.
990 */
991 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
992 SUN4I_TCON0_CTL_SRC_SEL_MASK,
993 tcon->id);
994 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
995 SUN4I_TCON1_CTL_SRC_SEL_MASK,
996 tcon->id);
997 }
998
999 list_add_tail(&tcon->list, &drv->tcon_list);
1000
1001 return 0;
1002
1003 err_free_dotclock:
1004 sun4i_dclk_free(tcon);
1005 err_free_clocks:
1006 sun4i_tcon_free_clocks(tcon);
1007 err_assert_reset:
1008 reset_control_assert(tcon->lcd_rst);
1009 return ret;
1010 }
1011
1012 static void sun4i_tcon_unbind(struct device *dev, struct device *master,
1013 void *data)
1014 {
1015 struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1016
1017 list_del(&tcon->list);
1018 sun4i_dclk_free(tcon);
1019 sun4i_tcon_free_clocks(tcon);
1020 }
1021
1022 static const struct component_ops sun4i_tcon_ops = {
1023 .bind = sun4i_tcon_bind,
1024 .unbind = sun4i_tcon_unbind,
1025 };
1026
1027 static int sun4i_tcon_probe(struct platform_device *pdev)
1028 {
1029 struct device_node *node = pdev->dev.of_node;
1030 struct drm_bridge *bridge;
1031 struct drm_panel *panel;
1032 int ret;
1033
1034 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
1035 if (ret == -EPROBE_DEFER)
1036 return ret;
1037
1038 return component_add(&pdev->dev, &sun4i_tcon_ops);
1039 }
1040
1041 static int sun4i_tcon_remove(struct platform_device *pdev)
1042 {
1043 component_del(&pdev->dev, &sun4i_tcon_ops);
1044
1045 return 0;
1046 }
1047
1048 /* platform specific TCON muxing callbacks */
1049 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1050 const struct drm_encoder *encoder)
1051 {
1052 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1053 u32 shift;
1054
1055 if (!tcon0)
1056 return -EINVAL;
1057
1058 switch (encoder->encoder_type) {
1059 case DRM_MODE_ENCODER_TMDS:
1060 /* HDMI */
1061 shift = 8;
1062 break;
1063 default:
1064 return -EINVAL;
1065 }
1066
1067 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1068 0x3 << shift, tcon->id << shift);
1069
1070 return 0;
1071 }
1072
1073 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1074 const struct drm_encoder *encoder)
1075 {
1076 u32 val;
1077
1078 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1079 val = 1;
1080 else
1081 val = 0;
1082
1083 /*
1084 * FIXME: Undocumented bits
1085 */
1086 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1087 }
1088
1089 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1090 const struct drm_encoder *encoder)
1091 {
1092 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1093 u32 shift;
1094
1095 if (!tcon0)
1096 return -EINVAL;
1097
1098 switch (encoder->encoder_type) {
1099 case DRM_MODE_ENCODER_TMDS:
1100 /* HDMI */
1101 shift = 8;
1102 break;
1103 default:
1104 /* TODO A31 has MIPI DSI but A31s does not */
1105 return -EINVAL;
1106 }
1107
1108 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1109 0x3 << shift, tcon->id << shift);
1110
1111 return 0;
1112 }
1113
1114 static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
1115 .has_channel_1 = true,
1116 .set_mux = sun4i_a10_tcon_set_mux,
1117 };
1118
1119 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
1120 .has_channel_1 = true,
1121 .set_mux = sun5i_a13_tcon_set_mux,
1122 };
1123
1124 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
1125 .has_channel_1 = true,
1126 .has_lvds_alt = true,
1127 .needs_de_be_mux = true,
1128 .set_mux = sun6i_tcon_set_mux,
1129 };
1130
1131 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
1132 .has_channel_1 = true,
1133 .needs_de_be_mux = true,
1134 };
1135
1136 static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
1137 .has_channel_1 = true,
1138 /* Same display pipeline structure as A10 */
1139 .set_mux = sun4i_a10_tcon_set_mux,
1140 };
1141
1142 static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
1143 .has_lvds_alt = true,
1144 };
1145
1146 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
1147 .supports_lvds = true,
1148 };
1149
1150 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
1151 /* nothing is supported */
1152 };
1153
1154 /* sun4i_drv uses this list to check if a device node is a TCON */
1155 const struct of_device_id sun4i_tcon_of_table[] = {
1156 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1157 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1158 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1159 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1160 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1161 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1162 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1163 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1164 { }
1165 };
1166 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
1167 EXPORT_SYMBOL(sun4i_tcon_of_table);
1168
1169 static struct platform_driver sun4i_tcon_platform_driver = {
1170 .probe = sun4i_tcon_probe,
1171 .remove = sun4i_tcon_remove,
1172 .driver = {
1173 .name = "sun4i-tcon",
1174 .of_match_table = sun4i_tcon_of_table,
1175 },
1176 };
1177 module_platform_driver(sun4i_tcon_platform_driver);
1178
1179 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1180 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
1181 MODULE_LICENSE("GPL");
Linux with added FPC-III support