drivers/usb/dwc2/core.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * core.c - DesignWare HS OTG Controller common routines
   4  *
   5  * Copyright (C) 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * The Core code provides basic services for accessing and managing the
  40  * DWC_otg hardware. These services are used by both the Host Controller
  41  * Driver and the Peripheral Controller Driver.
  42  */
  43 #include <linux/kernel.h>
  44 #include <linux/module.h>
  45 #include <linux/moduleparam.h>
  46 #include <linux/spinlock.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/dma-mapping.h>
  49 #include <linux/delay.h>
  50 #include <linux/io.h>
  51 #include <linux/slab.h>
  52 #include <linux/usb.h>
  53
  54 #include <linux/usb/hcd.h>
  55 #include <linux/usb/ch11.h>
  56
  57 #include "core.h"
  58 #include "hcd.h"
  59
  60 /**
  61  * dwc2_backup_global_registers() - Backup global controller registers.
  62  * When suspending usb bus, registers needs to be backuped
  63  * if controller power is disabled once suspended.
  64  *
  65  * @hsotg: Programming view of the DWC_otg controller
  66  */
  67 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
  68 {
  69         struct dwc2_gregs_backup *gr;
  70         int i;
  71
  72         /* Backup global regs */
  73         gr = &hsotg->gr_backup;
  74
  75         gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  76         gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  77         gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
  78         gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
  79         gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
  80         gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
  81         gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
  82         gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
  83         for (i = 0; i < MAX_EPS_CHANNELS; i++)
  84                 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
  85
  86         gr->valid = true;
  87         return 0;
  88 }
  89
  90 /**
  91  * dwc2_restore_global_registers() - Restore controller global registers.
  92  * When resuming usb bus, device registers needs to be restored
  93  * if controller power were disabled.
  94  *
  95  * @hsotg: Programming view of the DWC_otg controller
  96  */
  97 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
  98 {
  99         struct dwc2_gregs_backup *gr;
 100         int i;
 101
 102         dev_dbg(hsotg->dev, "%s\n", __func__);
 103
 104         /* Restore global regs */
 105         gr = &hsotg->gr_backup;
 106         if (!gr->valid) {
 107                 dev_err(hsotg->dev, "%s: no global registers to restore\n",
 108                         __func__);
 109                 return -EINVAL;
 110         }
 111         gr->valid = false;
 112
 113         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 114         dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
 115         dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
 116         dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
 117         dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
 118         dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
 119         dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
 120         dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
 121         dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
 122         for (i = 0; i < MAX_EPS_CHANNELS; i++)
 123                 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
 124
 125         return 0;
 126 }
 127
 128 /**
 129  * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
 130  *
 131  * @hsotg: Programming view of the DWC_otg controller
 132  * @restore: Controller registers need to be restored
 133  */
 134 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
 135 {
 136         u32 pcgcctl;
 137         int ret = 0;
 138
 139         if (!hsotg->params.hibernation)
 140                 return -ENOTSUPP;
 141
 142         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 143         pcgcctl &= ~PCGCTL_STOPPCLK;
 144         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 145
 146         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 147         pcgcctl &= ~PCGCTL_PWRCLMP;
 148         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 149
 150         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 151         pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
 152         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 153
 154         udelay(100);
 155         if (restore) {
 156                 ret = dwc2_restore_global_registers(hsotg);
 157                 if (ret) {
 158                         dev_err(hsotg->dev, "%s: failed to restore registers\n",
 159                                 __func__);
 160                         return ret;
 161                 }
 162                 if (dwc2_is_host_mode(hsotg)) {
 163                         ret = dwc2_restore_host_registers(hsotg);
 164                         if (ret) {
 165                                 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
 166                                         __func__);
 167                                 return ret;
 168                         }
 169                 } else {
 170                         ret = dwc2_restore_device_registers(hsotg);
 171                         if (ret) {
 172                                 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
 173                                         __func__);
 174                                 return ret;
 175                         }
 176                 }
 177         }
 178
 179         return ret;
 180 }
 181
 182 /**
 183  * dwc2_enter_hibernation() - Put controller in Partial Power Down.
 184  *
 185  * @hsotg: Programming view of the DWC_otg controller
 186  */
 187 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
 188 {
 189         u32 pcgcctl;
 190         int ret = 0;
 191
 192         if (!hsotg->params.hibernation)
 193                 return -ENOTSUPP;
 194
 195         /* Backup all registers */
 196         ret = dwc2_backup_global_registers(hsotg);
 197         if (ret) {
 198                 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
 199                         __func__);
 200                 return ret;
 201         }
 202
 203         if (dwc2_is_host_mode(hsotg)) {
 204                 ret = dwc2_backup_host_registers(hsotg);
 205                 if (ret) {
 206                         dev_err(hsotg->dev, "%s: failed to backup host registers\n",
 207                                 __func__);
 208                         return ret;
 209                 }
 210         } else {
 211                 ret = dwc2_backup_device_registers(hsotg);
 212                 if (ret) {
 213                         dev_err(hsotg->dev, "%s: failed to backup device registers\n",
 214                                 __func__);
 215                         return ret;
 216                 }
 217         }
 218
 219         /*
 220          * Clear any pending interrupts since dwc2 will not be able to
 221          * clear them after entering hibernation.
 222          */
 223         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 224
 225         /* Put the controller in low power state */
 226         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 227
 228         pcgcctl |= PCGCTL_PWRCLMP;
 229         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 230         ndelay(20);
 231
 232         pcgcctl |= PCGCTL_RSTPDWNMODULE;
 233         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 234         ndelay(20);
 235
 236         pcgcctl |= PCGCTL_STOPPCLK;
 237         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 238
 239         return ret;
 240 }
 241
 242 /**
 243  * dwc2_wait_for_mode() - Waits for the controller mode.
 244  * @hsotg:      Programming view of the DWC_otg controller.
 245  * @host_mode:  If true, waits for host mode, otherwise device mode.
 246  */
 247 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
 248                                bool host_mode)
 249 {
 250         ktime_t start;
 251         ktime_t end;
 252         unsigned int timeout = 110;
 253
 254         dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
 255                  host_mode ? "host" : "device");
 256
 257         start = ktime_get();
 258
 259         while (1) {
 260                 s64 ms;
 261
 262                 if (dwc2_is_host_mode(hsotg) == host_mode) {
 263                         dev_vdbg(hsotg->dev, "%s mode set\n",
 264                                  host_mode ? "Host" : "Device");
 265                         break;
 266                 }
 267
 268                 end = ktime_get();
 269                 ms = ktime_to_ms(ktime_sub(end, start));
 270
 271                 if (ms >= (s64)timeout) {
 272                         dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
 273                                  __func__, host_mode ? "host" : "device");
 274                         break;
 275                 }
 276
 277                 usleep_range(1000, 2000);
 278         }
 279 }
 280
 281 /**
 282  * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
 283  * filter is enabled.
 284  */
 285 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
 286 {
 287         u32 gsnpsid;
 288         u32 ghwcfg4;
 289
 290         if (!dwc2_hw_is_otg(hsotg))
 291                 return false;
 292
 293         /* Check if core configuration includes the IDDIG filter. */
 294         ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
 295         if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
 296                 return false;
 297
 298         /*
 299          * Check if the IDDIG debounce filter is bypassed. Available
 300          * in core version >= 3.10a.
 301          */
 302         gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
 303         if (gsnpsid >= DWC2_CORE_REV_3_10a) {
 304                 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 305
 306                 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
 307                         return false;
 308         }
 309
 310         return true;
 311 }
 312
 313 /*
 314  * Do core a soft reset of the core.  Be careful with this because it
 315  * resets all the internal state machines of the core.
 316  */
 317 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
 318 {
 319         u32 greset;
 320         int count = 0;
 321         bool wait_for_host_mode = false;
 322
 323         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 324
 325         /*
 326          * If the current mode is host, either due to the force mode
 327          * bit being set (which persists after core reset) or the
 328          * connector id pin, a core soft reset will temporarily reset
 329          * the mode to device. A delay from the IDDIG debounce filter
 330          * will occur before going back to host mode.
 331          *
 332          * Determine whether we will go back into host mode after a
 333          * reset and account for this delay after the reset.
 334          */
 335         if (dwc2_iddig_filter_enabled(hsotg)) {
 336                 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 337                 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 338
 339                 if (!(gotgctl & GOTGCTL_CONID_B) ||
 340                     (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
 341                         wait_for_host_mode = true;
 342                 }
 343         }
 344
 345         /* Core Soft Reset */
 346         greset = dwc2_readl(hsotg->regs + GRSTCTL);
 347         greset |= GRSTCTL_CSFTRST;
 348         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 349         do {
 350                 udelay(1);
 351                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 352                 if (++count > 50) {
 353                         dev_warn(hsotg->dev,
 354                                  "%s() HANG! Soft Reset GRSTCTL=%0x\n",
 355                                  __func__, greset);
 356                         return -EBUSY;
 357                 }
 358         } while (greset & GRSTCTL_CSFTRST);
 359
 360         /* Wait for AHB master IDLE state */
 361         count = 0;
 362         do {
 363                 udelay(1);
 364                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 365                 if (++count > 50) {
 366                         dev_warn(hsotg->dev,
 367                                  "%s() HANG! AHB Idle GRSTCTL=%0x\n",
 368                                  __func__, greset);
 369                         return -EBUSY;
 370                 }
 371         } while (!(greset & GRSTCTL_AHBIDLE));
 372
 373         if (wait_for_host_mode && !skip_wait)
 374                 dwc2_wait_for_mode(hsotg, true);
 375
 376         return 0;
 377 }
 378
 379 /*
 380  * Force the mode of the controller.
 381  *
 382  * Forcing the mode is needed for two cases:
 383  *
 384  * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
 385  * controller to stay in a particular mode regardless of ID pin
 386  * changes. We do this usually after a core reset.
 387  *
 388  * 2) During probe we want to read reset values of the hw
 389  * configuration registers that are only available in either host or
 390  * device mode. We may need to force the mode if the current mode does
 391  * not allow us to access the register in the mode that we want.
 392  *
 393  * In either case it only makes sense to force the mode if the
 394  * controller hardware is OTG capable.
 395  *
 396  * Checks are done in this function to determine whether doing a force
 397  * would be valid or not.
 398  *
 399  * If a force is done, it requires a IDDIG debounce filter delay if
 400  * the filter is configured and enabled. We poll the current mode of
 401  * the controller to account for this delay.
 402  */
 403 static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
 404 {
 405         u32 gusbcfg;
 406         u32 set;
 407         u32 clear;
 408
 409         dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
 410
 411         /*
 412          * Force mode has no effect if the hardware is not OTG.
 413          */
 414         if (!dwc2_hw_is_otg(hsotg))
 415                 return false;
 416
 417         /*
 418          * If dr_mode is either peripheral or host only, there is no
 419          * need to ever force the mode to the opposite mode.
 420          */
 421         if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
 422                 return false;
 423
 424         if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
 425                 return false;
 426
 427         gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 428
 429         set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
 430         clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
 431
 432         gusbcfg &= ~clear;
 433         gusbcfg |= set;
 434         dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 435
 436         dwc2_wait_for_mode(hsotg, host);
 437         return true;
 438 }
 439
 440 /**
 441  * dwc2_clear_force_mode() - Clears the force mode bits.
 442  *
 443  * After clearing the bits, wait up to 100 ms to account for any
 444  * potential IDDIG filter delay. We can't know if we expect this delay
 445  * or not because the value of the connector ID status is affected by
 446  * the force mode. We only need to call this once during probe if
 447  * dr_mode == OTG.
 448  */
 449 void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
 450 {
 451         u32 gusbcfg;
 452
 453         gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 454         gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
 455         gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
 456         dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 457
 458         if (dwc2_iddig_filter_enabled(hsotg))
 459                 msleep(100);
 460 }
 461
 462 /*
 463  * Sets or clears force mode based on the dr_mode parameter.
 464  */
 465 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
 466 {
 467         bool ret;
 468
 469         switch (hsotg->dr_mode) {
 470         case USB_DR_MODE_HOST:
 471                 ret = dwc2_force_mode(hsotg, true);
 472                 /*
 473                  * NOTE: This is required for some rockchip soc based
 474                  * platforms on their host-only dwc2.
 475                  */
 476                 if (!ret)
 477                         msleep(50);
 478
 479                 break;
 480         case USB_DR_MODE_PERIPHERAL:
 481                 dwc2_force_mode(hsotg, false);
 482                 break;
 483         case USB_DR_MODE_OTG:
 484                 dwc2_clear_force_mode(hsotg);
 485                 break;
 486         default:
 487                 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
 488                          __func__, hsotg->dr_mode);
 489                 break;
 490         }
 491 }
 492
 493 /*
 494  * Do core a soft reset of the core.  Be careful with this because it
 495  * resets all the internal state machines of the core.
 496  *
 497  * Additionally this will apply force mode as per the hsotg->dr_mode
 498  * parameter.
 499  */
 500 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
 501 {
 502         int retval;
 503
 504         retval = dwc2_core_reset(hsotg, false);
 505         if (retval)
 506                 return retval;
 507
 508         dwc2_force_dr_mode(hsotg);
 509         return 0;
 510 }
 511
 512 /**
 513  * dwc2_dump_host_registers() - Prints the host registers
 514  *
 515  * @hsotg: Programming view of DWC_otg controller
 516  *
 517  * NOTE: This function will be removed once the peripheral controller code
 518  * is integrated and the driver is stable
 519  */
 520 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
 521 {
 522 #ifdef DEBUG
 523         u32 __iomem *addr;
 524         int i;
 525
 526         dev_dbg(hsotg->dev, "Host Global Registers\n");
 527         addr = hsotg->regs + HCFG;
 528         dev_dbg(hsotg->dev, "HCFG        @0x%08lX : 0x%08X\n",
 529                 (unsigned long)addr, dwc2_readl(addr));
 530         addr = hsotg->regs + HFIR;
 531         dev_dbg(hsotg->dev, "HFIR        @0x%08lX : 0x%08X\n",
 532                 (unsigned long)addr, dwc2_readl(addr));
 533         addr = hsotg->regs + HFNUM;
 534         dev_dbg(hsotg->dev, "HFNUM       @0x%08lX : 0x%08X\n",
 535                 (unsigned long)addr, dwc2_readl(addr));
 536         addr = hsotg->regs + HPTXSTS;
 537         dev_dbg(hsotg->dev, "HPTXSTS     @0x%08lX : 0x%08X\n",
 538                 (unsigned long)addr, dwc2_readl(addr));
 539         addr = hsotg->regs + HAINT;
 540         dev_dbg(hsotg->dev, "HAINT       @0x%08lX : 0x%08X\n",
 541                 (unsigned long)addr, dwc2_readl(addr));
 542         addr = hsotg->regs + HAINTMSK;
 543         dev_dbg(hsotg->dev, "HAINTMSK    @0x%08lX : 0x%08X\n",
 544                 (unsigned long)addr, dwc2_readl(addr));
 545         if (hsotg->params.dma_desc_enable) {
 546                 addr = hsotg->regs + HFLBADDR;
 547                 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
 548                         (unsigned long)addr, dwc2_readl(addr));
 549         }
 550
 551         addr = hsotg->regs + HPRT0;
 552         dev_dbg(hsotg->dev, "HPRT0       @0x%08lX : 0x%08X\n",
 553                 (unsigned long)addr, dwc2_readl(addr));
 554
 555         for (i = 0; i < hsotg->params.host_channels; i++) {
 556                 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
 557                 addr = hsotg->regs + HCCHAR(i);
 558                 dev_dbg(hsotg->dev, "HCCHAR      @0x%08lX : 0x%08X\n",
 559                         (unsigned long)addr, dwc2_readl(addr));
 560                 addr = hsotg->regs + HCSPLT(i);
 561                 dev_dbg(hsotg->dev, "HCSPLT      @0x%08lX : 0x%08X\n",
 562                         (unsigned long)addr, dwc2_readl(addr));
 563                 addr = hsotg->regs + HCINT(i);
 564                 dev_dbg(hsotg->dev, "HCINT       @0x%08lX : 0x%08X\n",
 565                         (unsigned long)addr, dwc2_readl(addr));
 566                 addr = hsotg->regs + HCINTMSK(i);
 567                 dev_dbg(hsotg->dev, "HCINTMSK    @0x%08lX : 0x%08X\n",
 568                         (unsigned long)addr, dwc2_readl(addr));
 569                 addr = hsotg->regs + HCTSIZ(i);
 570                 dev_dbg(hsotg->dev, "HCTSIZ      @0x%08lX : 0x%08X\n",
 571                         (unsigned long)addr, dwc2_readl(addr));
 572                 addr = hsotg->regs + HCDMA(i);
 573                 dev_dbg(hsotg->dev, "HCDMA       @0x%08lX : 0x%08X\n",
 574                         (unsigned long)addr, dwc2_readl(addr));
 575                 if (hsotg->params.dma_desc_enable) {
 576                         addr = hsotg->regs + HCDMAB(i);
 577                         dev_dbg(hsotg->dev, "HCDMAB      @0x%08lX : 0x%08X\n",
 578                                 (unsigned long)addr, dwc2_readl(addr));
 579                 }
 580         }
 581 #endif
 582 }
 583
 584 /**
 585  * dwc2_dump_global_registers() - Prints the core global registers
 586  *
 587  * @hsotg: Programming view of DWC_otg controller
 588  *
 589  * NOTE: This function will be removed once the peripheral controller code
 590  * is integrated and the driver is stable
 591  */
 592 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
 593 {
 594 #ifdef DEBUG
 595         u32 __iomem *addr;
 596
 597         dev_dbg(hsotg->dev, "Core Global Registers\n");
 598         addr = hsotg->regs + GOTGCTL;
 599         dev_dbg(hsotg->dev, "GOTGCTL     @0x%08lX : 0x%08X\n",
 600                 (unsigned long)addr, dwc2_readl(addr));
 601         addr = hsotg->regs + GOTGINT;
 602         dev_dbg(hsotg->dev, "GOTGINT     @0x%08lX : 0x%08X\n",
 603                 (unsigned long)addr, dwc2_readl(addr));
 604         addr = hsotg->regs + GAHBCFG;
 605         dev_dbg(hsotg->dev, "GAHBCFG     @0x%08lX : 0x%08X\n",
 606                 (unsigned long)addr, dwc2_readl(addr));
 607         addr = hsotg->regs + GUSBCFG;
 608         dev_dbg(hsotg->dev, "GUSBCFG     @0x%08lX : 0x%08X\n",
 609                 (unsigned long)addr, dwc2_readl(addr));
 610         addr = hsotg->regs + GRSTCTL;
 611         dev_dbg(hsotg->dev, "GRSTCTL     @0x%08lX : 0x%08X\n",
 612                 (unsigned long)addr, dwc2_readl(addr));
 613         addr = hsotg->regs + GINTSTS;
 614         dev_dbg(hsotg->dev, "GINTSTS     @0x%08lX : 0x%08X\n",
 615                 (unsigned long)addr, dwc2_readl(addr));
 616         addr = hsotg->regs + GINTMSK;
 617         dev_dbg(hsotg->dev, "GINTMSK     @0x%08lX : 0x%08X\n",
 618                 (unsigned long)addr, dwc2_readl(addr));
 619         addr = hsotg->regs + GRXSTSR;
 620         dev_dbg(hsotg->dev, "GRXSTSR     @0x%08lX : 0x%08X\n",
 621                 (unsigned long)addr, dwc2_readl(addr));
 622         addr = hsotg->regs + GRXFSIZ;
 623         dev_dbg(hsotg->dev, "GRXFSIZ     @0x%08lX : 0x%08X\n",
 624                 (unsigned long)addr, dwc2_readl(addr));
 625         addr = hsotg->regs + GNPTXFSIZ;
 626         dev_dbg(hsotg->dev, "GNPTXFSIZ   @0x%08lX : 0x%08X\n",
 627                 (unsigned long)addr, dwc2_readl(addr));
 628         addr = hsotg->regs + GNPTXSTS;
 629         dev_dbg(hsotg->dev, "GNPTXSTS    @0x%08lX : 0x%08X\n",
 630                 (unsigned long)addr, dwc2_readl(addr));
 631         addr = hsotg->regs + GI2CCTL;
 632         dev_dbg(hsotg->dev, "GI2CCTL     @0x%08lX : 0x%08X\n",
 633                 (unsigned long)addr, dwc2_readl(addr));
 634         addr = hsotg->regs + GPVNDCTL;
 635         dev_dbg(hsotg->dev, "GPVNDCTL    @0x%08lX : 0x%08X\n",
 636                 (unsigned long)addr, dwc2_readl(addr));
 637         addr = hsotg->regs + GGPIO;
 638         dev_dbg(hsotg->dev, "GGPIO       @0x%08lX : 0x%08X\n",
 639                 (unsigned long)addr, dwc2_readl(addr));
 640         addr = hsotg->regs + GUID;
 641         dev_dbg(hsotg->dev, "GUID        @0x%08lX : 0x%08X\n",
 642                 (unsigned long)addr, dwc2_readl(addr));
 643         addr = hsotg->regs + GSNPSID;
 644         dev_dbg(hsotg->dev, "GSNPSID     @0x%08lX : 0x%08X\n",
 645                 (unsigned long)addr, dwc2_readl(addr));
 646         addr = hsotg->regs + GHWCFG1;
 647         dev_dbg(hsotg->dev, "GHWCFG1     @0x%08lX : 0x%08X\n",
 648                 (unsigned long)addr, dwc2_readl(addr));
 649         addr = hsotg->regs + GHWCFG2;
 650         dev_dbg(hsotg->dev, "GHWCFG2     @0x%08lX : 0x%08X\n",
 651                 (unsigned long)addr, dwc2_readl(addr));
 652         addr = hsotg->regs + GHWCFG3;
 653         dev_dbg(hsotg->dev, "GHWCFG3     @0x%08lX : 0x%08X\n",
 654                 (unsigned long)addr, dwc2_readl(addr));
 655         addr = hsotg->regs + GHWCFG4;
 656         dev_dbg(hsotg->dev, "GHWCFG4     @0x%08lX : 0x%08X\n",
 657                 (unsigned long)addr, dwc2_readl(addr));
 658         addr = hsotg->regs + GLPMCFG;
 659         dev_dbg(hsotg->dev, "GLPMCFG     @0x%08lX : 0x%08X\n",
 660                 (unsigned long)addr, dwc2_readl(addr));
 661         addr = hsotg->regs + GPWRDN;
 662         dev_dbg(hsotg->dev, "GPWRDN      @0x%08lX : 0x%08X\n",
 663                 (unsigned long)addr, dwc2_readl(addr));
 664         addr = hsotg->regs + GDFIFOCFG;
 665         dev_dbg(hsotg->dev, "GDFIFOCFG   @0x%08lX : 0x%08X\n",
 666                 (unsigned long)addr, dwc2_readl(addr));
 667         addr = hsotg->regs + HPTXFSIZ;
 668         dev_dbg(hsotg->dev, "HPTXFSIZ    @0x%08lX : 0x%08X\n",
 669                 (unsigned long)addr, dwc2_readl(addr));
 670
 671         addr = hsotg->regs + PCGCTL;
 672         dev_dbg(hsotg->dev, "PCGCTL      @0x%08lX : 0x%08X\n",
 673                 (unsigned long)addr, dwc2_readl(addr));
 674 #endif
 675 }
 676
 677 /**
 678  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
 679  *
 680  * @hsotg: Programming view of DWC_otg controller
 681  * @num:   Tx FIFO to flush
 682  */
 683 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
 684 {
 685         u32 greset;
 686         int count = 0;
 687
 688         dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
 689
 690         greset = GRSTCTL_TXFFLSH;
 691         greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
 692         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 693
 694         do {
 695                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 696                 if (++count > 10000) {
 697                         dev_warn(hsotg->dev,
 698                                  "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
 699                                  __func__, greset,
 700                                  dwc2_readl(hsotg->regs + GNPTXSTS));
 701                         break;
 702                 }
 703                 udelay(1);
 704         } while (greset & GRSTCTL_TXFFLSH);
 705
 706         /* Wait for at least 3 PHY Clocks */
 707         udelay(1);
 708 }
 709
 710 /**
 711  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
 712  *
 713  * @hsotg: Programming view of DWC_otg controller
 714  */
 715 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
 716 {
 717         u32 greset;
 718         int count = 0;
 719
 720         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 721
 722         greset = GRSTCTL_RXFFLSH;
 723         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 724
 725         do {
 726                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 727                 if (++count > 10000) {
 728                         dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
 729                                  __func__, greset);
 730                         break;
 731                 }
 732                 udelay(1);
 733         } while (greset & GRSTCTL_RXFFLSH);
 734
 735         /* Wait for at least 3 PHY Clocks */
 736         udelay(1);
 737 }
 738
 739 /*
 740  * Forces either host or device mode if the controller is not
 741  * currently in that mode.
 742  *
 743  * Returns true if the mode was forced.
 744  */
 745 bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
 746 {
 747         if (host && dwc2_is_host_mode(hsotg))
 748                 return false;
 749         else if (!host && dwc2_is_device_mode(hsotg))
 750                 return false;
 751
 752         return dwc2_force_mode(hsotg, host);
 753 }
 754
 755 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
 756 {
 757         if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
 758                 return false;
 759         else
 760                 return true;
 761 }
 762
 763 /**
 764  * dwc2_enable_global_interrupts() - Enables the controller's Global
 765  * Interrupt in the AHB Config register
 766  *
 767  * @hsotg: Programming view of DWC_otg controller
 768  */
 769 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
 770 {
 771         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 772
 773         ahbcfg |= GAHBCFG_GLBL_INTR_EN;
 774         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 775 }
 776
 777 /**
 778  * dwc2_disable_global_interrupts() - Disables the controller's Global
 779  * Interrupt in the AHB Config register
 780  *
 781  * @hsotg: Programming view of DWC_otg controller
 782  */
 783 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
 784 {
 785         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 786
 787         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
 788         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 789 }
 790
 791 /* Returns the controller's GHWCFG2.OTG_MODE. */
 792 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
 793 {
 794         u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
 795
 796         return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 797                 GHWCFG2_OP_MODE_SHIFT;
 798 }
 799
 800 /* Returns true if the controller is capable of DRD. */
 801 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
 802 {
 803         unsigned int op_mode = dwc2_op_mode(hsotg);
 804
 805         return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
 806                 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
 807                 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
 808 }
 809
 810 /* Returns true if the controller is host-only. */
 811 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
 812 {
 813         unsigned int op_mode = dwc2_op_mode(hsotg);
 814
 815         return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
 816                 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
 817 }
 818
 819 /* Returns true if the controller is device-only. */
 820 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
 821 {
 822         unsigned int op_mode = dwc2_op_mode(hsotg);
 823
 824         return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
 825                 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
 826 }
 827
 828 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
 829 MODULE_AUTHOR("Synopsys, Inc.");
 830 MODULE_LICENSE("Dual BSD/GPL");