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bpf: Prevent memory disambiguation attack
[linux/fpc-iii.git] / drivers / usb / musb / blackfin.c
blob0a98dcd66d19d123d9ca0f9fd8ff130df78704c4
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * MUSB OTG controller driver for Blackfin Processors
4 *
5 * Copyright 2006-2008 Analog Devices Inc.
6 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 */
9
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/list.h>
14 #include <linux/gpio.h>
15 #include <linux/io.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/prefetch.h>
20 #include <linux/usb/usb_phy_generic.h>
21
22 #include <asm/cacheflush.h>
23
24 #include "musb_core.h"
25 #include "musbhsdma.h"
26 #include "blackfin.h"
27
28 struct bfin_glue {
29 struct device *dev;
30 struct platform_device *musb;
31 struct platform_device *phy;
32 };
33 #define glue_to_musb(g) platform_get_drvdata(g->musb)
34
35 static u32 bfin_fifo_offset(u8 epnum)
36 {
37 return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
38 }
39
40 static u8 bfin_readb(const void __iomem *addr, unsigned offset)
41 {
42 return (u8)(bfin_read16(addr + offset));
43 }
44
45 static u16 bfin_readw(const void __iomem *addr, unsigned offset)
46 {
47 return bfin_read16(addr + offset);
48 }
49
50 static u32 bfin_readl(const void __iomem *addr, unsigned offset)
51 {
52 return (u32)(bfin_read16(addr + offset));
53 }
54
55 static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
56 {
57 bfin_write16(addr + offset, (u16)data);
58 }
59
60 static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
61 {
62 bfin_write16(addr + offset, data);
63 }
64
65 static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
66 {
67 bfin_write16(addr + offset, (u16)data);
68 }
69
70 /*
71 * Load an endpoint's FIFO
72 */
73 static void bfin_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
74 {
75 struct musb *musb = hw_ep->musb;
76 void __iomem *fifo = hw_ep->fifo;
77 void __iomem *epio = hw_ep->regs;
78 u8 epnum = hw_ep->epnum;
79
80 prefetch((u8 *)src);
81
82 musb_writew(epio, MUSB_TXCOUNT, len);
83
84 dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
85 hw_ep->epnum, fifo, len, src, epio);
86
87 dump_fifo_data(src, len);
88
89 if (!ANOMALY_05000380 && epnum != 0) {
90 u16 dma_reg;
91
92 flush_dcache_range((unsigned long)src,
93 (unsigned long)(src + len));
94
95 /* Setup DMA address register */
96 dma_reg = (u32)src;
97 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
98 SSYNC();
99
100 dma_reg = (u32)src >> 16;
101 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
102 SSYNC();
103
104 /* Setup DMA count register */
105 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
106 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
107 SSYNC();
108
109 /* Enable the DMA */
110 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
111 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
112 SSYNC();
113
114 /* Wait for complete */
115 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
116 cpu_relax();
117
118 /* acknowledge dma interrupt */
119 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
120 SSYNC();
121
122 /* Reset DMA */
123 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
124 SSYNC();
125 } else {
126 SSYNC();
127
128 if (unlikely((unsigned long)src & 0x01))
129 outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
130 else
131 outsw((unsigned long)fifo, src, (len + 1) >> 1);
132 }
133 }
134 /*
135 * Unload an endpoint's FIFO
136 */
137 static void bfin_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
138 {
139 struct musb *musb = hw_ep->musb;
140 void __iomem *fifo = hw_ep->fifo;
141 u8 epnum = hw_ep->epnum;
142
143 if (ANOMALY_05000467 && epnum != 0) {
144 u16 dma_reg;
145
146 invalidate_dcache_range((unsigned long)dst,
147 (unsigned long)(dst + len));
148
149 /* Setup DMA address register */
150 dma_reg = (u32)dst;
151 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
152 SSYNC();
153
154 dma_reg = (u32)dst >> 16;
155 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
156 SSYNC();
157
158 /* Setup DMA count register */
159 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
160 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
161 SSYNC();
162
163 /* Enable the DMA */
164 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
165 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
166 SSYNC();
167
168 /* Wait for complete */
169 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
170 cpu_relax();
171
172 /* acknowledge dma interrupt */
173 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
174 SSYNC();
175
176 /* Reset DMA */
177 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
178 SSYNC();
179 } else {
180 SSYNC();
181 /* Read the last byte of packet with odd size from address fifo + 4
182 * to trigger 1 byte access to EP0 FIFO.
183 */
184 if (len == 1)
185 *dst = (u8)inw((unsigned long)fifo + 4);
186 else {
187 if (unlikely((unsigned long)dst & 0x01))
188 insw_8((unsigned long)fifo, dst, len >> 1);
189 else
190 insw((unsigned long)fifo, dst, len >> 1);
191
192 if (len & 0x01)
193 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
194 }
195 }
196 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
197 'R', hw_ep->epnum, fifo, len, dst);
198
199 dump_fifo_data(dst, len);
200 }
201
202 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
203 {
204 unsigned long flags;
205 irqreturn_t retval = IRQ_NONE;
206 struct musb *musb = __hci;
207
208 spin_lock_irqsave(&musb->lock, flags);
209
210 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
211 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
212 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
213
214 if (musb->int_usb || musb->int_tx || musb->int_rx) {
215 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
216 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
217 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
218 retval = musb_interrupt(musb);
219 }
220
221 /* Start sampling ID pin, when plug is removed from MUSB */
222 if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
223 || musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
224 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
225 mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
226 musb->a_wait_bcon = TIMER_DELAY;
227 }
228
229 spin_unlock_irqrestore(&musb->lock, flags);
230
231 return retval;
232 }
233
234 static void musb_conn_timer_handler(struct timer_list *t)
235 {
236 struct musb *musb = from_timer(musb, t, dev_timer);
237 unsigned long flags;
238 u16 val;
239 static u8 toggle;
240
241 spin_lock_irqsave(&musb->lock, flags);
242 switch (musb->xceiv->otg->state) {
243 case OTG_STATE_A_IDLE:
244 case OTG_STATE_A_WAIT_BCON:
245 /* Start a new session */
246 val = musb_readw(musb->mregs, MUSB_DEVCTL);
247 val &= ~MUSB_DEVCTL_SESSION;
248 musb_writew(musb->mregs, MUSB_DEVCTL, val);
249 val |= MUSB_DEVCTL_SESSION;
250 musb_writew(musb->mregs, MUSB_DEVCTL, val);
251 /* Check if musb is host or peripheral. */
252 val = musb_readw(musb->mregs, MUSB_DEVCTL);
253
254 if (!(val & MUSB_DEVCTL_BDEVICE)) {
255 gpio_set_value(musb->config->gpio_vrsel, 1);
256 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
257 } else {
258 gpio_set_value(musb->config->gpio_vrsel, 0);
259 /* Ignore VBUSERROR and SUSPEND IRQ */
260 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
261 val &= ~MUSB_INTR_VBUSERROR;
262 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
263
264 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
265 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
266 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
267 }
268 mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
269 break;
270 case OTG_STATE_B_IDLE:
271 /*
272 * Start a new session. It seems that MUSB needs taking
273 * some time to recognize the type of the plug inserted?
274 */
275 val = musb_readw(musb->mregs, MUSB_DEVCTL);
276 val |= MUSB_DEVCTL_SESSION;
277 musb_writew(musb->mregs, MUSB_DEVCTL, val);
278 val = musb_readw(musb->mregs, MUSB_DEVCTL);
279
280 if (!(val & MUSB_DEVCTL_BDEVICE)) {
281 gpio_set_value(musb->config->gpio_vrsel, 1);
282 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
283 } else {
284 gpio_set_value(musb->config->gpio_vrsel, 0);
285
286 /* Ignore VBUSERROR and SUSPEND IRQ */
287 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
288 val &= ~MUSB_INTR_VBUSERROR;
289 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
290
291 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
292 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
293
294 /* Toggle the Soft Conn bit, so that we can response to
295 * the inserting of either A-plug or B-plug.
296 */
297 if (toggle) {
298 val = musb_readb(musb->mregs, MUSB_POWER);
299 val &= ~MUSB_POWER_SOFTCONN;
300 musb_writeb(musb->mregs, MUSB_POWER, val);
301 toggle = 0;
302 } else {
303 val = musb_readb(musb->mregs, MUSB_POWER);
304 val |= MUSB_POWER_SOFTCONN;
305 musb_writeb(musb->mregs, MUSB_POWER, val);
306 toggle = 1;
307 }
308 /* The delay time is set to 1/4 second by default,
309 * shortening it, if accelerating A-plug detection
310 * is needed in OTG mode.
311 */
312 mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY / 4);
313 }
314 break;
315 default:
316 dev_dbg(musb->controller, "%s state not handled\n",
317 usb_otg_state_string(musb->xceiv->otg->state));
318 break;
319 }
320 spin_unlock_irqrestore(&musb->lock, flags);
321
322 dev_dbg(musb->controller, "state is %s\n",
323 usb_otg_state_string(musb->xceiv->otg->state));
324 }
325
326 static void bfin_musb_enable(struct musb *musb)
327 {
328 /* REVISIT is this really correct ? */
329 }
330
331 static void bfin_musb_disable(struct musb *musb)
332 {
333 }
334
335 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
336 {
337 int value = musb->config->gpio_vrsel_active;
338 if (!is_on)
339 value = !value;
340 gpio_set_value(musb->config->gpio_vrsel, value);
341
342 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
343 /* otg %3x conf %08x prcm %08x */ "\n",
344 usb_otg_state_string(musb->xceiv->otg->state),
345 musb_readb(musb->mregs, MUSB_DEVCTL));
346 }
347
348 static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
349 {
350 return 0;
351 }
352
353 static int bfin_musb_vbus_status(struct musb *musb)
354 {
355 return 0;
356 }
357
358 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
359 {
360 return -EIO;
361 }
362
363 static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
364 u16 packet_sz, u8 *mode,
365 dma_addr_t *dma_addr, u32 *len)
366 {
367 struct musb_dma_channel *musb_channel = channel->private_data;
368
369 /*
370 * Anomaly 05000450 might cause data corruption when using DMA
371 * MODE 1 transmits with short packet. So to work around this,
372 * we truncate all MODE 1 transfers down to a multiple of the
373 * max packet size, and then do the last short packet transfer
374 * (if there is any) using MODE 0.
375 */
376 if (ANOMALY_05000450) {
377 if (musb_channel->transmit && *mode == 1)
378 *len = *len - (*len % packet_sz);
379 }
380
381 return 0;
382 }
383
384 static void bfin_musb_reg_init(struct musb *musb)
385 {
386 if (ANOMALY_05000346) {
387 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
388 SSYNC();
389 }
390
391 if (ANOMALY_05000347) {
392 bfin_write_USB_APHY_CNTRL(0x0);
393 SSYNC();
394 }
395
396 /* Configure PLL oscillator register */
397 bfin_write_USB_PLLOSC_CTRL(0x3080 |
398 ((480/musb->config->clkin) << 1));
399 SSYNC();
400
401 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
402 SSYNC();
403
404 bfin_write_USB_EP_NI0_RXMAXP(64);
405 SSYNC();
406
407 bfin_write_USB_EP_NI0_TXMAXP(64);
408 SSYNC();
409
410 /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
411 bfin_write_USB_GLOBINTR(0x7);
412 SSYNC();
413
414 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
415 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
416 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
417 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
418 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
419 SSYNC();
420 }
421
422 static int bfin_musb_init(struct musb *musb)
423 {
424
425 /*
426 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
427 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
428 * be low for DEVICE mode and high for HOST mode. We set it high
429 * here because we are in host mode
430 */
431
432 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
433 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
434 musb->config->gpio_vrsel);
435 return -ENODEV;
436 }
437 gpio_direction_output(musb->config->gpio_vrsel, 0);
438
439 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
440 if (IS_ERR_OR_NULL(musb->xceiv)) {
441 gpio_free(musb->config->gpio_vrsel);
442 return -EPROBE_DEFER;
443 }
444
445 bfin_musb_reg_init(musb);
446
447 timer_setup(&musb->dev_timer, musb_conn_timer_handler, 0);
448
449 musb->xceiv->set_power = bfin_musb_set_power;
450
451 musb->isr = blackfin_interrupt;
452 musb->double_buffer_not_ok = true;
453
454 return 0;
455 }
456
457 static int bfin_musb_exit(struct musb *musb)
458 {
459 gpio_free(musb->config->gpio_vrsel);
460 usb_put_phy(musb->xceiv);
461
462 return 0;
463 }
464
465 static const struct musb_platform_ops bfin_ops = {
466 .quirks = MUSB_DMA_INVENTRA,
467 .init = bfin_musb_init,
468 .exit = bfin_musb_exit,
469
470 .fifo_offset = bfin_fifo_offset,
471 .readb = bfin_readb,
472 .writeb = bfin_writeb,
473 .readw = bfin_readw,
474 .writew = bfin_writew,
475 .readl = bfin_readl,
476 .writel = bfin_writel,
477 .fifo_mode = 2,
478 .read_fifo = bfin_read_fifo,
479 .write_fifo = bfin_write_fifo,
480 #ifdef CONFIG_USB_INVENTRA_DMA
481 .dma_init = musbhs_dma_controller_create,
482 .dma_exit = musbhs_dma_controller_destroy,
483 #endif
484 .enable = bfin_musb_enable,
485 .disable = bfin_musb_disable,
486
487 .set_mode = bfin_musb_set_mode,
488
489 .vbus_status = bfin_musb_vbus_status,
490 .set_vbus = bfin_musb_set_vbus,
491
492 .adjust_channel_params = bfin_musb_adjust_channel_params,
493 };
494
495 static u64 bfin_dmamask = DMA_BIT_MASK(32);
496
497 static int bfin_probe(struct platform_device *pdev)
498 {
499 struct resource musb_resources[2];
500 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
501 struct platform_device *musb;
502 struct bfin_glue *glue;
503
504 int ret = -ENOMEM;
505
506 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
507 if (!glue)
508 goto err0;
509
510 musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
511 if (!musb)
512 goto err0;
513
514 musb->dev.parent = &pdev->dev;
515 musb->dev.dma_mask = &bfin_dmamask;
516 musb->dev.coherent_dma_mask = bfin_dmamask;
517
518 glue->dev = &pdev->dev;
519 glue->musb = musb;
520
521 pdata->platform_ops = &bfin_ops;
522
523 glue->phy = usb_phy_generic_register();
524 if (IS_ERR(glue->phy))
525 goto err1;
526 platform_set_drvdata(pdev, glue);
527
528 memset(musb_resources, 0x00, sizeof(*musb_resources) *
529 ARRAY_SIZE(musb_resources));
530
531 musb_resources[0].name = pdev->resource[0].name;
532 musb_resources[0].start = pdev->resource[0].start;
533 musb_resources[0].end = pdev->resource[0].end;
534 musb_resources[0].flags = pdev->resource[0].flags;
535
536 musb_resources[1].name = pdev->resource[1].name;
537 musb_resources[1].start = pdev->resource[1].start;
538 musb_resources[1].end = pdev->resource[1].end;
539 musb_resources[1].flags = pdev->resource[1].flags;
540
541 ret = platform_device_add_resources(musb, musb_resources,
542 ARRAY_SIZE(musb_resources));
543 if (ret) {
544 dev_err(&pdev->dev, "failed to add resources\n");
545 goto err2;
546 }
547
548 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
549 if (ret) {
550 dev_err(&pdev->dev, "failed to add platform_data\n");
551 goto err2;
552 }
553
554 ret = platform_device_add(musb);
555 if (ret) {
556 dev_err(&pdev->dev, "failed to register musb device\n");
557 goto err2;
558 }
559
560 return 0;
561
562 err2:
563 usb_phy_generic_unregister(glue->phy);
564
565 err1:
566 platform_device_put(musb);
567
568 err0:
569 return ret;
570 }
571
572 static int bfin_remove(struct platform_device *pdev)
573 {
574 struct bfin_glue *glue = platform_get_drvdata(pdev);
575
576 platform_device_unregister(glue->musb);
577 usb_phy_generic_unregister(glue->phy);
578
579 return 0;
580 }
581
582 static int __maybe_unused bfin_suspend(struct device *dev)
583 {
584 struct bfin_glue *glue = dev_get_drvdata(dev);
585 struct musb *musb = glue_to_musb(glue);
586
587 if (is_host_active(musb))
588 /*
589 * During hibernate gpio_vrsel will change from high to low
590 * low which will generate wakeup event resume the system
591 * immediately. Set it to 0 before hibernate to avoid this
592 * wakeup event.
593 */
594 gpio_set_value(musb->config->gpio_vrsel, 0);
595
596 return 0;
597 }
598
599 static int __maybe_unused bfin_resume(struct device *dev)
600 {
601 struct bfin_glue *glue = dev_get_drvdata(dev);
602 struct musb *musb = glue_to_musb(glue);
603
604 bfin_musb_reg_init(musb);
605
606 return 0;
607 }
608
609 static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
610
611 static struct platform_driver bfin_driver = {
612 .probe = bfin_probe,
613 .remove = bfin_remove,
614 .driver = {
615 .name = "musb-blackfin",
616 .pm = &bfin_pm_ops,
617 },
618 };
619
620 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
621 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
622 MODULE_LICENSE("GPL v2");
623 module_platform_driver(bfin_driver);
Linux with added FPC-III support