drivers/usb/musb/musb_regs.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MUSB OTG driver register defines
   4  *
   5  * Copyright 2005 Mentor Graphics Corporation
   6  * Copyright (C) 2005-2006 by Texas Instruments
   7  * Copyright (C) 2006-2007 Nokia Corporation
   8  */
   9
  10 #ifndef __MUSB_REGS_H__
  11 #define __MUSB_REGS_H__
  12
  13 #define MUSB_EP0_FIFOSIZE       64      /* This is non-configurable */
  14
  15 /*
  16  * MUSB Register bits
  17  */
  18
  19 /* POWER */
  20 #define MUSB_POWER_ISOUPDATE    0x80
  21 #define MUSB_POWER_SOFTCONN     0x40
  22 #define MUSB_POWER_HSENAB       0x20
  23 #define MUSB_POWER_HSMODE       0x10
  24 #define MUSB_POWER_RESET        0x08
  25 #define MUSB_POWER_RESUME       0x04
  26 #define MUSB_POWER_SUSPENDM     0x02
  27 #define MUSB_POWER_ENSUSPEND    0x01
  28
  29 /* INTRUSB */
  30 #define MUSB_INTR_SUSPEND       0x01
  31 #define MUSB_INTR_RESUME        0x02
  32 #define MUSB_INTR_RESET         0x04
  33 #define MUSB_INTR_BABBLE        0x04
  34 #define MUSB_INTR_SOF           0x08
  35 #define MUSB_INTR_CONNECT       0x10
  36 #define MUSB_INTR_DISCONNECT    0x20
  37 #define MUSB_INTR_SESSREQ       0x40
  38 #define MUSB_INTR_VBUSERROR     0x80    /* For SESSION end */
  39
  40 /* DEVCTL */
  41 #define MUSB_DEVCTL_BDEVICE     0x80
  42 #define MUSB_DEVCTL_FSDEV       0x40
  43 #define MUSB_DEVCTL_LSDEV       0x20
  44 #define MUSB_DEVCTL_VBUS        0x18
  45 #define MUSB_DEVCTL_VBUS_SHIFT  3
  46 #define MUSB_DEVCTL_HM          0x04
  47 #define MUSB_DEVCTL_HR          0x02
  48 #define MUSB_DEVCTL_SESSION     0x01
  49
  50 /* BABBLE_CTL */
  51 #define MUSB_BABBLE_FORCE_TXIDLE        0x80
  52 #define MUSB_BABBLE_SW_SESSION_CTRL     0x40
  53 #define MUSB_BABBLE_STUCK_J             0x20
  54 #define MUSB_BABBLE_RCV_DISABLE         0x04
  55
  56 /* MUSB ULPI VBUSCONTROL */
  57 #define MUSB_ULPI_USE_EXTVBUS   0x01
  58 #define MUSB_ULPI_USE_EXTVBUSIND 0x02
  59 /* ULPI_REG_CONTROL */
  60 #define MUSB_ULPI_REG_REQ       (1 << 0)
  61 #define MUSB_ULPI_REG_CMPLT     (1 << 1)
  62 #define MUSB_ULPI_RDN_WR        (1 << 2)
  63
  64 /* TESTMODE */
  65 #define MUSB_TEST_FORCE_HOST    0x80
  66 #define MUSB_TEST_FIFO_ACCESS   0x40
  67 #define MUSB_TEST_FORCE_FS      0x20
  68 #define MUSB_TEST_FORCE_HS      0x10
  69 #define MUSB_TEST_PACKET        0x08
  70 #define MUSB_TEST_K             0x04
  71 #define MUSB_TEST_J             0x02
  72 #define MUSB_TEST_SE0_NAK       0x01
  73
  74 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
  75 #define MUSB_FIFOSZ_DPB 0x10
  76 /* Allocation size (8, 16, 32, ... 4096) */
  77 #define MUSB_FIFOSZ_SIZE        0x0f
  78
  79 /* CSR0 */
  80 #define MUSB_CSR0_FLUSHFIFO     0x0100
  81 #define MUSB_CSR0_TXPKTRDY      0x0002
  82 #define MUSB_CSR0_RXPKTRDY      0x0001
  83
  84 /* CSR0 in Peripheral mode */
  85 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
  86 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
  87 #define MUSB_CSR0_P_SENDSTALL   0x0020
  88 #define MUSB_CSR0_P_SETUPEND    0x0010
  89 #define MUSB_CSR0_P_DATAEND     0x0008
  90 #define MUSB_CSR0_P_SENTSTALL   0x0004
  91
  92 /* CSR0 in Host mode */
  93 #define MUSB_CSR0_H_DIS_PING            0x0800
  94 #define MUSB_CSR0_H_WR_DATATOGGLE       0x0400  /* Set to allow setting: */
  95 #define MUSB_CSR0_H_DATATOGGLE          0x0200  /* Data toggle control */
  96 #define MUSB_CSR0_H_NAKTIMEOUT          0x0080
  97 #define MUSB_CSR0_H_STATUSPKT           0x0040
  98 #define MUSB_CSR0_H_REQPKT              0x0020
  99 #define MUSB_CSR0_H_ERROR               0x0010
 100 #define MUSB_CSR0_H_SETUPPKT            0x0008
 101 #define MUSB_CSR0_H_RXSTALL             0x0004
 102
 103 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
 104 #define MUSB_CSR0_P_WZC_BITS    \
 105         (MUSB_CSR0_P_SENTSTALL)
 106 #define MUSB_CSR0_H_WZC_BITS    \
 107         (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
 108         | MUSB_CSR0_RXPKTRDY)
 109
 110 /* TxType/RxType */
 111 #define MUSB_TYPE_SPEED         0xc0
 112 #define MUSB_TYPE_SPEED_SHIFT   6
 113 #define MUSB_TYPE_PROTO         0x30    /* Implicitly zero for ep0 */
 114 #define MUSB_TYPE_PROTO_SHIFT   4
 115 #define MUSB_TYPE_REMOTE_END    0xf     /* Implicitly zero for ep0 */
 116
 117 /* CONFIGDATA */
 118 #define MUSB_CONFIGDATA_MPRXE           0x80    /* Auto bulk pkt combining */
 119 #define MUSB_CONFIGDATA_MPTXE           0x40    /* Auto bulk pkt splitting */
 120 #define MUSB_CONFIGDATA_BIGENDIAN       0x20
 121 #define MUSB_CONFIGDATA_HBRXE           0x10    /* HB-ISO for RX */
 122 #define MUSB_CONFIGDATA_HBTXE           0x08    /* HB-ISO for TX */
 123 #define MUSB_CONFIGDATA_DYNFIFO         0x04    /* Dynamic FIFO sizing */
 124 #define MUSB_CONFIGDATA_SOFTCONE        0x02    /* SoftConnect */
 125 #define MUSB_CONFIGDATA_UTMIDW          0x01    /* Data width 0/1 => 8/16bits */
 126
 127 /* TXCSR in Peripheral and Host mode */
 128 #define MUSB_TXCSR_AUTOSET              0x8000
 129 #define MUSB_TXCSR_DMAENAB              0x1000
 130 #define MUSB_TXCSR_FRCDATATOG           0x0800
 131 #define MUSB_TXCSR_DMAMODE              0x0400
 132 #define MUSB_TXCSR_CLRDATATOG           0x0040
 133 #define MUSB_TXCSR_FLUSHFIFO            0x0008
 134 #define MUSB_TXCSR_FIFONOTEMPTY         0x0002
 135 #define MUSB_TXCSR_TXPKTRDY             0x0001
 136
 137 /* TXCSR in Peripheral mode */
 138 #define MUSB_TXCSR_P_ISO                0x4000
 139 #define MUSB_TXCSR_P_INCOMPTX           0x0080
 140 #define MUSB_TXCSR_P_SENTSTALL          0x0020
 141 #define MUSB_TXCSR_P_SENDSTALL          0x0010
 142 #define MUSB_TXCSR_P_UNDERRUN           0x0004
 143
 144 /* TXCSR in Host mode */
 145 #define MUSB_TXCSR_H_WR_DATATOGGLE      0x0200
 146 #define MUSB_TXCSR_H_DATATOGGLE         0x0100
 147 #define MUSB_TXCSR_H_NAKTIMEOUT         0x0080
 148 #define MUSB_TXCSR_H_RXSTALL            0x0020
 149 #define MUSB_TXCSR_H_ERROR              0x0004
 150
 151 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 152 #define MUSB_TXCSR_P_WZC_BITS   \
 153         (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
 154         | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
 155 #define MUSB_TXCSR_H_WZC_BITS   \
 156         (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
 157         | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
 158
 159 /* RXCSR in Peripheral and Host mode */
 160 #define MUSB_RXCSR_AUTOCLEAR            0x8000
 161 #define MUSB_RXCSR_DMAENAB              0x2000
 162 #define MUSB_RXCSR_DISNYET              0x1000
 163 #define MUSB_RXCSR_PID_ERR              0x1000
 164 #define MUSB_RXCSR_DMAMODE              0x0800
 165 #define MUSB_RXCSR_INCOMPRX             0x0100
 166 #define MUSB_RXCSR_CLRDATATOG           0x0080
 167 #define MUSB_RXCSR_FLUSHFIFO            0x0010
 168 #define MUSB_RXCSR_DATAERROR            0x0008
 169 #define MUSB_RXCSR_FIFOFULL             0x0002
 170 #define MUSB_RXCSR_RXPKTRDY             0x0001
 171
 172 /* RXCSR in Peripheral mode */
 173 #define MUSB_RXCSR_P_ISO                0x4000
 174 #define MUSB_RXCSR_P_SENTSTALL          0x0040
 175 #define MUSB_RXCSR_P_SENDSTALL          0x0020
 176 #define MUSB_RXCSR_P_OVERRUN            0x0004
 177
 178 /* RXCSR in Host mode */
 179 #define MUSB_RXCSR_H_AUTOREQ            0x4000
 180 #define MUSB_RXCSR_H_WR_DATATOGGLE      0x0400
 181 #define MUSB_RXCSR_H_DATATOGGLE         0x0200
 182 #define MUSB_RXCSR_H_RXSTALL            0x0040
 183 #define MUSB_RXCSR_H_REQPKT             0x0020
 184 #define MUSB_RXCSR_H_ERROR              0x0004
 185
 186 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 187 #define MUSB_RXCSR_P_WZC_BITS   \
 188         (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
 189         | MUSB_RXCSR_RXPKTRDY)
 190 #define MUSB_RXCSR_H_WZC_BITS   \
 191         (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
 192         | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
 193
 194 /* HUBADDR */
 195 #define MUSB_HUBADDR_MULTI_TT           0x80
 196
 197
 198 #ifndef CONFIG_BLACKFIN
 199
 200 /*
 201  * Common USB registers
 202  */
 203
 204 #define MUSB_FADDR              0x00    /* 8-bit */
 205 #define MUSB_POWER              0x01    /* 8-bit */
 206
 207 #define MUSB_INTRTX             0x02    /* 16-bit */
 208 #define MUSB_INTRRX             0x04
 209 #define MUSB_INTRTXE            0x06
 210 #define MUSB_INTRRXE            0x08
 211 #define MUSB_INTRUSB            0x0A    /* 8 bit */
 212 #define MUSB_INTRUSBE           0x0B    /* 8 bit */
 213 #define MUSB_FRAME              0x0C
 214 #define MUSB_INDEX              0x0E    /* 8 bit */
 215 #define MUSB_TESTMODE           0x0F    /* 8 bit */
 216
 217 /*
 218  * Additional Control Registers
 219  */
 220
 221 #define MUSB_DEVCTL             0x60    /* 8 bit */
 222 #define MUSB_BABBLE_CTL         0x61    /* 8 bit */
 223
 224 /* These are always controlled through the INDEX register */
 225 #define MUSB_TXFIFOSZ           0x62    /* 8-bit (see masks) */
 226 #define MUSB_RXFIFOSZ           0x63    /* 8-bit (see masks) */
 227 #define MUSB_TXFIFOADD          0x64    /* 16-bit offset shifted right 3 */
 228 #define MUSB_RXFIFOADD          0x66    /* 16-bit offset shifted right 3 */
 229
 230 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
 231 #define MUSB_HWVERS             0x6C    /* 8 bit */
 232 #define MUSB_ULPI_BUSCONTROL    0x70    /* 8 bit */
 233 #define MUSB_ULPI_INT_MASK      0x72    /* 8 bit */
 234 #define MUSB_ULPI_INT_SRC       0x73    /* 8 bit */
 235 #define MUSB_ULPI_REG_DATA      0x74    /* 8 bit */
 236 #define MUSB_ULPI_REG_ADDR      0x75    /* 8 bit */
 237 #define MUSB_ULPI_REG_CONTROL   0x76    /* 8 bit */
 238 #define MUSB_ULPI_RAW_DATA      0x77    /* 8 bit */
 239
 240 #define MUSB_EPINFO             0x78    /* 8 bit */
 241 #define MUSB_RAMINFO            0x79    /* 8 bit */
 242 #define MUSB_LINKINFO           0x7a    /* 8 bit */
 243 #define MUSB_VPLEN              0x7b    /* 8 bit */
 244 #define MUSB_HS_EOF1            0x7c    /* 8 bit */
 245 #define MUSB_FS_EOF1            0x7d    /* 8 bit */
 246 #define MUSB_LS_EOF1            0x7e    /* 8 bit */
 247
 248 /* Offsets to endpoint registers */
 249 #define MUSB_TXMAXP             0x00
 250 #define MUSB_TXCSR              0x02
 251 #define MUSB_CSR0               MUSB_TXCSR      /* Re-used for EP0 */
 252 #define MUSB_RXMAXP             0x04
 253 #define MUSB_RXCSR              0x06
 254 #define MUSB_RXCOUNT            0x08
 255 #define MUSB_COUNT0             MUSB_RXCOUNT    /* Re-used for EP0 */
 256 #define MUSB_TXTYPE             0x0A
 257 #define MUSB_TYPE0              MUSB_TXTYPE     /* Re-used for EP0 */
 258 #define MUSB_TXINTERVAL         0x0B
 259 #define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
 260 #define MUSB_RXTYPE             0x0C
 261 #define MUSB_RXINTERVAL         0x0D
 262 #define MUSB_FIFOSIZE           0x0F
 263 #define MUSB_CONFIGDATA         MUSB_FIFOSIZE   /* Re-used for EP0 */
 264
 265 #include "tusb6010.h"           /* Needed "only" for TUSB_EP0_CONF */
 266
 267 #define MUSB_TXCSR_MODE                 0x2000
 268
 269 /* "bus control"/target registers, for host side multipoint (external hubs) */
 270 #define MUSB_TXFUNCADDR         0x00
 271 #define MUSB_TXHUBADDR          0x02
 272 #define MUSB_TXHUBPORT          0x03
 273
 274 #define MUSB_RXFUNCADDR         0x04
 275 #define MUSB_RXHUBADDR          0x06
 276 #define MUSB_RXHUBPORT          0x07
 277
 278 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
 279 {
 280         musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
 281 }
 282
 283 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
 284 {
 285         musb_writew(mbase, MUSB_TXFIFOADD, c_off);
 286 }
 287
 288 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
 289 {
 290         musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
 291 }
 292
 293 static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
 294 {
 295         musb_writew(mbase, MUSB_RXFIFOADD, c_off);
 296 }
 297
 298 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
 299 {
 300         musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
 301 }
 302
 303 static inline u8 musb_read_txfifosz(void __iomem *mbase)
 304 {
 305         return musb_readb(mbase, MUSB_TXFIFOSZ);
 306 }
 307
 308 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
 309 {
 310         return musb_readw(mbase, MUSB_TXFIFOADD);
 311 }
 312
 313 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
 314 {
 315         return musb_readb(mbase, MUSB_RXFIFOSZ);
 316 }
 317
 318 static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
 319 {
 320         return musb_readw(mbase, MUSB_RXFIFOADD);
 321 }
 322
 323 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
 324 {
 325         return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
 326 }
 327
 328 static inline u8 musb_read_configdata(void __iomem *mbase)
 329 {
 330         musb_writeb(mbase, MUSB_INDEX, 0);
 331         return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
 332 }
 333
 334 static inline u16 musb_read_hwvers(void __iomem *mbase)
 335 {
 336         return musb_readw(mbase, MUSB_HWVERS);
 337 }
 338
 339 static inline void musb_write_rxfunaddr(struct musb *musb, u8 epnum,
 340                 u8 qh_addr_reg)
 341 {
 342         musb_writeb(musb->mregs,
 343                     musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR),
 344                     qh_addr_reg);
 345 }
 346
 347 static inline void musb_write_rxhubaddr(struct musb *musb, u8 epnum,
 348                 u8 qh_h_addr_reg)
 349 {
 350         musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBADDR),
 351                         qh_h_addr_reg);
 352 }
 353
 354 static inline void musb_write_rxhubport(struct musb *musb, u8 epnum,
 355                 u8 qh_h_port_reg)
 356 {
 357         musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBPORT),
 358                         qh_h_port_reg);
 359 }
 360
 361 static inline void musb_write_txfunaddr(struct musb *musb, u8 epnum,
 362                 u8 qh_addr_reg)
 363 {
 364         musb_writeb(musb->mregs,
 365                     musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR),
 366                     qh_addr_reg);
 367 }
 368
 369 static inline void musb_write_txhubaddr(struct musb *musb, u8 epnum,
 370                 u8 qh_addr_reg)
 371 {
 372         musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBADDR),
 373                         qh_addr_reg);
 374 }
 375
 376 static inline void musb_write_txhubport(struct musb *musb, u8 epnum,
 377                 u8 qh_h_port_reg)
 378 {
 379         musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBPORT),
 380                         qh_h_port_reg);
 381 }
 382
 383 static inline u8 musb_read_rxfunaddr(struct musb *musb, u8 epnum)
 384 {
 385         return musb_readb(musb->mregs,
 386                           musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR));
 387 }
 388
 389 static inline u8 musb_read_rxhubaddr(struct musb *musb, u8 epnum)
 390 {
 391         return musb_readb(musb->mregs,
 392                           musb->io.busctl_offset(epnum, MUSB_RXHUBADDR));
 393 }
 394
 395 static inline u8 musb_read_rxhubport(struct musb *musb, u8 epnum)
 396 {
 397         return musb_readb(musb->mregs,
 398                           musb->io.busctl_offset(epnum, MUSB_RXHUBPORT));
 399 }
 400
 401 static inline u8 musb_read_txfunaddr(struct musb *musb, u8 epnum)
 402 {
 403         return musb_readb(musb->mregs,
 404                           musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR));
 405 }
 406
 407 static inline u8 musb_read_txhubaddr(struct musb *musb, u8 epnum)
 408 {
 409         return musb_readb(musb->mregs,
 410                           musb->io.busctl_offset(epnum, MUSB_TXHUBADDR));
 411 }
 412
 413 static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum)
 414 {
 415         return musb_readb(musb->mregs,
 416                           musb->io.busctl_offset(epnum, MUSB_TXHUBPORT));
 417 }
 418
 419 #else /* CONFIG_BLACKFIN */
 420
 421 #define USB_BASE                USB_FADDR
 422 #define USB_OFFSET(reg)         (reg - USB_BASE)
 423
 424 /*
 425  * Common USB registers
 426  */
 427 #define MUSB_FADDR              USB_OFFSET(USB_FADDR)   /* 8-bit */
 428 #define MUSB_POWER              USB_OFFSET(USB_POWER)   /* 8-bit */
 429 #define MUSB_INTRTX             USB_OFFSET(USB_INTRTX)  /* 16-bit */
 430 #define MUSB_INTRRX             USB_OFFSET(USB_INTRRX)
 431 #define MUSB_INTRTXE            USB_OFFSET(USB_INTRTXE)
 432 #define MUSB_INTRRXE            USB_OFFSET(USB_INTRRXE)
 433 #define MUSB_INTRUSB            USB_OFFSET(USB_INTRUSB) /* 8 bit */
 434 #define MUSB_INTRUSBE           USB_OFFSET(USB_INTRUSBE)/* 8 bit */
 435 #define MUSB_FRAME              USB_OFFSET(USB_FRAME)
 436 #define MUSB_INDEX              USB_OFFSET(USB_INDEX)   /* 8 bit */
 437 #define MUSB_TESTMODE           USB_OFFSET(USB_TESTMODE)/* 8 bit */
 438
 439 /*
 440  * Additional Control Registers
 441  */
 442
 443 #define MUSB_DEVCTL             USB_OFFSET(USB_OTG_DEV_CTL)     /* 8 bit */
 444
 445 #define MUSB_LINKINFO           USB_OFFSET(USB_LINKINFO)/* 8 bit */
 446 #define MUSB_VPLEN              USB_OFFSET(USB_VPLEN)   /* 8 bit */
 447 #define MUSB_HS_EOF1            USB_OFFSET(USB_HS_EOF1) /* 8 bit */
 448 #define MUSB_FS_EOF1            USB_OFFSET(USB_FS_EOF1) /* 8 bit */
 449 #define MUSB_LS_EOF1            USB_OFFSET(USB_LS_EOF1) /* 8 bit */
 450
 451 /* Offsets to endpoint registers */
 452 #define MUSB_TXMAXP             0x00
 453 #define MUSB_TXCSR              0x04
 454 #define MUSB_CSR0               MUSB_TXCSR      /* Re-used for EP0 */
 455 #define MUSB_RXMAXP             0x08
 456 #define MUSB_RXCSR              0x0C
 457 #define MUSB_RXCOUNT            0x10
 458 #define MUSB_COUNT0             MUSB_RXCOUNT    /* Re-used for EP0 */
 459 #define MUSB_TXTYPE             0x14
 460 #define MUSB_TYPE0              MUSB_TXTYPE     /* Re-used for EP0 */
 461 #define MUSB_TXINTERVAL         0x18
 462 #define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
 463 #define MUSB_RXTYPE             0x1C
 464 #define MUSB_RXINTERVAL         0x20
 465 #define MUSB_TXCOUNT            0x28
 466
 467 /* Offsets to endpoint registers in indexed model (using INDEX register) */
 468 #define MUSB_INDEXED_OFFSET(_epnum, _offset)    \
 469         (0x40 + (_offset))
 470
 471 /* Offsets to endpoint registers in flat models */
 472 #define MUSB_FLAT_OFFSET(_epnum, _offset)       \
 473         (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
 474
 475 /* Not implemented - HW has separate Tx/Rx FIFO */
 476 #define MUSB_TXCSR_MODE                 0x0000
 477
 478 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
 479 {
 480 }
 481
 482 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
 483 {
 484 }
 485
 486 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
 487 {
 488 }
 489
 490 static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
 491 {
 492 }
 493
 494 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
 495 {
 496 }
 497
 498 static inline u8 musb_read_txfifosz(void __iomem *mbase)
 499 {
 500         return 0;
 501 }
 502
 503 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
 504 {
 505         return 0;
 506 }
 507
 508 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
 509 {
 510         return 0;
 511 }
 512
 513 static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
 514 {
 515         return 0;
 516 }
 517
 518 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
 519 {
 520         return 0;
 521 }
 522
 523 static inline u8 musb_read_configdata(void __iomem *mbase)
 524 {
 525         return 0;
 526 }
 527
 528 static inline u16 musb_read_hwvers(void __iomem *mbase)
 529 {
 530         /*
 531          * This register is invisible on Blackfin, actually the MUSB
 532          * RTL version of Blackfin is 1.9, so just hardcode its value.
 533          */
 534         return MUSB_HWVERS_1900;
 535 }
 536
 537 static inline void musb_write_rxfunaddr(void __iomem *mbase, u8 epnum,
 538                 u8 qh_addr_req)
 539 {
 540 }
 541
 542 static inline void musb_write_rxhubaddr(void __iomem *mbase, u8 epnum,
 543                 u8 qh_h_addr_reg)
 544 {
 545 }
 546
 547 static inline void musb_write_rxhubport(void __iomem *mbase, u8 epnum,
 548                 u8 qh_h_port_reg)
 549 {
 550 }
 551
 552 static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
 553                 u8 qh_addr_reg)
 554 {
 555 }
 556
 557 static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
 558                 u8 qh_addr_reg)
 559 {
 560 }
 561
 562 static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
 563                 u8 qh_h_port_reg)
 564 {
 565 }
 566
 567 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
 568 {
 569         return 0;
 570 }
 571
 572 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
 573 {
 574         return 0;
 575 }
 576
 577 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
 578 {
 579         return 0;
 580 }
 581
 582 static inline u8  musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
 583 {
 584         return 0;
 585 }
 586
 587 static inline u8  musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
 588 {
 589         return 0;
 590 }
 591
 592 static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
 593 {
 594         return 0;
 595 }
 596
 597 #endif /* CONFIG_BLACKFIN */
 598
 599 #endif  /* __MUSB_REGS_H__ */