arch/mips/include/asm/mach-pnx833x/irq.h

   1 /*
   2  *  irq.h: IRQ mappings for PNX833X.
   3  *
   4  *  Copyright 2008 NXP Semiconductors
   5  *        Chris Steel <chris.steel@nxp.com>
   6  *    Daniel Laird <daniel.j.laird@nxp.com>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
  24 #define __ASM_MIPS_MACH_PNX833X_IRQ_H
  25 /*
  26  * The "IRQ numbers" are completely virtual.
  27  *
  28  * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
  29  * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
  30  * numbers 49..64 for (virtual) GPIO interrupts.
  31  *
  32  * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
  33  * connected to PIC, which uses core hardware interrupt 2, and also
  34  * a timer interrupt through hardware interrupt 5.
  35  * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
  36  * numbers 65..80 for (virtual) GPIO interrupts.
  37  *
  38  */
  39 #if defined(CONFIG_SOC_PNX8335)
  40         #define PNX833X_PIC_NUM_IRQ                     58
  41 #else
  42         #define PNX833X_PIC_NUM_IRQ                     37
  43 #endif
  44
  45 #define MIPS_CPU_NUM_IRQ                                8
  46 #define PNX833X_GPIO_NUM_IRQ                    16
  47
  48 #define MIPS_CPU_IRQ_BASE                               0
  49 #define PNX833X_PIC_IRQ_BASE                    (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
  50 #define PNX833X_GPIO_IRQ_BASE                   (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
  51 #define NR_IRQS                                                 (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
  52
  53 #endif