?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
xfs: calculate XFS_TRANS_QM_QUOTAOFF_END space log reservation at mount time
[linux/fpc-iii.git] / arch / mips / include / asm / mipsmtregs.h
blob5b3cb8553e9abafa3d3bb18b4628d1064b1bff12
1 /*
2 * MT regs definitions, follows on from mipsregs.h
3 * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
4 * Elizabeth Clarke et. al.
5 *
6 */
7 #ifndef _ASM_MIPSMTREGS_H
8 #define _ASM_MIPSMTREGS_H
9
10 #include <asm/mipsregs.h>
11 #include <asm/war.h>
12
13 #ifndef __ASSEMBLY__
14
15 /*
16 * C macros
17 */
18
19 #define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
21
22 #define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
23 #define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
24
25 #define read_c0_vpecontrol() __read_32bit_c0_register($1, 1)
26 #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val)
27
28 #define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
29 #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
30
31 #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
32 #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
33
34 #define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
35 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
36
37 #define read_c0_tcbind() __read_32bit_c0_register($2, 2)
38
39 #define read_c0_tccontext() __read_32bit_c0_register($2, 5)
40 #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val)
41
42 #else /* Assembly */
43 /*
44 * Macros for use in assembly language code
45 */
46
47 #define CP0_MVPCONTROL $0, 1
48 #define CP0_MVPCONF0 $0, 2
49 #define CP0_MVPCONF1 $0, 3
50 #define CP0_VPECONTROL $1, 1
51 #define CP0_VPECONF0 $1, 2
52 #define CP0_VPECONF1 $1, 3
53 #define CP0_YQMASK $1, 4
54 #define CP0_VPESCHEDULE $1, 5
55 #define CP0_VPESCHEFBK $1, 6
56 #define CP0_TCSTATUS $2, 1
57 #define CP0_TCBIND $2, 2
58 #define CP0_TCRESTART $2, 3
59 #define CP0_TCHALT $2, 4
60 #define CP0_TCCONTEXT $2, 5
61 #define CP0_TCSCHEDULE $2, 6
62 #define CP0_TCSCHEFBK $2, 7
63 #define CP0_SRSCONF0 $6, 1
64 #define CP0_SRSCONF1 $6, 2
65 #define CP0_SRSCONF2 $6, 3
66 #define CP0_SRSCONF3 $6, 4
67 #define CP0_SRSCONF4 $6, 5
68
69 #endif
70
71 /* MVPControl fields */
72 #define MVPCONTROL_EVP (_ULCAST_(1))
73
74 #define MVPCONTROL_VPC_SHIFT 1
75 #define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
76
77 #define MVPCONTROL_STLB_SHIFT 2
78 #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
79
80
81 /* MVPConf0 fields */
82 #define MVPCONF0_PTC_SHIFT 0
83 #define MVPCONF0_PTC ( _ULCAST_(0xff))
84 #define MVPCONF0_PVPE_SHIFT 10
85 #define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
86 #define MVPCONF0_TCA_SHIFT 15
87 #define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
88 #define MVPCONF0_PTLBE_SHIFT 16
89 #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
90 #define MVPCONF0_TLBS_SHIFT 29
91 #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
92 #define MVPCONF0_M_SHIFT 31
93 #define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
94
95
96 /* config3 fields */
97 #define CONFIG3_MT_SHIFT 2
98 #define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
99
100
101 /* VPEControl fields (per VPE) */
102 #define VPECONTROL_TARGTC (_ULCAST_(0xff))
103
104 #define VPECONTROL_TE_SHIFT 15
105 #define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
106 #define VPECONTROL_EXCPT_SHIFT 16
107 #define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
108
109 /* Thread Exception Codes for EXCPT field */
110 #define THREX_TU 0
111 #define THREX_TO 1
112 #define THREX_IYQ 2
113 #define THREX_GSX 3
114 #define THREX_YSCH 4
115 #define THREX_GSSCH 5
116
117 #define VPECONTROL_GSI_SHIFT 20
118 #define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
119 #define VPECONTROL_YSI_SHIFT 21
120 #define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
121
122 /* VPEConf0 fields (per VPE) */
123 #define VPECONF0_VPA_SHIFT 0
124 #define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
125 #define VPECONF0_MVP_SHIFT 1
126 #define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
127 #define VPECONF0_XTC_SHIFT 21
128 #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
129
130 /* VPEConf1 fields (per VPE) */
131 #define VPECONF1_NCP1_SHIFT 0
132 #define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
133 #define VPECONF1_NCP2_SHIFT 10
134 #define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
135 #define VPECONF1_NCX_SHIFT 20
136 #define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
137
138 /* TCStatus fields (per TC) */
139 #define TCSTATUS_TASID (_ULCAST_(0xff))
140 #define TCSTATUS_IXMT_SHIFT 10
141 #define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
142 #define TCSTATUS_TKSU_SHIFT 11
143 #define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
144 #define TCSTATUS_A_SHIFT 13
145 #define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
146 #define TCSTATUS_DA_SHIFT 15
147 #define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
148 #define TCSTATUS_DT_SHIFT 20
149 #define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
150 #define TCSTATUS_TDS_SHIFT 21
151 #define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
152 #define TCSTATUS_TSST_SHIFT 22
153 #define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
154 #define TCSTATUS_RNST_SHIFT 23
155 #define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
156 /* Codes for RNST */
157 #define TC_RUNNING 0
158 #define TC_WAITING 1
159 #define TC_YIELDING 2
160 #define TC_GATED 3
161
162 #define TCSTATUS_TMX_SHIFT 27
163 #define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
164 /* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
165
166 /* TCBind */
167 #define TCBIND_CURVPE_SHIFT 0
168 #define TCBIND_CURVPE (_ULCAST_(0xf))
169
170 #define TCBIND_CURTC_SHIFT 21
171
172 #define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
173
174 /* TCHalt */
175 #define TCHALT_H (_ULCAST_(1))
176
177 #ifndef __ASSEMBLY__
178
179 static inline unsigned int dvpe(void)
180 {
181 int res = 0;
182
183 __asm__ __volatile__(
184 " .set push \n"
185 " .set noreorder \n"
186 " .set noat \n"
187 " .set mips32r2 \n"
188 " .word 0x41610001 # dvpe $1 \n"
189 " move %0, $1 \n"
190 " ehb \n"
191 " .set pop \n"
192 : "=r" (res));
193
194 instruction_hazard();
195
196 return res;
197 }
198
199 static inline void __raw_evpe(void)
200 {
201 __asm__ __volatile__(
202 " .set push \n"
203 " .set noreorder \n"
204 " .set noat \n"
205 " .set mips32r2 \n"
206 " .word 0x41600021 # evpe \n"
207 " ehb \n"
208 " .set pop \n");
209 }
210
211 /* Enable virtual processor execution if previous suggested it should be.
212 EVPE_ENABLE to force */
213
214 #define EVPE_ENABLE MVPCONTROL_EVP
215
216 static inline void evpe(int previous)
217 {
218 if ((previous & MVPCONTROL_EVP))
219 __raw_evpe();
220 }
221
222 static inline unsigned int dmt(void)
223 {
224 int res;
225
226 __asm__ __volatile__(
227 " .set push \n"
228 " .set mips32r2 \n"
229 " .set noat \n"
230 " .word 0x41610BC1 # dmt $1 \n"
231 " ehb \n"
232 " move %0, $1 \n"
233 " .set pop \n"
234 : "=r" (res));
235
236 instruction_hazard();
237
238 return res;
239 }
240
241 static inline void __raw_emt(void)
242 {
243 __asm__ __volatile__(
244 " .set noreorder \n"
245 " .set mips32r2 \n"
246 " .word 0x41600be1 # emt \n"
247 " ehb \n"
248 " .set mips0 \n"
249 " .set reorder");
250 }
251
252 /* enable multi-threaded execution if previous suggested it should be.
253 EMT_ENABLE to force */
254
255 #define EMT_ENABLE VPECONTROL_TE
256
257 static inline void emt(int previous)
258 {
259 if ((previous & EMT_ENABLE))
260 __raw_emt();
261 }
262
263 static inline void ehb(void)
264 {
265 __asm__ __volatile__(
266 " .set mips32r2 \n"
267 " ehb \n"
268 " .set mips0 \n");
269 }
270
271 #define mftc0(rt,sel) \
272 ({ \
273 unsigned long __res; \
274 \
275 __asm__ __volatile__( \
276 " .set push \n" \
277 " .set mips32r2 \n" \
278 " .set noat \n" \
279 " # mftc0 $1, $" #rt ", " #sel " \n" \
280 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
281 " move %0, $1 \n" \
282 " .set pop \n" \
283 : "=r" (__res)); \
284 \
285 __res; \
286 })
287
288 #define mftgpr(rt) \
289 ({ \
290 unsigned long __res; \
291 \
292 __asm__ __volatile__( \
293 " .set push \n" \
294 " .set noat \n" \
295 " .set mips32r2 \n" \
296 " # mftgpr $1," #rt " \n" \
297 " .word 0x41000820 | (" #rt " << 16) \n" \
298 " move %0, $1 \n" \
299 " .set pop \n" \
300 : "=r" (__res)); \
301 \
302 __res; \
303 })
304
305 #define mftr(rt, u, sel) \
306 ({ \
307 unsigned long __res; \
308 \
309 __asm__ __volatile__( \
310 " mftr %0, " #rt ", " #u ", " #sel " \n" \
311 : "=r" (__res)); \
312 \
313 __res; \
314 })
315
316 #define mttgpr(rd,v) \
317 do { \
318 __asm__ __volatile__( \
319 " .set push \n" \
320 " .set mips32r2 \n" \
321 " .set noat \n" \
322 " move $1, %0 \n" \
323 " # mttgpr $1, " #rd " \n" \
324 " .word 0x41810020 | (" #rd " << 11) \n" \
325 " .set pop \n" \
326 : : "r" (v)); \
327 } while (0)
328
329 #define mttc0(rd, sel, v) \
330 ({ \
331 __asm__ __volatile__( \
332 " .set push \n" \
333 " .set mips32r2 \n" \
334 " .set noat \n" \
335 " move $1, %0 \n" \
336 " # mttc0 %0," #rd ", " #sel " \n" \
337 " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
338 " .set pop \n" \
339 : \
340 : "r" (v)); \
341 })
342
343
344 #define mttr(rd, u, sel, v) \
345 ({ \
346 __asm__ __volatile__( \
347 "mttr %0," #rd ", " #u ", " #sel \
348 : : "r" (v)); \
349 })
350
351
352 #define settc(tc) \
353 do { \
354 write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
355 ehb(); \
356 } while (0)
357
358
359 /* you *must* set the target tc (settc) before trying to use these */
360 #define read_vpe_c0_vpecontrol() mftc0(1, 1)
361 #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
362 #define read_vpe_c0_vpeconf0() mftc0(1, 2)
363 #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
364 #define read_vpe_c0_vpeconf1() mftc0(1, 3)
365 #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
366 #define read_vpe_c0_count() mftc0(9, 0)
367 #define write_vpe_c0_count(val) mttc0(9, 0, val)
368 #define read_vpe_c0_status() mftc0(12, 0)
369 #define write_vpe_c0_status(val) mttc0(12, 0, val)
370 #define read_vpe_c0_cause() mftc0(13, 0)
371 #define write_vpe_c0_cause(val) mttc0(13, 0, val)
372 #define read_vpe_c0_config() mftc0(16, 0)
373 #define write_vpe_c0_config(val) mttc0(16, 0, val)
374 #define read_vpe_c0_config1() mftc0(16, 1)
375 #define write_vpe_c0_config1(val) mttc0(16, 1, val)
376 #define read_vpe_c0_config7() mftc0(16, 7)
377 #define write_vpe_c0_config7(val) mttc0(16, 7, val)
378 #define read_vpe_c0_ebase() mftc0(15, 1)
379 #define write_vpe_c0_ebase(val) mttc0(15, 1, val)
380 #define write_vpe_c0_compare(val) mttc0(11, 0, val)
381 #define read_vpe_c0_badvaddr() mftc0(8, 0)
382 #define read_vpe_c0_epc() mftc0(14, 0)
383 #define write_vpe_c0_epc(val) mttc0(14, 0, val)
384
385
386 /* TC */
387 #define read_tc_c0_tcstatus() mftc0(2, 1)
388 #define write_tc_c0_tcstatus(val) mttc0(2, 1, val)
389 #define read_tc_c0_tcbind() mftc0(2, 2)
390 #define write_tc_c0_tcbind(val) mttc0(2, 2, val)
391 #define read_tc_c0_tcrestart() mftc0(2, 3)
392 #define write_tc_c0_tcrestart(val) mttc0(2, 3, val)
393 #define read_tc_c0_tchalt() mftc0(2, 4)
394 #define write_tc_c0_tchalt(val) mttc0(2, 4, val)
395 #define read_tc_c0_tccontext() mftc0(2, 5)
396 #define write_tc_c0_tccontext(val) mttc0(2, 5, val)
397
398 /* GPR */
399 #define read_tc_gpr_sp() mftgpr(29)
400 #define write_tc_gpr_sp(val) mttgpr(29, val)
401 #define read_tc_gpr_gp() mftgpr(28)
402 #define write_tc_gpr_gp(val) mttgpr(28, val)
403
404 __BUILD_SET_C0(mvpcontrol)
405
406 #endif /* Not __ASSEMBLY__ */
407
408 #endif
Linux with added FPC-III support