arch/mips/include/asm/netlogic/haldefs.h

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #ifndef __NLM_HAL_HALDEFS_H__
  36 #define __NLM_HAL_HALDEFS_H__
  37
  38 /*
  39  * This file contains platform specific memory mapped IO implementation
  40  * and will provide a way to read 32/64 bit memory mapped registers in
  41  * all ABIs
  42  */
  43 #if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
  44 #error "o32 compile not supported on XLP yet"
  45 #endif
  46 /*
  47  * For o32 compilation, we have to disable interrupts and enable KX bit to
  48  * access 64 bit addresses or data.
  49  *
  50  * We need to disable interrupts because we save just the lower 32 bits of
  51  * registers in  interrupt handling. So if we get hit by an interrupt while
  52  * using the upper 32 bits of a register, we lose.
  53  */
  54 static inline uint32_t nlm_save_flags_kx(void)
  55 {
  56         return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
  57 }
  58
  59 static inline uint32_t nlm_save_flags_cop2(void)
  60 {
  61         return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
  62 }
  63
  64 static inline void nlm_restore_flags(uint32_t sr)
  65 {
  66         write_c0_status(sr);
  67 }
  68
  69 /*
  70  * The n64 implementations are simple, the o32 implementations when they
  71  * are added, will have to disable interrupts and enable KX before doing
  72  * 64 bit ops.
  73  */
  74 static inline uint32_t
  75 nlm_read_reg(uint64_t base, uint32_t reg)
  76 {
  77         volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
  78
  79         return *addr;
  80 }
  81
  82 static inline void
  83 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
  84 {
  85         volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
  86
  87         *addr = val;
  88 }
  89
  90 static inline uint64_t
  91 nlm_read_reg64(uint64_t base, uint32_t reg)
  92 {
  93         uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
  94         volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
  95
  96         return *ptr;
  97 }
  98
  99 static inline void
 100 nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
 101 {
 102         uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
 103         volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
 104
 105         *ptr = val;
 106 }
 107
 108 /*
 109  * Routines to store 32/64 bit values to 64 bit addresses,
 110  * used when going thru XKPHYS to access registers
 111  */
 112 static inline uint32_t
 113 nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
 114 {
 115         return nlm_read_reg(base, reg);
 116 }
 117
 118 static inline void
 119 nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
 120 {
 121         nlm_write_reg(base, reg, val);
 122 }
 123
 124 static inline uint64_t
 125 nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
 126 {
 127         return nlm_read_reg64(base, reg);
 128 }
 129
 130 static inline void
 131 nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
 132 {
 133         nlm_write_reg64(base, reg, val);
 134 }
 135
 136 /* Location where IO base is mapped */
 137 extern uint64_t nlm_io_base;
 138
 139 #if defined(CONFIG_CPU_XLP)
 140 static inline uint64_t
 141 nlm_pcicfg_base(uint32_t devoffset)
 142 {
 143         return nlm_io_base + devoffset;
 144 }
 145
 146 static inline uint64_t
 147 nlm_xkphys_map_pcibar0(uint64_t pcibase)
 148 {
 149         uint64_t paddr;
 150
 151         paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
 152         return (uint64_t)0x9000000000000000 | paddr;
 153 }
 154 #elif defined(CONFIG_CPU_XLR)
 155
 156 static inline uint64_t
 157 nlm_mmio_base(uint32_t devoffset)
 158 {
 159         return nlm_io_base + devoffset;
 160 }
 161 #endif
 162
 163 #endif