arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #ifndef __NLM_HAL_CPUCONTROL_H__
  36 #define __NLM_HAL_CPUCONTROL_H__
  37
  38 #define CPU_BLOCKID_IFU         0
  39 #define CPU_BLOCKID_ICU         1
  40 #define CPU_BLOCKID_IEU         2
  41 #define CPU_BLOCKID_LSU         3
  42 #define CPU_BLOCKID_MMU         4
  43 #define CPU_BLOCKID_PRF         5
  44 #define CPU_BLOCKID_SCH         7
  45 #define CPU_BLOCKID_SCU         8
  46 #define CPU_BLOCKID_FPU         9
  47 #define CPU_BLOCKID_MAP         10
  48
  49 #define LSU_DEFEATURE           0x304
  50 #define LSU_DEBUG_ADDR          0x305
  51 #define LSU_DEBUG_DATA0         0x306
  52 #define LSU_CERRLOG_REGID       0x309
  53 #define SCHED_DEFEATURE         0x700
  54
  55 /* Offsets of interest from the 'MAP' Block */
  56 #define MAP_THREADMODE                  0x00
  57 #define MAP_EXT_EBASE_ENABLE            0x04
  58 #define MAP_CCDI_CONFIG                 0x08
  59 #define MAP_THRD0_CCDI_STATUS           0x0c
  60 #define MAP_THRD1_CCDI_STATUS           0x10
  61 #define MAP_THRD2_CCDI_STATUS           0x14
  62 #define MAP_THRD3_CCDI_STATUS           0x18
  63 #define MAP_THRD0_DEBUG_MODE            0x1c
  64 #define MAP_THRD1_DEBUG_MODE            0x20
  65 #define MAP_THRD2_DEBUG_MODE            0x24
  66 #define MAP_THRD3_DEBUG_MODE            0x28
  67 #define MAP_MISC_STATE                  0x60
  68 #define MAP_DEBUG_READ_CTL              0x64
  69 #define MAP_DEBUG_READ_REG0             0x68
  70 #define MAP_DEBUG_READ_REG1             0x6c
  71
  72 #define MMU_SETUP               0x400
  73 #define MMU_LFSRSEED            0x401
  74 #define MMU_HPW_NUM_PAGE_LVL    0x410
  75 #define MMU_PGWKR_PGDBASE       0x411
  76 #define MMU_PGWKR_PGDSHFT       0x412
  77 #define MMU_PGWKR_PGDMASK       0x413
  78 #define MMU_PGWKR_PUDSHFT       0x414
  79 #define MMU_PGWKR_PUDMASK       0x415
  80 #define MMU_PGWKR_PMDSHFT       0x416
  81 #define MMU_PGWKR_PMDMASK       0x417
  82 #define MMU_PGWKR_PTESHFT       0x418
  83 #define MMU_PGWKR_PTEMASK       0x419
  84
  85 #endif /* __NLM_CPUCONTROL_H__ */