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rtlwifi: rtl8192ce: Change rtl8192ce routines phy and trx and modify rtl8192cu for...
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / wifi.h
blob690508feafcc50df2b69e182f0ce1ad8b83382d2
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
32
33 #include <linux/sched.h>
34 #include <linux/firmware.h>
35 #include <linux/version.h>
36 #include <linux/etherdevice.h>
37 #include <linux/vmalloc.h>
38 #include <linux/usb.h>
39 #include <net/mac80211.h>
40 #include "debug.h"
41
42 #define RF_CHANGE_BY_INIT 0
43 #define RF_CHANGE_BY_IPS BIT(28)
44 #define RF_CHANGE_BY_PS BIT(29)
45 #define RF_CHANGE_BY_HW BIT(30)
46 #define RF_CHANGE_BY_SW BIT(31)
47
48 #define IQK_ADDA_REG_NUM 16
49 #define IQK_MAC_REG_NUM 4
50
51 #define MAX_KEY_LEN 61
52 #define KEY_BUF_SIZE 5
53
54 /* QoS related. */
55 /*aci: 0x00 Best Effort*/
56 /*aci: 0x01 Background*/
57 /*aci: 0x10 Video*/
58 /*aci: 0x11 Voice*/
59 /*Max: define total number.*/
60 #define AC0_BE 0
61 #define AC1_BK 1
62 #define AC2_VI 2
63 #define AC3_VO 3
64 #define AC_MAX 4
65 #define QOS_QUEUE_NUM 4
66 #define RTL_MAC80211_NUM_QUEUE 5
67
68 #define QBSS_LOAD_SIZE 5
69 #define MAX_WMMELE_LENGTH 64
70
71 #define TOTAL_CAM_ENTRY 32
72
73 /*slot time for 11g. */
74 #define RTL_SLOT_TIME_9 9
75 #define RTL_SLOT_TIME_20 20
76
77 /*related with tcp/ip. */
78 /*if_ehther.h*/
79 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
80 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
81 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
82 #define SNAP_SIZE 6
83 #define PROTOC_TYPE_SIZE 2
84
85 /*related with 802.11 frame*/
86 #define MAC80211_3ADDR_LEN 24
87 #define MAC80211_4ADDR_LEN 30
88
89 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
90 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
91 #define MAX_PG_GROUP 13
92 #define CHANNEL_GROUP_MAX_2G 3
93 #define CHANNEL_GROUP_IDX_5GL 3
94 #define CHANNEL_GROUP_IDX_5GM 6
95 #define CHANNEL_GROUP_IDX_5GH 9
96 #define CHANNEL_GROUP_MAX_5G 9
97 #define CHANNEL_MAX_NUMBER_2G 14
98 #define AVG_THERMAL_NUM 8
99 #define MAX_TID_COUNT 9
100
101 /* for early mode */
102 #define FCS_LEN 4
103 #define EM_HDR_LEN 8
104 enum intf_type {
105 INTF_PCI = 0,
106 INTF_USB = 1,
107 };
108
109 enum radio_path {
110 RF90_PATH_A = 0,
111 RF90_PATH_B = 1,
112 RF90_PATH_C = 2,
113 RF90_PATH_D = 3,
114 };
115
116 enum rt_eeprom_type {
117 EEPROM_93C46,
118 EEPROM_93C56,
119 EEPROM_BOOT_EFUSE,
120 };
121
122 enum rtl_status {
123 RTL_STATUS_INTERFACE_START = 0,
124 };
125
126 enum hardware_type {
127 HARDWARE_TYPE_RTL8192E,
128 HARDWARE_TYPE_RTL8192U,
129 HARDWARE_TYPE_RTL8192SE,
130 HARDWARE_TYPE_RTL8192SU,
131 HARDWARE_TYPE_RTL8192CE,
132 HARDWARE_TYPE_RTL8192CU,
133 HARDWARE_TYPE_RTL8192DE,
134 HARDWARE_TYPE_RTL8192DU,
135 HARDWARE_TYPE_RTL8723E,
136 HARDWARE_TYPE_RTL8723U,
137
138 /* keep it last */
139 HARDWARE_TYPE_NUM
140 };
141
142 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
143 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
144 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
145 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
146 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
147 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
148 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
149 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
150 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
151 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
152 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
153 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
154 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
155 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
156 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
157 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
158 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
159 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
160 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
161 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
162 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
163 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
164 #define IS_HARDWARE_TYPE_8723(rtlhal) \
165 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
166 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
167 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
168
169 enum scan_operation_backup_opt {
170 SCAN_OPT_BACKUP = 0,
171 SCAN_OPT_RESTORE,
172 SCAN_OPT_MAX
173 };
174
175 /*RF state.*/
176 enum rf_pwrstate {
177 ERFON,
178 ERFSLEEP,
179 ERFOFF
180 };
181
182 struct bb_reg_def {
183 u32 rfintfs;
184 u32 rfintfi;
185 u32 rfintfo;
186 u32 rfintfe;
187 u32 rf3wire_offset;
188 u32 rflssi_select;
189 u32 rftxgain_stage;
190 u32 rfhssi_para1;
191 u32 rfhssi_para2;
192 u32 rfswitch_control;
193 u32 rfagc_control1;
194 u32 rfagc_control2;
195 u32 rfrxiq_imbalance;
196 u32 rfrx_afe;
197 u32 rftxiq_imbalance;
198 u32 rftx_afe;
199 u32 rflssi_readback;
200 u32 rflssi_readbackpi;
201 };
202
203 enum io_type {
204 IO_CMD_PAUSE_DM_BY_SCAN = 0,
205 IO_CMD_RESUME_DM_BY_SCAN = 1,
206 };
207
208 enum hw_variables {
209 HW_VAR_ETHER_ADDR,
210 HW_VAR_MULTICAST_REG,
211 HW_VAR_BASIC_RATE,
212 HW_VAR_BSSID,
213 HW_VAR_MEDIA_STATUS,
214 HW_VAR_SECURITY_CONF,
215 HW_VAR_BEACON_INTERVAL,
216 HW_VAR_ATIM_WINDOW,
217 HW_VAR_LISTEN_INTERVAL,
218 HW_VAR_CS_COUNTER,
219 HW_VAR_DEFAULTKEY0,
220 HW_VAR_DEFAULTKEY1,
221 HW_VAR_DEFAULTKEY2,
222 HW_VAR_DEFAULTKEY3,
223 HW_VAR_SIFS,
224 HW_VAR_DIFS,
225 HW_VAR_EIFS,
226 HW_VAR_SLOT_TIME,
227 HW_VAR_ACK_PREAMBLE,
228 HW_VAR_CW_CONFIG,
229 HW_VAR_CW_VALUES,
230 HW_VAR_RATE_FALLBACK_CONTROL,
231 HW_VAR_CONTENTION_WINDOW,
232 HW_VAR_RETRY_COUNT,
233 HW_VAR_TR_SWITCH,
234 HW_VAR_COMMAND,
235 HW_VAR_WPA_CONFIG,
236 HW_VAR_AMPDU_MIN_SPACE,
237 HW_VAR_SHORTGI_DENSITY,
238 HW_VAR_AMPDU_FACTOR,
239 HW_VAR_MCS_RATE_AVAILABLE,
240 HW_VAR_AC_PARAM,
241 HW_VAR_ACM_CTRL,
242 HW_VAR_DIS_Req_Qsize,
243 HW_VAR_CCX_CHNL_LOAD,
244 HW_VAR_CCX_NOISE_HISTOGRAM,
245 HW_VAR_CCX_CLM_NHM,
246 HW_VAR_TxOPLimit,
247 HW_VAR_TURBO_MODE,
248 HW_VAR_RF_STATE,
249 HW_VAR_RF_OFF_BY_HW,
250 HW_VAR_BUS_SPEED,
251 HW_VAR_SET_DEV_POWER,
252
253 HW_VAR_RCR,
254 HW_VAR_RATR_0,
255 HW_VAR_RRSR,
256 HW_VAR_CPU_RST,
257 HW_VAR_CECHK_BSSID,
258 HW_VAR_LBK_MODE,
259 HW_VAR_AES_11N_FIX,
260 HW_VAR_USB_RX_AGGR,
261 HW_VAR_USER_CONTROL_TURBO_MODE,
262 HW_VAR_RETRY_LIMIT,
263 HW_VAR_INIT_TX_RATE,
264 HW_VAR_TX_RATE_REG,
265 HW_VAR_EFUSE_USAGE,
266 HW_VAR_EFUSE_BYTES,
267 HW_VAR_AUTOLOAD_STATUS,
268 HW_VAR_RF_2R_DISABLE,
269 HW_VAR_SET_RPWM,
270 HW_VAR_H2C_FW_PWRMODE,
271 HW_VAR_H2C_FW_JOINBSSRPT,
272 HW_VAR_FW_PSMODE_STATUS,
273 HW_VAR_1X1_RECV_COMBINE,
274 HW_VAR_STOP_SEND_BEACON,
275 HW_VAR_TSF_TIMER,
276 HW_VAR_IO_CMD,
277
278 HW_VAR_RF_RECOVERY,
279 HW_VAR_H2C_FW_UPDATE_GTK,
280 HW_VAR_WF_MASK,
281 HW_VAR_WF_CRC,
282 HW_VAR_WF_IS_MAC_ADDR,
283 HW_VAR_H2C_FW_OFFLOAD,
284 HW_VAR_RESET_WFCRC,
285
286 HW_VAR_HANDLE_FW_C2H,
287 HW_VAR_DL_FW_RSVD_PAGE,
288 HW_VAR_AID,
289 HW_VAR_HW_SEQ_ENABLE,
290 HW_VAR_CORRECT_TSF,
291 HW_VAR_BCN_VALID,
292 HW_VAR_FWLPS_RF_ON,
293 HW_VAR_DUAL_TSF_RST,
294 HW_VAR_SWITCH_EPHY_WoWLAN,
295 HW_VAR_INT_MIGRATION,
296 HW_VAR_INT_AC,
297 HW_VAR_RF_TIMING,
298
299 HW_VAR_MRC,
300
301 HW_VAR_MGT_FILTER,
302 HW_VAR_CTRL_FILTER,
303 HW_VAR_DATA_FILTER,
304 };
305
306 enum _RT_MEDIA_STATUS {
307 RT_MEDIA_DISCONNECT = 0,
308 RT_MEDIA_CONNECT = 1
309 };
310
311 enum rt_oem_id {
312 RT_CID_DEFAULT = 0,
313 RT_CID_8187_ALPHA0 = 1,
314 RT_CID_8187_SERCOMM_PS = 2,
315 RT_CID_8187_HW_LED = 3,
316 RT_CID_8187_NETGEAR = 4,
317 RT_CID_WHQL = 5,
318 RT_CID_819x_CAMEO = 6,
319 RT_CID_819x_RUNTOP = 7,
320 RT_CID_819x_Senao = 8,
321 RT_CID_TOSHIBA = 9,
322 RT_CID_819x_Netcore = 10,
323 RT_CID_Nettronix = 11,
324 RT_CID_DLINK = 12,
325 RT_CID_PRONET = 13,
326 RT_CID_COREGA = 14,
327 RT_CID_819x_ALPHA = 15,
328 RT_CID_819x_Sitecom = 16,
329 RT_CID_CCX = 17,
330 RT_CID_819x_Lenovo = 18,
331 RT_CID_819x_QMI = 19,
332 RT_CID_819x_Edimax_Belkin = 20,
333 RT_CID_819x_Sercomm_Belkin = 21,
334 RT_CID_819x_CAMEO1 = 22,
335 RT_CID_819x_MSI = 23,
336 RT_CID_819x_Acer = 24,
337 RT_CID_819x_HP = 27,
338 RT_CID_819x_CLEVO = 28,
339 RT_CID_819x_Arcadyan_Belkin = 29,
340 RT_CID_819x_SAMSUNG = 30,
341 RT_CID_819x_WNC_COREGA = 31,
342 RT_CID_819x_Foxcoon = 32,
343 RT_CID_819x_DELL = 33,
344 };
345
346 enum hw_descs {
347 HW_DESC_OWN,
348 HW_DESC_RXOWN,
349 HW_DESC_TX_NEXTDESC_ADDR,
350 HW_DESC_TXBUFF_ADDR,
351 HW_DESC_RXBUFF_ADDR,
352 HW_DESC_RXPKT_LEN,
353 HW_DESC_RXERO,
354 };
355
356 enum prime_sc {
357 PRIME_CHNL_OFFSET_DONT_CARE = 0,
358 PRIME_CHNL_OFFSET_LOWER = 1,
359 PRIME_CHNL_OFFSET_UPPER = 2,
360 };
361
362 enum rf_type {
363 RF_1T1R = 0,
364 RF_1T2R = 1,
365 RF_2T2R = 2,
366 RF_2T2R_GREEN = 3,
367 };
368
369 enum ht_channel_width {
370 HT_CHANNEL_WIDTH_20 = 0,
371 HT_CHANNEL_WIDTH_20_40 = 1,
372 };
373
374 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
375 Cipher Suites Encryption Algorithms */
376 enum rt_enc_alg {
377 NO_ENCRYPTION = 0,
378 WEP40_ENCRYPTION = 1,
379 TKIP_ENCRYPTION = 2,
380 RSERVED_ENCRYPTION = 3,
381 AESCCMP_ENCRYPTION = 4,
382 WEP104_ENCRYPTION = 5,
383 };
384
385 enum rtl_hal_state {
386 _HAL_STATE_STOP = 0,
387 _HAL_STATE_START = 1,
388 };
389
390 enum rtl_var_map {
391 /*reg map */
392 SYS_ISO_CTRL = 0,
393 SYS_FUNC_EN,
394 SYS_CLK,
395 MAC_RCR_AM,
396 MAC_RCR_AB,
397 MAC_RCR_ACRC32,
398 MAC_RCR_ACF,
399 MAC_RCR_AAP,
400
401 /*efuse map */
402 EFUSE_TEST,
403 EFUSE_CTRL,
404 EFUSE_CLK,
405 EFUSE_CLK_CTRL,
406 EFUSE_PWC_EV12V,
407 EFUSE_FEN_ELDR,
408 EFUSE_LOADER_CLK_EN,
409 EFUSE_ANA8M,
410 EFUSE_HWSET_MAX_SIZE,
411 EFUSE_MAX_SECTION_MAP,
412 EFUSE_REAL_CONTENT_SIZE,
413
414 /*CAM map */
415 RWCAM,
416 WCAMI,
417 RCAMO,
418 CAMDBG,
419 SECR,
420 SEC_CAM_NONE,
421 SEC_CAM_WEP40,
422 SEC_CAM_TKIP,
423 SEC_CAM_AES,
424 SEC_CAM_WEP104,
425
426 /*IMR map */
427 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
428 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
429 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
430 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
431 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
432 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
433 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
434 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
435 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
436 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
437 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
438 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
439 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
440 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
441 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
442 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
443 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
444 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
445 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
446 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
447 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
448 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
449 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
450 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
451 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
452 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
453 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
454 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
455 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
456 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
457 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
458 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
459 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
460 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
461 * RTL_IMR_TBDER) */
462
463 /*CCK Rates, TxHT = 0 */
464 RTL_RC_CCK_RATE1M,
465 RTL_RC_CCK_RATE2M,
466 RTL_RC_CCK_RATE5_5M,
467 RTL_RC_CCK_RATE11M,
468
469 /*OFDM Rates, TxHT = 0 */
470 RTL_RC_OFDM_RATE6M,
471 RTL_RC_OFDM_RATE9M,
472 RTL_RC_OFDM_RATE12M,
473 RTL_RC_OFDM_RATE18M,
474 RTL_RC_OFDM_RATE24M,
475 RTL_RC_OFDM_RATE36M,
476 RTL_RC_OFDM_RATE48M,
477 RTL_RC_OFDM_RATE54M,
478
479 RTL_RC_HT_RATEMCS7,
480 RTL_RC_HT_RATEMCS15,
481
482 /*keep it last */
483 RTL_VAR_MAP_MAX,
484 };
485
486 /*Firmware PS mode for control LPS.*/
487 enum _fw_ps_mode {
488 FW_PS_ACTIVE_MODE = 0,
489 FW_PS_MIN_MODE = 1,
490 FW_PS_MAX_MODE = 2,
491 FW_PS_DTIM_MODE = 3,
492 FW_PS_VOIP_MODE = 4,
493 FW_PS_UAPSD_WMM_MODE = 5,
494 FW_PS_UAPSD_MODE = 6,
495 FW_PS_IBSS_MODE = 7,
496 FW_PS_WWLAN_MODE = 8,
497 FW_PS_PM_Radio_Off = 9,
498 FW_PS_PM_Card_Disable = 10,
499 };
500
501 enum rt_psmode {
502 EACTIVE, /*Active/Continuous access. */
503 EMAXPS, /*Max power save mode. */
504 EFASTPS, /*Fast power save mode. */
505 EAUTOPS, /*Auto power save mode. */
506 };
507
508 /*LED related.*/
509 enum led_ctl_mode {
510 LED_CTL_POWER_ON = 1,
511 LED_CTL_LINK = 2,
512 LED_CTL_NO_LINK = 3,
513 LED_CTL_TX = 4,
514 LED_CTL_RX = 5,
515 LED_CTL_SITE_SURVEY = 6,
516 LED_CTL_POWER_OFF = 7,
517 LED_CTL_START_TO_LINK = 8,
518 LED_CTL_START_WPS = 9,
519 LED_CTL_STOP_WPS = 10,
520 };
521
522 enum rtl_led_pin {
523 LED_PIN_GPIO0,
524 LED_PIN_LED0,
525 LED_PIN_LED1,
526 LED_PIN_LED2
527 };
528
529 /*QoS related.*/
530 /*acm implementation method.*/
531 enum acm_method {
532 eAcmWay0_SwAndHw = 0,
533 eAcmWay1_HW = 1,
534 eAcmWay2_SW = 2,
535 };
536
537 enum macphy_mode {
538 SINGLEMAC_SINGLEPHY = 0,
539 DUALMAC_DUALPHY,
540 DUALMAC_SINGLEPHY,
541 };
542
543 enum band_type {
544 BAND_ON_2_4G = 0,
545 BAND_ON_5G,
546 BAND_ON_BOTH,
547 BANDMAX
548 };
549
550 /*aci/aifsn Field.
551 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
552 union aci_aifsn {
553 u8 char_data;
554
555 struct {
556 u8 aifsn:4;
557 u8 acm:1;
558 u8 aci:2;
559 u8 reserved:1;
560 } f; /* Field */
561 };
562
563 /*mlme related.*/
564 enum wireless_mode {
565 WIRELESS_MODE_UNKNOWN = 0x00,
566 WIRELESS_MODE_A = 0x01,
567 WIRELESS_MODE_B = 0x02,
568 WIRELESS_MODE_G = 0x04,
569 WIRELESS_MODE_AUTO = 0x08,
570 WIRELESS_MODE_N_24G = 0x10,
571 WIRELESS_MODE_N_5G = 0x20
572 };
573
574 #define IS_WIRELESS_MODE_A(wirelessmode) \
575 (wirelessmode == WIRELESS_MODE_A)
576 #define IS_WIRELESS_MODE_B(wirelessmode) \
577 (wirelessmode == WIRELESS_MODE_B)
578 #define IS_WIRELESS_MODE_G(wirelessmode) \
579 (wirelessmode == WIRELESS_MODE_G)
580 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
581 (wirelessmode == WIRELESS_MODE_N_24G)
582 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
583 (wirelessmode == WIRELESS_MODE_N_5G)
584
585 enum ratr_table_mode {
586 RATR_INX_WIRELESS_NGB = 0,
587 RATR_INX_WIRELESS_NG = 1,
588 RATR_INX_WIRELESS_NB = 2,
589 RATR_INX_WIRELESS_N = 3,
590 RATR_INX_WIRELESS_GB = 4,
591 RATR_INX_WIRELESS_G = 5,
592 RATR_INX_WIRELESS_B = 6,
593 RATR_INX_WIRELESS_MC = 7,
594 RATR_INX_WIRELESS_A = 8,
595 };
596
597 enum rtl_link_state {
598 MAC80211_NOLINK = 0,
599 MAC80211_LINKING = 1,
600 MAC80211_LINKED = 2,
601 MAC80211_LINKED_SCANNING = 3,
602 };
603
604 enum act_category {
605 ACT_CAT_QOS = 1,
606 ACT_CAT_DLS = 2,
607 ACT_CAT_BA = 3,
608 ACT_CAT_HT = 7,
609 ACT_CAT_WMM = 17,
610 };
611
612 enum ba_action {
613 ACT_ADDBAREQ = 0,
614 ACT_ADDBARSP = 1,
615 ACT_DELBA = 2,
616 };
617
618 struct octet_string {
619 u8 *octet;
620 u16 length;
621 };
622
623 struct rtl_hdr_3addr {
624 __le16 frame_ctl;
625 __le16 duration_id;
626 u8 addr1[ETH_ALEN];
627 u8 addr2[ETH_ALEN];
628 u8 addr3[ETH_ALEN];
629 __le16 seq_ctl;
630 u8 payload[0];
631 } __packed;
632
633 struct rtl_info_element {
634 u8 id;
635 u8 len;
636 u8 data[0];
637 } __packed;
638
639 struct rtl_probe_rsp {
640 struct rtl_hdr_3addr header;
641 u32 time_stamp[2];
642 __le16 beacon_interval;
643 __le16 capability;
644 /*SSID, supported rates, FH params, DS params,
645 CF params, IBSS params, TIM (if beacon), RSN */
646 struct rtl_info_element info_element[0];
647 } __packed;
648
649 /*LED related.*/
650 /*ledpin Identify how to implement this SW led.*/
651 struct rtl_led {
652 void *hw;
653 enum rtl_led_pin ledpin;
654 bool ledon;
655 };
656
657 struct rtl_led_ctl {
658 bool led_opendrain;
659 struct rtl_led sw_led0;
660 struct rtl_led sw_led1;
661 };
662
663 struct rtl_qos_parameters {
664 __le16 cw_min;
665 __le16 cw_max;
666 u8 aifs;
667 u8 flag;
668 __le16 tx_op;
669 } __packed;
670
671 struct rt_smooth_data {
672 u32 elements[100]; /*array to store values */
673 u32 index; /*index to current array to store */
674 u32 total_num; /*num of valid elements */
675 u32 total_val; /*sum of valid elements */
676 };
677
678 struct false_alarm_statistics {
679 u32 cnt_parity_fail;
680 u32 cnt_rate_illegal;
681 u32 cnt_crc8_fail;
682 u32 cnt_mcs_fail;
683 u32 cnt_fast_fsync_fail;
684 u32 cnt_sb_search_fail;
685 u32 cnt_ofdm_fail;
686 u32 cnt_cck_fail;
687 u32 cnt_all;
688 };
689
690 struct init_gain {
691 u8 xaagccore1;
692 u8 xbagccore1;
693 u8 xcagccore1;
694 u8 xdagccore1;
695 u8 cca;
696
697 };
698
699 struct wireless_stats {
700 unsigned long txbytesunicast;
701 unsigned long txbytesmulticast;
702 unsigned long txbytesbroadcast;
703 unsigned long rxbytesunicast;
704
705 long rx_snr_db[4];
706 /*Correct smoothed ss in Dbm, only used
707 in driver to report real power now. */
708 long recv_signal_power;
709 long signal_quality;
710 long last_sigstrength_inpercent;
711
712 u32 rssi_calculate_cnt;
713
714 /*Transformed, in dbm. Beautified signal
715 strength for UI, not correct. */
716 long signal_strength;
717
718 u8 rx_rssi_percentage[4];
719 u8 rx_evm_percentage[2];
720
721 struct rt_smooth_data ui_rssi;
722 struct rt_smooth_data ui_link_quality;
723 };
724
725 struct rate_adaptive {
726 u8 rate_adaptive_disabled;
727 u8 ratr_state;
728 u16 reserve;
729
730 u32 high_rssi_thresh_for_ra;
731 u32 high2low_rssi_thresh_for_ra;
732 u8 low2high_rssi_thresh_for_ra40m;
733 u32 low_rssi_thresh_for_ra40M;
734 u8 low2high_rssi_thresh_for_ra20m;
735 u32 low_rssi_thresh_for_ra20M;
736 u32 upper_rssi_threshold_ratr;
737 u32 middleupper_rssi_threshold_ratr;
738 u32 middle_rssi_threshold_ratr;
739 u32 middlelow_rssi_threshold_ratr;
740 u32 low_rssi_threshold_ratr;
741 u32 ultralow_rssi_threshold_ratr;
742 u32 low_rssi_threshold_ratr_40m;
743 u32 low_rssi_threshold_ratr_20m;
744 u8 ping_rssi_enable;
745 u32 ping_rssi_ratr;
746 u32 ping_rssi_thresh_for_ra;
747 u32 last_ratr;
748 u8 pre_ratr_state;
749 };
750
751 struct regd_pair_mapping {
752 u16 reg_dmnenum;
753 u16 reg_5ghz_ctl;
754 u16 reg_2ghz_ctl;
755 };
756
757 struct rtl_regulatory {
758 char alpha2[2];
759 u16 country_code;
760 u16 max_power_level;
761 u32 tp_scale;
762 u16 current_rd;
763 u16 current_rd_ext;
764 int16_t power_limit;
765 struct regd_pair_mapping *regpair;
766 };
767
768 struct rtl_rfkill {
769 bool rfkill_state; /*0 is off, 1 is on */
770 };
771
772 #define IQK_MATRIX_REG_NUM 8
773 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
774 struct iqk_matrix_regs {
775 bool iqk_done;
776 long value[1][IQK_MATRIX_REG_NUM];
777 };
778
779 struct phy_parameters {
780 u16 length;
781 u32 *pdata;
782 };
783
784 enum hw_param_tab_index {
785 PHY_REG_2T,
786 PHY_REG_1T,
787 PHY_REG_PG,
788 RADIOA_2T,
789 RADIOB_2T,
790 RADIOA_1T,
791 RADIOB_1T,
792 MAC_REG,
793 AGCTAB_2T,
794 AGCTAB_1T,
795 MAX_TAB
796 };
797
798 struct rtl_phy {
799 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
800 struct init_gain initgain_backup;
801 enum io_type current_io_type;
802
803 u8 rf_mode;
804 u8 rf_type;
805 u8 current_chan_bw;
806 u8 set_bwmode_inprogress;
807 u8 sw_chnl_inprogress;
808 u8 sw_chnl_stage;
809 u8 sw_chnl_step;
810 u8 current_channel;
811 u8 h2c_box_num;
812 u8 set_io_inprogress;
813 u8 lck_inprogress;
814
815 /* record for power tracking */
816 s32 reg_e94;
817 s32 reg_e9c;
818 s32 reg_ea4;
819 s32 reg_eac;
820 s32 reg_eb4;
821 s32 reg_ebc;
822 s32 reg_ec4;
823 s32 reg_ecc;
824 u8 rfpienable;
825 u8 reserve_0;
826 u16 reserve_1;
827 u32 reg_c04, reg_c08, reg_874;
828 u32 adda_backup[16];
829 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
830 u32 iqk_bb_backup[10];
831
832 /* Dual mac */
833 bool need_iqk;
834 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
835
836 bool rfpi_enable;
837
838 u8 pwrgroup_cnt;
839 u8 cck_high_power;
840 /* MAX_PG_GROUP groups of pwr diff by rates */
841 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
842 u8 default_initialgain[4];
843
844 /* the current Tx power level */
845 u8 cur_cck_txpwridx;
846 u8 cur_ofdm24g_txpwridx;
847
848 u32 rfreg_chnlval[2];
849 bool apk_done;
850 u32 reg_rf3c[2]; /* pathA / pathB */
851
852 /* bfsync */
853 u8 framesync;
854 u32 framesync_c34;
855
856 u8 num_total_rfpath;
857 struct phy_parameters hwparam_tables[MAX_TAB];
858 u16 rf_pathmap;
859 };
860
861 #define MAX_TID_COUNT 9
862 #define RTL_AGG_STOP 0
863 #define RTL_AGG_PROGRESS 1
864 #define RTL_AGG_START 2
865 #define RTL_AGG_OPERATIONAL 3
866 #define RTL_AGG_OFF 0
867 #define RTL_AGG_ON 1
868 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
869 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
870
871 struct rtl_ht_agg {
872 u16 txq_id;
873 u16 wait_for_ba;
874 u16 start_idx;
875 u64 bitmap;
876 u32 rate_n_flags;
877 u8 agg_state;
878 };
879
880 struct rtl_tid_data {
881 u16 seq_number;
882 struct rtl_ht_agg agg;
883 };
884
885 struct rtl_sta_info {
886 u8 ratr_index;
887 u8 wireless_mode;
888 u8 mimo_ps;
889 struct rtl_tid_data tids[MAX_TID_COUNT];
890 } __packed;
891
892 struct rtl_priv;
893 struct rtl_io {
894 struct device *dev;
895 struct mutex bb_mutex;
896
897 /*PCI MEM map */
898 unsigned long pci_mem_end; /*shared mem end */
899 unsigned long pci_mem_start; /*shared mem start */
900
901 /*PCI IO map */
902 unsigned long pci_base_addr; /*device I/O address */
903
904 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
905 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
906 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
907 int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
908 u8 *pdata);
909
910 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
911 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
912 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
913 int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
914 u8 *pdata);
915
916 };
917
918 struct rtl_mac {
919 u8 mac_addr[ETH_ALEN];
920 u8 mac80211_registered;
921 u8 beacon_enabled;
922
923 u32 tx_ss_num;
924 u32 rx_ss_num;
925
926 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
927 struct ieee80211_hw *hw;
928 struct ieee80211_vif *vif;
929 enum nl80211_iftype opmode;
930
931 /*Probe Beacon management */
932 struct rtl_tid_data tids[MAX_TID_COUNT];
933 enum rtl_link_state link_state;
934
935 int n_channels;
936 int n_bitrates;
937
938 bool offchan_deley;
939
940 /*filters */
941 u32 rx_conf;
942 u16 rx_mgt_filter;
943 u16 rx_ctrl_filter;
944 u16 rx_data_filter;
945
946 bool act_scanning;
947 u8 cnt_after_linked;
948
949 /* early mode */
950 /* skb wait queue */
951 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
952 u8 earlymode_threshold;
953
954 /*RDG*/
955 bool rdg_en;
956
957 /*AP*/
958 u8 bssid[6];
959 u32 vendor;
960 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
961 u32 basic_rates; /* b/g rates */
962 u8 ht_enable;
963 u8 sgi_40;
964 u8 sgi_20;
965 u8 bw_40;
966 u8 mode; /* wireless mode */
967 u8 slot_time;
968 u8 short_preamble;
969 u8 use_cts_protect;
970 u8 cur_40_prime_sc;
971 u8 cur_40_prime_sc_bk;
972 u64 tsf;
973 u8 retry_short;
974 u8 retry_long;
975 u16 assoc_id;
976
977 /*IBSS*/
978 int beacon_interval;
979
980 /*AMPDU*/
981 u8 min_space_cfg; /*For Min spacing configurations */
982 u8 max_mss_density;
983 u8 current_ampdu_factor;
984 u8 current_ampdu_density;
985
986 /*QOS & EDCA */
987 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
988 struct rtl_qos_parameters ac[AC_MAX];
989 };
990
991 struct rtl_hal {
992 struct ieee80211_hw *hw;
993
994 enum intf_type interface;
995 u16 hw_type; /*92c or 92d or 92s and so on */
996 u8 ic_class;
997 u8 oem_id;
998 u32 version; /*version of chip */
999 u8 state; /*stop 0, start 1 */
1000
1001 /*firmware */
1002 u32 fwsize;
1003 u8 *pfirmware;
1004 u16 fw_version;
1005 u16 fw_subversion;
1006 bool h2c_setinprogress;
1007 u8 last_hmeboxnum;
1008 bool fw_ready;
1009 /*Reserve page start offset except beacon in TxQ. */
1010 u8 fw_rsvdpage_startoffset;
1011 u8 h2c_txcmd_seq;
1012
1013 /* FW Cmd IO related */
1014 u16 fwcmd_iomap;
1015 u32 fwcmd_ioparam;
1016 bool set_fwcmd_inprogress;
1017 u8 current_fwcmd_io;
1018
1019 /**/
1020 bool driver_going2unload;
1021
1022 /*AMPDU init min space*/
1023 u8 minspace_cfg; /*For Min spacing configurations */
1024
1025 /* Dual mac */
1026 enum macphy_mode macphymode;
1027 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1028 enum band_type current_bandtypebackup;
1029 enum band_type bandset;
1030 /* dual MAC 0--Mac0 1--Mac1 */
1031 u32 interfaceindex;
1032 /* just for DualMac S3S4 */
1033 u8 macphyctl_reg;
1034 bool earlymode_enable;
1035 /* Dual mac*/
1036 bool during_mac0init_radiob;
1037 bool during_mac1init_radioa;
1038 bool reloadtxpowerindex;
1039 /* True if IMR or IQK have done
1040 for 2.4G in scan progress */
1041 bool load_imrandiqk_setting_for2g;
1042
1043 bool disable_amsdu_8k;
1044 };
1045
1046 struct rtl_security {
1047 /*default 0 */
1048 bool use_sw_sec;
1049
1050 bool being_setkey;
1051 bool use_defaultkey;
1052 /*Encryption Algorithm for Unicast Packet */
1053 enum rt_enc_alg pairwise_enc_algorithm;
1054 /*Encryption Algorithm for Brocast/Multicast */
1055 enum rt_enc_alg group_enc_algorithm;
1056 /*Cam Entry Bitmap */
1057 u32 hwsec_cam_bitmap;
1058 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1059 /*local Key buffer, indx 0 is for
1060 pairwise key 1-4 is for agoup key. */
1061 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1062 u8 key_len[KEY_BUF_SIZE];
1063
1064 /*The pointer of Pairwise Key,
1065 it always points to KeyBuf[4] */
1066 u8 *pairwise_key;
1067 };
1068
1069 struct rtl_dm {
1070 /*PHY status for Dynamic Management */
1071 long entry_min_undecoratedsmoothed_pwdb;
1072 long undecorated_smoothed_pwdb; /*out dm */
1073 long entry_max_undecoratedsmoothed_pwdb;
1074 bool dm_initialgain_enable;
1075 bool dynamic_txpower_enable;
1076 bool current_turbo_edca;
1077 bool is_any_nonbepkts; /*out dm */
1078 bool is_cur_rdlstate;
1079 bool txpower_trackinginit;
1080 bool disable_framebursting;
1081 bool cck_inch14;
1082 bool txpower_tracking;
1083 bool useramask;
1084 bool rfpath_rxenable[4];
1085 bool inform_fw_driverctrldm;
1086 bool current_mrc_switch;
1087 u8 txpowercount;
1088
1089 u8 thermalvalue_rxgain;
1090 u8 thermalvalue_iqk;
1091 u8 thermalvalue_lck;
1092 u8 thermalvalue;
1093 u8 last_dtp_lvl;
1094 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1095 u8 thermalvalue_avg_index;
1096 bool done_txpower;
1097 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1098 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1099 u8 dm_type;
1100 u8 txpower_track_control;
1101 bool interrupt_migration;
1102 bool disable_tx_int;
1103 char ofdm_index[2];
1104 char cck_index;
1105 };
1106
1107 #define EFUSE_MAX_LOGICAL_SIZE 256
1108
1109 struct rtl_efuse {
1110 bool autoLoad_ok;
1111 bool bootfromefuse;
1112 u16 max_physical_size;
1113
1114 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1115 u16 efuse_usedbytes;
1116 u8 efuse_usedpercentage;
1117 #ifdef EFUSE_REPG_WORKAROUND
1118 bool efuse_re_pg_sec1flag;
1119 u8 efuse_re_pg_data[8];
1120 #endif
1121
1122 u8 autoload_failflag;
1123 u8 autoload_status;
1124
1125 short epromtype;
1126 u16 eeprom_vid;
1127 u16 eeprom_did;
1128 u16 eeprom_svid;
1129 u16 eeprom_smid;
1130 u8 eeprom_oemid;
1131 u16 eeprom_channelplan;
1132 u8 eeprom_version;
1133 u8 board_type;
1134 u8 external_pa;
1135
1136 u8 dev_addr[6];
1137
1138 bool txpwr_fromeprom;
1139 u8 eeprom_crystalcap;
1140 u8 eeprom_tssi[2];
1141 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1142 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1143 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1144 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1145 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1146 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1147 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1148 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1149 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1150
1151 u8 internal_pa_5g[2]; /* pathA / pathB */
1152 u8 eeprom_c9;
1153 u8 eeprom_cc;
1154
1155 /*For power group */
1156 u8 eeprom_pwrgroup[2][3];
1157 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1158 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1159
1160 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1161 /*For HT<->legacy pwr diff*/
1162 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1163 u8 txpwr_safetyflag; /* Band edge enable flag */
1164 u16 eeprom_txpowerdiff;
1165 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1166 u8 antenna_txpwdiff[3];
1167
1168 u8 eeprom_regulatory;
1169 u8 eeprom_thermalmeter;
1170 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1171 u16 tssi_13dbm;
1172 u8 crystalcap; /* CrystalCap. */
1173 u8 delta_iqk;
1174 u8 delta_lck;
1175
1176 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1177 bool apk_thermalmeterignore;
1178
1179 bool b1x1_recvcombine;
1180 bool b1ss_support;
1181
1182 /*channel plan */
1183 u8 channel_plan;
1184 };
1185
1186 struct rtl_ps_ctl {
1187 bool pwrdomain_protect;
1188 bool set_rfpowerstate_inprogress;
1189 bool in_powersavemode;
1190 bool rfchange_inprogress;
1191 bool swrf_processing;
1192 bool hwradiooff;
1193
1194 /*
1195 * just for PCIE ASPM
1196 * If it supports ASPM, Offset[560h] = 0x40,
1197 * otherwise Offset[560h] = 0x00.
1198 * */
1199 bool support_aspm;
1200
1201 bool support_backdoor;
1202
1203 /*for LPS */
1204 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1205 bool swctrl_lps;
1206 bool leisure_ps;
1207 bool fwctrl_lps;
1208 u8 fwctrl_psmode;
1209 /*For Fw control LPS mode */
1210 u8 reg_fwctrl_lps;
1211 /*Record Fw PS mode status. */
1212 bool fw_current_inpsmode;
1213 u8 reg_max_lps_awakeintvl;
1214 bool report_linked;
1215
1216 /*for IPS */
1217 bool inactiveps;
1218
1219 u32 rfoff_reason;
1220
1221 /*RF OFF Level */
1222 u32 cur_ps_level;
1223 u32 reg_rfps_level;
1224
1225 /*just for PCIE ASPM */
1226 u8 const_amdpci_aspm;
1227 bool pwrdown_mode;
1228
1229 enum rf_pwrstate inactive_pwrstate;
1230 enum rf_pwrstate rfpwr_state; /*cur power state */
1231
1232 /* for SW LPS*/
1233 bool sw_ps_enabled;
1234 bool state;
1235 bool state_inap;
1236 bool multi_buffered;
1237 u16 nullfunc_seq;
1238 unsigned int dtim_counter;
1239 unsigned int sleep_ms;
1240 unsigned long last_sleep_jiffies;
1241 unsigned long last_awake_jiffies;
1242 unsigned long last_delaylps_stamp_jiffies;
1243 unsigned long last_dtim;
1244 unsigned long last_beacon;
1245 unsigned long last_action;
1246 unsigned long last_slept;
1247 };
1248
1249 struct rtl_stats {
1250 u32 mac_time[2];
1251 s8 rssi;
1252 u8 signal;
1253 u8 noise;
1254 u16 rate; /*in 100 kbps */
1255 u8 received_channel;
1256 u8 control;
1257 u8 mask;
1258 u8 freq;
1259 u16 len;
1260 u64 tsf;
1261 u32 beacon_time;
1262 u8 nic_type;
1263 u16 length;
1264 u8 signalquality; /*in 0-100 index. */
1265 /*
1266 * Real power in dBm for this packet,
1267 * no beautification and aggregation.
1268 * */
1269 s32 recvsignalpower;
1270 s8 rxpower; /*in dBm Translate from PWdB */
1271 u8 signalstrength; /*in 0-100 index. */
1272 u16 hwerror:1;
1273 u16 crc:1;
1274 u16 icv:1;
1275 u16 shortpreamble:1;
1276 u16 antenna:1;
1277 u16 decrypted:1;
1278 u16 wakeup:1;
1279 u32 timestamp_low;
1280 u32 timestamp_high;
1281
1282 u8 rx_drvinfo_size;
1283 u8 rx_bufshift;
1284 bool isampdu;
1285 bool isfirst_ampdu;
1286 bool rx_is40Mhzpacket;
1287 u32 rx_pwdb_all;
1288 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1289 s8 rx_mimo_signalquality[2];
1290 bool packet_matchbssid;
1291 bool is_cck;
1292 bool packet_toself;
1293 bool packet_beacon; /*for rssi */
1294 char cck_adc_pwdb[4]; /*for rx path selection */
1295 };
1296
1297 struct rt_link_detect {
1298 u32 num_tx_in4period[4];
1299 u32 num_rx_in4period[4];
1300
1301 u32 num_tx_inperiod;
1302 u32 num_rx_inperiod;
1303
1304 bool busytraffic;
1305 bool higher_busytraffic;
1306 bool higher_busyrxtraffic;
1307
1308 u32 tidtx_in4period[MAX_TID_COUNT][4];
1309 u32 tidtx_inperiod[MAX_TID_COUNT];
1310 bool higher_busytxtraffic[MAX_TID_COUNT];
1311 };
1312
1313 struct rtl_tcb_desc {
1314 u8 packet_bw:1;
1315 u8 multicast:1;
1316 u8 broadcast:1;
1317
1318 u8 rts_stbc:1;
1319 u8 rts_enable:1;
1320 u8 cts_enable:1;
1321 u8 rts_use_shortpreamble:1;
1322 u8 rts_use_shortgi:1;
1323 u8 rts_sc:1;
1324 u8 rts_bw:1;
1325 u8 rts_rate;
1326
1327 u8 use_shortgi:1;
1328 u8 use_shortpreamble:1;
1329 u8 use_driver_rate:1;
1330 u8 disable_ratefallback:1;
1331
1332 u8 ratr_index;
1333 u8 mac_id;
1334 u8 hw_rate;
1335
1336 u8 last_inipkt:1;
1337 u8 cmd_or_init:1;
1338 u8 queue_index;
1339
1340 /* early mode */
1341 u8 empkt_num;
1342 /* The max value by HW */
1343 u32 empkt_len[5];
1344 };
1345
1346 struct rtl_hal_ops {
1347 int (*init_sw_vars) (struct ieee80211_hw *hw);
1348 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1349 void (*read_chip_version)(struct ieee80211_hw *hw);
1350 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1351 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1352 u32 *p_inta, u32 *p_intb);
1353 int (*hw_init) (struct ieee80211_hw *hw);
1354 void (*hw_disable) (struct ieee80211_hw *hw);
1355 void (*hw_suspend) (struct ieee80211_hw *hw);
1356 void (*hw_resume) (struct ieee80211_hw *hw);
1357 void (*enable_interrupt) (struct ieee80211_hw *hw);
1358 void (*disable_interrupt) (struct ieee80211_hw *hw);
1359 int (*set_network_type) (struct ieee80211_hw *hw,
1360 enum nl80211_iftype type);
1361 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1362 bool check_bssid);
1363 void (*set_bw_mode) (struct ieee80211_hw *hw,
1364 enum nl80211_channel_type ch_type);
1365 u8(*switch_channel) (struct ieee80211_hw *hw);
1366 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1367 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1368 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1369 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1370 u32 add_msr, u32 rm_msr);
1371 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1372 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1373 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1374 struct ieee80211_sta *sta, u8 rssi_level);
1375 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1376 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1377 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1378 struct ieee80211_tx_info *info,
1379 struct sk_buff *skb, u8 hw_queue,
1380 struct rtl_tcb_desc *ptcb_desc);
1381 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1382 u32 buffer_len, bool bIsPsPoll);
1383 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1384 bool firstseg, bool lastseg,
1385 struct sk_buff *skb);
1386 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1387 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1388 struct rtl_stats *stats,
1389 struct ieee80211_rx_status *rx_status,
1390 u8 *pdesc, struct sk_buff *skb);
1391 void (*set_channel_access) (struct ieee80211_hw *hw);
1392 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1393 void (*dm_watchdog) (struct ieee80211_hw *hw);
1394 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1395 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1396 enum rf_pwrstate rfpwr_state);
1397 void (*led_control) (struct ieee80211_hw *hw,
1398 enum led_ctl_mode ledaction);
1399 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1400 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1401 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1402 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1403 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1404 u8 *macaddr, bool is_group, u8 enc_algo,
1405 bool is_wepkey, bool clear_all);
1406 void (*init_sw_leds) (struct ieee80211_hw *hw);
1407 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1408 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1409 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1410 u32 data);
1411 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1412 u32 regaddr, u32 bitmask);
1413 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1414 u32 regaddr, u32 bitmask, u32 data);
1415 void (*linked_set_reg) (struct ieee80211_hw *hw);
1416 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1417 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1418 u8 *powerlevel);
1419 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1420 u8 *ppowerlevel, u8 channel);
1421 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1422 u8 configtype);
1423 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1424 u8 configtype);
1425 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1426 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1427 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1428 };
1429
1430 struct rtl_intf_ops {
1431 /*com */
1432 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1433 int (*adapter_start) (struct ieee80211_hw *hw);
1434 void (*adapter_stop) (struct ieee80211_hw *hw);
1435
1436 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1437 struct rtl_tcb_desc *ptcb_desc);
1438 void (*flush)(struct ieee80211_hw *hw, bool drop);
1439 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1440 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1441
1442 /*pci */
1443 void (*disable_aspm) (struct ieee80211_hw *hw);
1444 void (*enable_aspm) (struct ieee80211_hw *hw);
1445
1446 /*usb */
1447 };
1448
1449 struct rtl_mod_params {
1450 /* default: 0 = using hardware encryption */
1451 int sw_crypto;
1452
1453 /* default: 1 = using no linked power save */
1454 bool inactiveps;
1455
1456 /* default: 1 = using linked sw power save */
1457 bool swctrl_lps;
1458
1459 /* default: 1 = using linked fw power save */
1460 bool fwctrl_lps;
1461 };
1462
1463 struct rtl_hal_usbint_cfg {
1464 /* data - rx */
1465 u32 in_ep_num;
1466 u32 rx_urb_num;
1467 u32 rx_max_size;
1468
1469 /* op - rx */
1470 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1471 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1472 struct sk_buff_head *);
1473
1474 /* tx */
1475 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1476 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1477 struct sk_buff *);
1478 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1479 struct sk_buff_head *);
1480
1481 /* endpoint mapping */
1482 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1483 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1484 };
1485
1486 struct rtl_hal_cfg {
1487 u8 bar_id;
1488 bool write_readback;
1489 char *name;
1490 char *fw_name;
1491 struct rtl_hal_ops *ops;
1492 struct rtl_mod_params *mod_params;
1493 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1494
1495 /*this map used for some registers or vars
1496 defined int HAL but used in MAIN */
1497 u32 maps[RTL_VAR_MAP_MAX];
1498
1499 };
1500
1501 struct rtl_locks {
1502 /* mutex */
1503 struct mutex conf_mutex;
1504
1505 /*spin lock */
1506 spinlock_t ips_lock;
1507 spinlock_t irq_th_lock;
1508 spinlock_t h2c_lock;
1509 spinlock_t rf_ps_lock;
1510 spinlock_t rf_lock;
1511 spinlock_t lps_lock;
1512 spinlock_t waitq_lock;
1513
1514 /*Dual mac*/
1515 spinlock_t cck_and_rw_pagea_lock;
1516 };
1517
1518 struct rtl_works {
1519 struct ieee80211_hw *hw;
1520
1521 /*timer */
1522 struct timer_list watchdog_timer;
1523
1524 /*task */
1525 struct tasklet_struct irq_tasklet;
1526 struct tasklet_struct irq_prepare_bcn_tasklet;
1527
1528 /*work queue */
1529 struct workqueue_struct *rtl_wq;
1530 struct delayed_work watchdog_wq;
1531 struct delayed_work ips_nic_off_wq;
1532
1533 /* For SW LPS */
1534 struct delayed_work ps_work;
1535 struct delayed_work ps_rfon_wq;
1536 };
1537
1538 struct rtl_debug {
1539 u32 dbgp_type[DBGP_TYPE_MAX];
1540 u32 global_debuglevel;
1541 u64 global_debugcomponents;
1542
1543 /* add for proc debug */
1544 struct proc_dir_entry *proc_dir;
1545 char proc_name[20];
1546 };
1547
1548 struct rtl_priv {
1549 struct rtl_locks locks;
1550 struct rtl_works works;
1551 struct rtl_mac mac80211;
1552 struct rtl_hal rtlhal;
1553 struct rtl_regulatory regd;
1554 struct rtl_rfkill rfkill;
1555 struct rtl_io io;
1556 struct rtl_phy phy;
1557 struct rtl_dm dm;
1558 struct rtl_security sec;
1559 struct rtl_efuse efuse;
1560
1561 struct rtl_ps_ctl psc;
1562 struct rate_adaptive ra;
1563 struct wireless_stats stats;
1564 struct rt_link_detect link_info;
1565 struct false_alarm_statistics falsealm_cnt;
1566
1567 struct rtl_rate_priv *rate_priv;
1568
1569 struct rtl_debug dbg;
1570
1571 /*
1572 *hal_cfg : for diff cards
1573 *intf_ops : for diff interrface usb/pcie
1574 */
1575 struct rtl_hal_cfg *cfg;
1576 struct rtl_intf_ops *intf_ops;
1577
1578 /*this var will be set by set_bit,
1579 and was used to indicate status of
1580 interface or hardware */
1581 unsigned long status;
1582
1583 /*This must be the last item so
1584 that it points to the data allocated
1585 beyond this structure like:
1586 rtl_pci_priv or rtl_usb_priv */
1587 u8 priv[0];
1588 };
1589
1590 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1591 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1592 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1593 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1594 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1595
1596
1597 /***************************************
1598 Bluetooth Co-existance Related
1599 ****************************************/
1600
1601 enum bt_ant_num {
1602 ANT_X2 = 0,
1603 ANT_X1 = 1,
1604 };
1605
1606 enum bt_co_type {
1607 BT_2WIRE = 0,
1608 BT_ISSC_3WIRE = 1,
1609 BT_ACCEL = 2,
1610 BT_CSR_BC4 = 3,
1611 BT_CSR_BC8 = 4,
1612 BT_RTL8756 = 5,
1613 };
1614
1615 enum bt_cur_state {
1616 BT_OFF = 0,
1617 BT_ON = 1,
1618 };
1619
1620 enum bt_service_type {
1621 BT_SCO = 0,
1622 BT_A2DP = 1,
1623 BT_HID = 2,
1624 BT_HID_IDLE = 3,
1625 BT_SCAN = 4,
1626 BT_IDLE = 5,
1627 BT_OTHER_ACTION = 6,
1628 BT_BUSY = 7,
1629 BT_OTHERBUSY = 8,
1630 BT_PAN = 9,
1631 };
1632
1633 enum bt_radio_shared {
1634 BT_RADIO_SHARED = 0,
1635 BT_RADIO_INDIVIDUAL = 1,
1636 };
1637
1638 struct bt_coexist_info {
1639
1640 /* EEPROM BT info. */
1641 u8 eeprom_bt_coexist;
1642 u8 eeprom_bt_type;
1643 u8 eeprom_bt_ant_num;
1644 u8 eeprom_bt_ant_isolation;
1645 u8 eeprom_bt_radio_shared;
1646
1647 u8 bt_coexistence;
1648 u8 bt_ant_num;
1649 u8 bt_coexist_type;
1650 u8 bt_state;
1651 u8 bt_cur_state; /* 0:on, 1:off */
1652 u8 bt_ant_isolation; /* 0:good, 1:bad */
1653 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1654 u8 bt_service;
1655 u8 bt_radio_shared_type;
1656 u8 bt_rfreg_origin_1e;
1657 u8 bt_rfreg_origin_1f;
1658 u8 bt_rssi_state;
1659 u32 ratio_tx;
1660 u32 ratio_pri;
1661 u32 bt_edca_ul;
1662 u32 bt_edca_dl;
1663
1664 bool init_set;
1665 bool bt_busy_traffic;
1666 bool bt_traffic_mode_set;
1667 bool bt_non_traffic_mode_set;
1668
1669 bool fw_coexist_all_off;
1670 bool sw_coexist_all_off;
1671 u32 current_state;
1672 u32 previous_state;
1673 u8 bt_pre_rssi_state;
1674
1675 u8 reg_bt_iso;
1676 u8 reg_bt_sco;
1677
1678 };
1679
1680
1681 /****************************************
1682 mem access macro define start
1683 Call endian free function when
1684 1. Read/write packet content.
1685 2. Before write integer to IO.
1686 3. After read integer from IO.
1687 ****************************************/
1688 /* Convert little data endian to host ordering */
1689 #define EF1BYTE(_val) \
1690 ((u8)(_val))
1691 #define EF2BYTE(_val) \
1692 (le16_to_cpu(_val))
1693 #define EF4BYTE(_val) \
1694 (le32_to_cpu(_val))
1695
1696 /* Read data from memory */
1697 #define READEF1BYTE(_ptr) \
1698 EF1BYTE(*((u8 *)(_ptr)))
1699 /* Read le16 data from memory and convert to host ordering */
1700 #define READEF2BYTE(_ptr) \
1701 EF2BYTE(*((u16 *)(_ptr)))
1702 #define READEF4BYTE(_ptr) \
1703 EF4BYTE(*((u32 *)(_ptr)))
1704
1705 /* Write data to memory */
1706 #define WRITEEF1BYTE(_ptr, _val) \
1707 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1708 /* Write le16 data to memory in host ordering */
1709 #define WRITEEF2BYTE(_ptr, _val) \
1710 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1711 #define WRITEEF4BYTE(_ptr, _val) \
1712 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1713
1714 /* Create a bit mask
1715 * Examples:
1716 * BIT_LEN_MASK_32(0) => 0x00000000
1717 * BIT_LEN_MASK_32(1) => 0x00000001
1718 * BIT_LEN_MASK_32(2) => 0x00000003
1719 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1720 */
1721 #define BIT_LEN_MASK_32(__bitlen) \
1722 (0xFFFFFFFF >> (32 - (__bitlen)))
1723 #define BIT_LEN_MASK_16(__bitlen) \
1724 (0xFFFF >> (16 - (__bitlen)))
1725 #define BIT_LEN_MASK_8(__bitlen) \
1726 (0xFF >> (8 - (__bitlen)))
1727
1728 /* Create an offset bit mask
1729 * Examples:
1730 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1731 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1732 */
1733 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1734 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1735 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1736 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1737 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1738 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1739
1740 /*Description:
1741 * Return 4-byte value in host byte ordering from
1742 * 4-byte pointer in little-endian system.
1743 */
1744 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1745 (EF4BYTE(*((u32 *)(__pstart))))
1746 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1747 (EF2BYTE(*((u16 *)(__pstart))))
1748 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1749 (EF1BYTE(*((u8 *)(__pstart))))
1750
1751 /*Description:
1752 Translate subfield (continuous bits in little-endian) of 4-byte
1753 value to host byte ordering.*/
1754 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1755 ( \
1756 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1757 BIT_LEN_MASK_32(__bitlen) \
1758 )
1759 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1760 ( \
1761 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1762 BIT_LEN_MASK_16(__bitlen) \
1763 )
1764 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1765 ( \
1766 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1767 BIT_LEN_MASK_8(__bitlen) \
1768 )
1769
1770 /* Description:
1771 * Mask subfield (continuous bits in little-endian) of 4-byte value
1772 * and return the result in 4-byte value in host byte ordering.
1773 */
1774 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1775 ( \
1776 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1777 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1778 )
1779 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1780 ( \
1781 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1782 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1783 )
1784 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1785 ( \
1786 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1787 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1788 )
1789
1790 /* Description:
1791 * Set subfield of little-endian 4-byte value to specified value.
1792 */
1793 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1794 *((u32 *)(__pstart)) = EF4BYTE \
1795 ( \
1796 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1797 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1798 );
1799 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1800 *((u16 *)(__pstart)) = EF2BYTE \
1801 ( \
1802 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1803 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1804 );
1805 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1806 *((u8 *)(__pstart)) = EF1BYTE \
1807 ( \
1808 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1809 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1810 );
1811
1812 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1813 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1814
1815 /****************************************
1816 mem access macro define end
1817 ****************************************/
1818
1819 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1820
1821 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1822 #define RTL_WATCH_DOG_TIME 2000
1823 #define MSECS(t) msecs_to_jiffies(t)
1824 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1825 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1826 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1827 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1828 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1829 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1830 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1831
1832 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1833 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1834 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1835 /*NIC halt, re-initialize hw parameters*/
1836 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1837 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1838 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1839 /*Always enable ASPM and Clock Req in initialization.*/
1840 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1841 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1842 #define RT_PS_LEVEL_ASPM BIT(7)
1843 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1844 #define RT_RF_LPS_DISALBE_2R BIT(30)
1845 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1846 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1847 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1848 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1849 (ppsc->cur_ps_level &= (~(_ps_flg)))
1850 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1851 (ppsc->cur_ps_level |= _ps_flg)
1852
1853 #define container_of_dwork_rtl(x, y, z) \
1854 container_of(container_of(x, struct delayed_work, work), y, z)
1855
1856 #define FILL_OCTET_STRING(_os, _octet, _len) \
1857 (_os).octet = (u8 *)(_octet); \
1858 (_os).length = (_len);
1859
1860 #define CP_MACADDR(des, src) \
1861 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1862 (des)[2] = (src)[2], (des)[3] = (src)[3],\
1863 (des)[4] = (src)[4], (des)[5] = (src)[5])
1864
1865 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1866 {
1867 return rtlpriv->io.read8_sync(rtlpriv, addr);
1868 }
1869
1870 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1871 {
1872 return rtlpriv->io.read16_sync(rtlpriv, addr);
1873 }
1874
1875 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1876 {
1877 return rtlpriv->io.read32_sync(rtlpriv, addr);
1878 }
1879
1880 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1881 {
1882 rtlpriv->io.write8_async(rtlpriv, addr, val8);
1883
1884 if (rtlpriv->cfg->write_readback)
1885 rtlpriv->io.read8_sync(rtlpriv, addr);
1886 }
1887
1888 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1889 {
1890 rtlpriv->io.write16_async(rtlpriv, addr, val16);
1891
1892 if (rtlpriv->cfg->write_readback)
1893 rtlpriv->io.read16_sync(rtlpriv, addr);
1894 }
1895
1896 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1897 u32 addr, u32 val32)
1898 {
1899 rtlpriv->io.write32_async(rtlpriv, addr, val32);
1900
1901 if (rtlpriv->cfg->write_readback)
1902 rtlpriv->io.read32_sync(rtlpriv, addr);
1903 }
1904
1905 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1906 u32 regaddr, u32 bitmask)
1907 {
1908 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1909 regaddr,
1910 bitmask);
1911 }
1912
1913 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1914 u32 bitmask, u32 data)
1915 {
1916 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1917 regaddr, bitmask,
1918 data);
1919
1920 }
1921
1922 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1923 enum radio_path rfpath, u32 regaddr,
1924 u32 bitmask)
1925 {
1926 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1927 rfpath,
1928 regaddr,
1929 bitmask);
1930 }
1931
1932 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1933 enum radio_path rfpath, u32 regaddr,
1934 u32 bitmask, u32 data)
1935 {
1936 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1937 rfpath, regaddr,
1938 bitmask, data);
1939 }
1940
1941 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1942 {
1943 return (_HAL_STATE_STOP == rtlhal->state);
1944 }
1945
1946 static inline void set_hal_start(struct rtl_hal *rtlhal)
1947 {
1948 rtlhal->state = _HAL_STATE_START;
1949 }
1950
1951 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1952 {
1953 rtlhal->state = _HAL_STATE_STOP;
1954 }
1955
1956 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1957 {
1958 return rtlphy->rf_type;
1959 }
1960
1961 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
1962 {
1963 return (struct ieee80211_hdr *)(skb->data);
1964 }
1965
1966 static inline u16 rtl_get_fc(struct sk_buff *skb)
1967 {
1968 return le16_to_cpu(rtl_get_hdr(skb)->frame_control);
1969 }
1970
1971 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
1972 {
1973 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
1974 }
1975
1976 static inline u16 rtl_get_tid(struct sk_buff *skb)
1977 {
1978 return rtl_get_tid_h(rtl_get_hdr(skb));
1979 }
1980
1981 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
1982 struct ieee80211_vif *vif,
1983 u8 *bssid)
1984 {
1985 return ieee80211_find_sta(vif, bssid);
1986 }
1987
1988 #endif
Linux with added FPC-III support