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drm/nouveau/fb: add gm20b device
[linux/fpc-iii.git] / drivers / gpu / drm / exynos / exynos_drm_dsi.c
blobe07cb1fe4860440596debe0636877afe968d4470
1 /*
2 * Samsung SoC MIPI DSI Master driver.
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
5 *
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <asm/unaligned.h>
14
15 #include <drm/drmP.h>
16 #include <drm/drm_crtc_helper.h>
17 #include <drm/drm_mipi_dsi.h>
18 #include <drm/drm_panel.h>
19 #include <drm/drm_atomic_helper.h>
20
21 #include <linux/clk.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/irq.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/of_graph.h>
27 #include <linux/phy/phy.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/component.h>
30
31 #include <video/mipi_display.h>
32 #include <video/videomode.h>
33
34 #include "exynos_drm_crtc.h"
35 #include "exynos_drm_drv.h"
36
37 /* returns true iff both arguments logically differs */
38 #define NEQV(a, b) (!(a) ^ !(b))
39
40 /* DSIM_STATUS */
41 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
42 #define DSIM_STOP_STATE_CLK (1 << 8)
43 #define DSIM_TX_READY_HS_CLK (1 << 10)
44 #define DSIM_PLL_STABLE (1 << 31)
45
46 /* DSIM_SWRST */
47 #define DSIM_FUNCRST (1 << 16)
48 #define DSIM_SWRST (1 << 0)
49
50 /* DSIM_TIMEOUT */
51 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
52 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
53
54 /* DSIM_CLKCTRL */
55 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
56 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
57 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
58 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
59 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
60 #define DSIM_BYTE_CLKEN (1 << 24)
61 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
62 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
63 #define DSIM_PLL_BYPASS (1 << 27)
64 #define DSIM_ESC_CLKEN (1 << 28)
65 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
66
67 /* DSIM_CONFIG */
68 #define DSIM_LANE_EN_CLK (1 << 0)
69 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
70 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
71 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
72 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
73 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
74 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
75 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
76 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
77 #define DSIM_SUB_VC (((x) & 0x3) << 16)
78 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
79 #define DSIM_HSA_MODE (1 << 20)
80 #define DSIM_HBP_MODE (1 << 21)
81 #define DSIM_HFP_MODE (1 << 22)
82 #define DSIM_HSE_MODE (1 << 23)
83 #define DSIM_AUTO_MODE (1 << 24)
84 #define DSIM_VIDEO_MODE (1 << 25)
85 #define DSIM_BURST_MODE (1 << 26)
86 #define DSIM_SYNC_INFORM (1 << 27)
87 #define DSIM_EOT_DISABLE (1 << 28)
88 #define DSIM_MFLUSH_VS (1 << 29)
89 /* This flag is valid only for exynos3250/3472/4415/5260/5430 */
90 #define DSIM_CLKLANE_STOP (1 << 30)
91
92 /* DSIM_ESCMODE */
93 #define DSIM_TX_TRIGGER_RST (1 << 4)
94 #define DSIM_TX_LPDT_LP (1 << 6)
95 #define DSIM_CMD_LPDT_LP (1 << 7)
96 #define DSIM_FORCE_BTA (1 << 16)
97 #define DSIM_FORCE_STOP_STATE (1 << 20)
98 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
99 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
100
101 /* DSIM_MDRESOL */
102 #define DSIM_MAIN_STAND_BY (1 << 31)
103 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
104 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
105
106 /* DSIM_MVPORCH */
107 #define DSIM_CMD_ALLOW(x) ((x) << 28)
108 #define DSIM_STABLE_VFP(x) ((x) << 16)
109 #define DSIM_MAIN_VBP(x) ((x) << 0)
110 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
111 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
112 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
113
114 /* DSIM_MHPORCH */
115 #define DSIM_MAIN_HFP(x) ((x) << 16)
116 #define DSIM_MAIN_HBP(x) ((x) << 0)
117 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
118 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
119
120 /* DSIM_MSYNC */
121 #define DSIM_MAIN_VSA(x) ((x) << 22)
122 #define DSIM_MAIN_HSA(x) ((x) << 0)
123 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
124 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
125
126 /* DSIM_SDRESOL */
127 #define DSIM_SUB_STANDY(x) ((x) << 31)
128 #define DSIM_SUB_VRESOL(x) ((x) << 16)
129 #define DSIM_SUB_HRESOL(x) ((x) << 0)
130 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
131 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
132 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
133
134 /* DSIM_INTSRC */
135 #define DSIM_INT_PLL_STABLE (1 << 31)
136 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
137 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
138 #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28)
139 #define DSIM_INT_BTA (1 << 25)
140 #define DSIM_INT_FRAME_DONE (1 << 24)
141 #define DSIM_INT_RX_TIMEOUT (1 << 21)
142 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
143 #define DSIM_INT_RX_DONE (1 << 18)
144 #define DSIM_INT_RX_TE (1 << 17)
145 #define DSIM_INT_RX_ACK (1 << 16)
146 #define DSIM_INT_RX_ECC_ERR (1 << 15)
147 #define DSIM_INT_RX_CRC_ERR (1 << 14)
148
149 /* DSIM_FIFOCTRL */
150 #define DSIM_RX_DATA_FULL (1 << 25)
151 #define DSIM_RX_DATA_EMPTY (1 << 24)
152 #define DSIM_SFR_HEADER_FULL (1 << 23)
153 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
154 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
155 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
156 #define DSIM_I80_HEADER_FULL (1 << 19)
157 #define DSIM_I80_HEADER_EMPTY (1 << 18)
158 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
159 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
160 #define DSIM_SD_HEADER_FULL (1 << 15)
161 #define DSIM_SD_HEADER_EMPTY (1 << 14)
162 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
163 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
164 #define DSIM_MD_HEADER_FULL (1 << 11)
165 #define DSIM_MD_HEADER_EMPTY (1 << 10)
166 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
167 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
168 #define DSIM_RX_FIFO (1 << 4)
169 #define DSIM_SFR_FIFO (1 << 3)
170 #define DSIM_I80_FIFO (1 << 2)
171 #define DSIM_SD_FIFO (1 << 1)
172 #define DSIM_MD_FIFO (1 << 0)
173
174 /* DSIM_PHYACCHR */
175 #define DSIM_AFC_EN (1 << 14)
176 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
177
178 /* DSIM_PLLCTRL */
179 #define DSIM_FREQ_BAND(x) ((x) << 24)
180 #define DSIM_PLL_EN (1 << 23)
181 #define DSIM_PLL_P(x) ((x) << 13)
182 #define DSIM_PLL_M(x) ((x) << 4)
183 #define DSIM_PLL_S(x) ((x) << 1)
184
185 /* DSIM_PHYCTRL */
186 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
187 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30)
188 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14)
189
190 /* DSIM_PHYTIMING */
191 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
192 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
193
194 /* DSIM_PHYTIMING1 */
195 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
196 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
197 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
198 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
199
200 /* DSIM_PHYTIMING2 */
201 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
202 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
203 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
204
205 #define DSI_MAX_BUS_WIDTH 4
206 #define DSI_NUM_VIRTUAL_CHANNELS 4
207 #define DSI_TX_FIFO_SIZE 2048
208 #define DSI_RX_FIFO_SIZE 256
209 #define DSI_XFER_TIMEOUT_MS 100
210 #define DSI_RX_FIFO_EMPTY 0x30800002
211
212 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
213
214 static char *clk_names[5] = { "bus_clk", "sclk_mipi",
215 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
216 "sclk_rgb_vclk_to_dsim0" };
217
218 enum exynos_dsi_transfer_type {
219 EXYNOS_DSI_TX,
220 EXYNOS_DSI_RX,
221 };
222
223 struct exynos_dsi_transfer {
224 struct list_head list;
225 struct completion completed;
226 int result;
227 struct mipi_dsi_packet packet;
228 u16 flags;
229 u16 tx_done;
230
231 u8 *rx_payload;
232 u16 rx_len;
233 u16 rx_done;
234 };
235
236 #define DSIM_STATE_ENABLED BIT(0)
237 #define DSIM_STATE_INITIALIZED BIT(1)
238 #define DSIM_STATE_CMD_LPM BIT(2)
239 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
240
241 struct exynos_dsi_driver_data {
242 const unsigned int *reg_ofs;
243 unsigned int plltmr_reg;
244 unsigned int has_freqband:1;
245 unsigned int has_clklane_stop:1;
246 unsigned int num_clks;
247 unsigned int max_freq;
248 unsigned int wait_for_reset;
249 unsigned int num_bits_resol;
250 const unsigned int *reg_values;
251 };
252
253 struct exynos_dsi {
254 struct drm_encoder encoder;
255 struct mipi_dsi_host dsi_host;
256 struct drm_connector connector;
257 struct device_node *panel_node;
258 struct drm_panel *panel;
259 struct device *dev;
260
261 void __iomem *reg_base;
262 struct phy *phy;
263 struct clk **clks;
264 struct regulator_bulk_data supplies[2];
265 int irq;
266 int te_gpio;
267
268 u32 pll_clk_rate;
269 u32 burst_clk_rate;
270 u32 esc_clk_rate;
271 u32 lanes;
272 u32 mode_flags;
273 u32 format;
274 struct videomode vm;
275
276 int state;
277 struct drm_property *brightness;
278 struct completion completed;
279
280 spinlock_t transfer_lock; /* protects transfer_list */
281 struct list_head transfer_list;
282
283 const struct exynos_dsi_driver_data *driver_data;
284 struct device_node *bridge_node;
285 };
286
287 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
288 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
289
290 static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
291 {
292 return container_of(e, struct exynos_dsi, encoder);
293 }
294
295 enum reg_idx {
296 DSIM_STATUS_REG, /* Status register */
297 DSIM_SWRST_REG, /* Software reset register */
298 DSIM_CLKCTRL_REG, /* Clock control register */
299 DSIM_TIMEOUT_REG, /* Time out register */
300 DSIM_CONFIG_REG, /* Configuration register */
301 DSIM_ESCMODE_REG, /* Escape mode register */
302 DSIM_MDRESOL_REG,
303 DSIM_MVPORCH_REG, /* Main display Vporch register */
304 DSIM_MHPORCH_REG, /* Main display Hporch register */
305 DSIM_MSYNC_REG, /* Main display sync area register */
306 DSIM_INTSRC_REG, /* Interrupt source register */
307 DSIM_INTMSK_REG, /* Interrupt mask register */
308 DSIM_PKTHDR_REG, /* Packet Header FIFO register */
309 DSIM_PAYLOAD_REG, /* Payload FIFO register */
310 DSIM_RXFIFO_REG, /* Read FIFO register */
311 DSIM_FIFOCTRL_REG, /* FIFO status and control register */
312 DSIM_PLLCTRL_REG, /* PLL control register */
313 DSIM_PHYCTRL_REG,
314 DSIM_PHYTIMING_REG,
315 DSIM_PHYTIMING1_REG,
316 DSIM_PHYTIMING2_REG,
317 NUM_REGS
318 };
319
320 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
321 u32 val)
322 {
323
324 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
325 }
326
327 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
328 {
329 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
330 }
331
332 static const unsigned int exynos_reg_ofs[] = {
333 [DSIM_STATUS_REG] = 0x00,
334 [DSIM_SWRST_REG] = 0x04,
335 [DSIM_CLKCTRL_REG] = 0x08,
336 [DSIM_TIMEOUT_REG] = 0x0c,
337 [DSIM_CONFIG_REG] = 0x10,
338 [DSIM_ESCMODE_REG] = 0x14,
339 [DSIM_MDRESOL_REG] = 0x18,
340 [DSIM_MVPORCH_REG] = 0x1c,
341 [DSIM_MHPORCH_REG] = 0x20,
342 [DSIM_MSYNC_REG] = 0x24,
343 [DSIM_INTSRC_REG] = 0x2c,
344 [DSIM_INTMSK_REG] = 0x30,
345 [DSIM_PKTHDR_REG] = 0x34,
346 [DSIM_PAYLOAD_REG] = 0x38,
347 [DSIM_RXFIFO_REG] = 0x3c,
348 [DSIM_FIFOCTRL_REG] = 0x44,
349 [DSIM_PLLCTRL_REG] = 0x4c,
350 [DSIM_PHYCTRL_REG] = 0x5c,
351 [DSIM_PHYTIMING_REG] = 0x64,
352 [DSIM_PHYTIMING1_REG] = 0x68,
353 [DSIM_PHYTIMING2_REG] = 0x6c,
354 };
355
356 static const unsigned int exynos5433_reg_ofs[] = {
357 [DSIM_STATUS_REG] = 0x04,
358 [DSIM_SWRST_REG] = 0x0C,
359 [DSIM_CLKCTRL_REG] = 0x10,
360 [DSIM_TIMEOUT_REG] = 0x14,
361 [DSIM_CONFIG_REG] = 0x18,
362 [DSIM_ESCMODE_REG] = 0x1C,
363 [DSIM_MDRESOL_REG] = 0x20,
364 [DSIM_MVPORCH_REG] = 0x24,
365 [DSIM_MHPORCH_REG] = 0x28,
366 [DSIM_MSYNC_REG] = 0x2C,
367 [DSIM_INTSRC_REG] = 0x34,
368 [DSIM_INTMSK_REG] = 0x38,
369 [DSIM_PKTHDR_REG] = 0x3C,
370 [DSIM_PAYLOAD_REG] = 0x40,
371 [DSIM_RXFIFO_REG] = 0x44,
372 [DSIM_FIFOCTRL_REG] = 0x4C,
373 [DSIM_PLLCTRL_REG] = 0x94,
374 [DSIM_PHYCTRL_REG] = 0xA4,
375 [DSIM_PHYTIMING_REG] = 0xB4,
376 [DSIM_PHYTIMING1_REG] = 0xB8,
377 [DSIM_PHYTIMING2_REG] = 0xBC,
378 };
379
380 enum reg_value_idx {
381 RESET_TYPE,
382 PLL_TIMER,
383 STOP_STATE_CNT,
384 PHYCTRL_ULPS_EXIT,
385 PHYCTRL_VREG_LP,
386 PHYCTRL_SLEW_UP,
387 PHYTIMING_LPX,
388 PHYTIMING_HS_EXIT,
389 PHYTIMING_CLK_PREPARE,
390 PHYTIMING_CLK_ZERO,
391 PHYTIMING_CLK_POST,
392 PHYTIMING_CLK_TRAIL,
393 PHYTIMING_HS_PREPARE,
394 PHYTIMING_HS_ZERO,
395 PHYTIMING_HS_TRAIL
396 };
397
398 static const unsigned int reg_values[] = {
399 [RESET_TYPE] = DSIM_SWRST,
400 [PLL_TIMER] = 500,
401 [STOP_STATE_CNT] = 0xf,
402 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
403 [PHYCTRL_VREG_LP] = 0,
404 [PHYCTRL_SLEW_UP] = 0,
405 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
406 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
407 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
408 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
409 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
410 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
411 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
412 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
413 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
414 };
415
416 static const unsigned int exynos5422_reg_values[] = {
417 [RESET_TYPE] = DSIM_SWRST,
418 [PLL_TIMER] = 500,
419 [STOP_STATE_CNT] = 0xf,
420 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
421 [PHYCTRL_VREG_LP] = 0,
422 [PHYCTRL_SLEW_UP] = 0,
423 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
424 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
425 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
426 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
427 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
428 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
429 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
430 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
431 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
432 };
433
434 static const unsigned int exynos5433_reg_values[] = {
435 [RESET_TYPE] = DSIM_FUNCRST,
436 [PLL_TIMER] = 22200,
437 [STOP_STATE_CNT] = 0xa,
438 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
439 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
440 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
441 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
442 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
443 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
444 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
445 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
446 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
447 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
448 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
449 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
450 };
451
452 static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
453 .reg_ofs = exynos_reg_ofs,
454 .plltmr_reg = 0x50,
455 .has_freqband = 1,
456 .has_clklane_stop = 1,
457 .num_clks = 2,
458 .max_freq = 1000,
459 .wait_for_reset = 1,
460 .num_bits_resol = 11,
461 .reg_values = reg_values,
462 };
463
464 static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
465 .reg_ofs = exynos_reg_ofs,
466 .plltmr_reg = 0x50,
467 .has_freqband = 1,
468 .has_clklane_stop = 1,
469 .num_clks = 2,
470 .max_freq = 1000,
471 .wait_for_reset = 1,
472 .num_bits_resol = 11,
473 .reg_values = reg_values,
474 };
475
476 static const struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
477 .reg_ofs = exynos_reg_ofs,
478 .plltmr_reg = 0x58,
479 .has_clklane_stop = 1,
480 .num_clks = 2,
481 .max_freq = 1000,
482 .wait_for_reset = 1,
483 .num_bits_resol = 11,
484 .reg_values = reg_values,
485 };
486
487 static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
488 .reg_ofs = exynos_reg_ofs,
489 .plltmr_reg = 0x58,
490 .num_clks = 2,
491 .max_freq = 1000,
492 .wait_for_reset = 1,
493 .num_bits_resol = 11,
494 .reg_values = reg_values,
495 };
496
497 static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
498 .reg_ofs = exynos5433_reg_ofs,
499 .plltmr_reg = 0xa0,
500 .has_clklane_stop = 1,
501 .num_clks = 5,
502 .max_freq = 1500,
503 .wait_for_reset = 0,
504 .num_bits_resol = 12,
505 .reg_values = exynos5433_reg_values,
506 };
507
508 static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
509 .reg_ofs = exynos5433_reg_ofs,
510 .plltmr_reg = 0xa0,
511 .has_clklane_stop = 1,
512 .num_clks = 2,
513 .max_freq = 1500,
514 .wait_for_reset = 1,
515 .num_bits_resol = 12,
516 .reg_values = exynos5422_reg_values,
517 };
518
519 static const struct of_device_id exynos_dsi_of_match[] = {
520 { .compatible = "samsung,exynos3250-mipi-dsi",
521 .data = &exynos3_dsi_driver_data },
522 { .compatible = "samsung,exynos4210-mipi-dsi",
523 .data = &exynos4_dsi_driver_data },
524 { .compatible = "samsung,exynos4415-mipi-dsi",
525 .data = &exynos4415_dsi_driver_data },
526 { .compatible = "samsung,exynos5410-mipi-dsi",
527 .data = &exynos5_dsi_driver_data },
528 { .compatible = "samsung,exynos5422-mipi-dsi",
529 .data = &exynos5422_dsi_driver_data },
530 { .compatible = "samsung,exynos5433-mipi-dsi",
531 .data = &exynos5433_dsi_driver_data },
532 { }
533 };
534
535 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
536 {
537 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
538 return;
539
540 dev_err(dsi->dev, "timeout waiting for reset\n");
541 }
542
543 static void exynos_dsi_reset(struct exynos_dsi *dsi)
544 {
545 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
546
547 reinit_completion(&dsi->completed);
548 exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
549 }
550
551 #ifndef MHZ
552 #define MHZ (1000*1000)
553 #endif
554
555 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
556 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
557 {
558 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
559 unsigned long best_freq = 0;
560 u32 min_delta = 0xffffffff;
561 u8 p_min, p_max;
562 u8 _p, uninitialized_var(best_p);
563 u16 _m, uninitialized_var(best_m);
564 u8 _s, uninitialized_var(best_s);
565
566 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
567 p_max = fin / (6 * MHZ);
568
569 for (_p = p_min; _p <= p_max; ++_p) {
570 for (_s = 0; _s <= 5; ++_s) {
571 u64 tmp;
572 u32 delta;
573
574 tmp = (u64)fout * (_p << _s);
575 do_div(tmp, fin);
576 _m = tmp;
577 if (_m < 41 || _m > 125)
578 continue;
579
580 tmp = (u64)_m * fin;
581 do_div(tmp, _p);
582 if (tmp < 500 * MHZ ||
583 tmp > driver_data->max_freq * MHZ)
584 continue;
585
586 tmp = (u64)_m * fin;
587 do_div(tmp, _p << _s);
588
589 delta = abs(fout - tmp);
590 if (delta < min_delta) {
591 best_p = _p;
592 best_m = _m;
593 best_s = _s;
594 min_delta = delta;
595 best_freq = tmp;
596 }
597 }
598 }
599
600 if (best_freq) {
601 *p = best_p;
602 *m = best_m;
603 *s = best_s;
604 }
605
606 return best_freq;
607 }
608
609 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
610 unsigned long freq)
611 {
612 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
613 unsigned long fin, fout;
614 int timeout;
615 u8 p, s;
616 u16 m;
617 u32 reg;
618
619 fin = dsi->pll_clk_rate;
620 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
621 if (!fout) {
622 dev_err(dsi->dev,
623 "failed to find PLL PMS for requested frequency\n");
624 return 0;
625 }
626 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
627
628 writel(driver_data->reg_values[PLL_TIMER],
629 dsi->reg_base + driver_data->plltmr_reg);
630
631 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
632
633 if (driver_data->has_freqband) {
634 static const unsigned long freq_bands[] = {
635 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
636 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
637 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
638 770 * MHZ, 870 * MHZ, 950 * MHZ,
639 };
640 int band;
641
642 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
643 if (fout < freq_bands[band])
644 break;
645
646 dev_dbg(dsi->dev, "band %d\n", band);
647
648 reg |= DSIM_FREQ_BAND(band);
649 }
650
651 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
652
653 timeout = 1000;
654 do {
655 if (timeout-- == 0) {
656 dev_err(dsi->dev, "PLL failed to stabilize\n");
657 return 0;
658 }
659 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
660 } while ((reg & DSIM_PLL_STABLE) == 0);
661
662 return fout;
663 }
664
665 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
666 {
667 unsigned long hs_clk, byte_clk, esc_clk;
668 unsigned long esc_div;
669 u32 reg;
670
671 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
672 if (!hs_clk) {
673 dev_err(dsi->dev, "failed to configure DSI PLL\n");
674 return -EFAULT;
675 }
676
677 byte_clk = hs_clk / 8;
678 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
679 esc_clk = byte_clk / esc_div;
680
681 if (esc_clk > 20 * MHZ) {
682 ++esc_div;
683 esc_clk = byte_clk / esc_div;
684 }
685
686 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
687 hs_clk, byte_clk, esc_clk);
688
689 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
690 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
691 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
692 | DSIM_BYTE_CLK_SRC_MASK);
693 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
694 | DSIM_ESC_PRESCALER(esc_div)
695 | DSIM_LANE_ESC_CLK_EN_CLK
696 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
697 | DSIM_BYTE_CLK_SRC(0)
698 | DSIM_TX_REQUEST_HSCLK;
699 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
700
701 return 0;
702 }
703
704 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
705 {
706 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
707 const unsigned int *reg_values = driver_data->reg_values;
708 u32 reg;
709
710 if (driver_data->has_freqband)
711 return;
712
713 /* B D-PHY: D-PHY Master & Slave Analog Block control */
714 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
715 reg_values[PHYCTRL_SLEW_UP];
716 exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
717
718 /*
719 * T LPX: Transmitted length of any Low-Power state period
720 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
721 * burst
722 */
723 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
724 exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
725
726 /*
727 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
728 * Line state immediately before the HS-0 Line state starting the
729 * HS transmission
730 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
731 * transmitting the Clock.
732 * T CLK_POST: Time that the transmitter continues to send HS clock
733 * after the last associated Data Lane has transitioned to LP Mode
734 * Interval is defined as the period from the end of T HS-TRAIL to
735 * the beginning of T CLK-TRAIL
736 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
737 * the last payload clock bit of a HS transmission burst
738 */
739 reg = reg_values[PHYTIMING_CLK_PREPARE] |
740 reg_values[PHYTIMING_CLK_ZERO] |
741 reg_values[PHYTIMING_CLK_POST] |
742 reg_values[PHYTIMING_CLK_TRAIL];
743
744 exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
745
746 /*
747 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
748 * Line state immediately before the HS-0 Line state starting the
749 * HS transmission
750 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
751 * transmitting the Sync sequence.
752 * T HS-TRAIL: Time that the transmitter drives the flipped differential
753 * state after last payload data bit of a HS transmission burst
754 */
755 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
756 reg_values[PHYTIMING_HS_TRAIL];
757 exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
758 }
759
760 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
761 {
762 u32 reg;
763
764 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
765 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
766 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
767 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
768
769 reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
770 reg &= ~DSIM_PLL_EN;
771 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
772 }
773
774 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
775 {
776 u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
777 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
778 DSIM_LANE_EN(lane));
779 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
780 }
781
782 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
783 {
784 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
785 int timeout;
786 u32 reg;
787 u32 lanes_mask;
788
789 /* Initialize FIFO pointers */
790 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
791 reg &= ~0x1f;
792 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
793
794 usleep_range(9000, 11000);
795
796 reg |= 0x1f;
797 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
798 usleep_range(9000, 11000);
799
800 /* DSI configuration */
801 reg = 0;
802
803 /*
804 * The first bit of mode_flags specifies display configuration.
805 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
806 * mode, otherwise it will support command mode.
807 */
808 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
809 reg |= DSIM_VIDEO_MODE;
810
811 /*
812 * The user manual describes that following bits are ignored in
813 * command mode.
814 */
815 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
816 reg |= DSIM_MFLUSH_VS;
817 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
818 reg |= DSIM_SYNC_INFORM;
819 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
820 reg |= DSIM_BURST_MODE;
821 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
822 reg |= DSIM_AUTO_MODE;
823 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
824 reg |= DSIM_HSE_MODE;
825 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
826 reg |= DSIM_HFP_MODE;
827 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
828 reg |= DSIM_HBP_MODE;
829 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
830 reg |= DSIM_HSA_MODE;
831 }
832
833 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
834 reg |= DSIM_EOT_DISABLE;
835
836 switch (dsi->format) {
837 case MIPI_DSI_FMT_RGB888:
838 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
839 break;
840 case MIPI_DSI_FMT_RGB666:
841 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
842 break;
843 case MIPI_DSI_FMT_RGB666_PACKED:
844 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
845 break;
846 case MIPI_DSI_FMT_RGB565:
847 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
848 break;
849 default:
850 dev_err(dsi->dev, "invalid pixel format\n");
851 return -EINVAL;
852 }
853
854 /*
855 * Use non-continuous clock mode if the periparal wants and
856 * host controller supports
857 *
858 * In non-continous clock mode, host controller will turn off
859 * the HS clock between high-speed transmissions to reduce
860 * power consumption.
861 */
862 if (driver_data->has_clklane_stop &&
863 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
864 reg |= DSIM_CLKLANE_STOP;
865 }
866 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
867
868 lanes_mask = BIT(dsi->lanes) - 1;
869 exynos_dsi_enable_lane(dsi, lanes_mask);
870
871 /* Check clock and data lane state are stop state */
872 timeout = 100;
873 do {
874 if (timeout-- == 0) {
875 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
876 return -EFAULT;
877 }
878
879 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
880 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
881 != DSIM_STOP_STATE_DAT(lanes_mask))
882 continue;
883 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
884
885 reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
886 reg &= ~DSIM_STOP_STATE_CNT_MASK;
887 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
888 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
889
890 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
891 exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
892
893 return 0;
894 }
895
896 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
897 {
898 struct videomode *vm = &dsi->vm;
899 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
900 u32 reg;
901
902 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
903 reg = DSIM_CMD_ALLOW(0xf)
904 | DSIM_STABLE_VFP(vm->vfront_porch)
905 | DSIM_MAIN_VBP(vm->vback_porch);
906 exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
907
908 reg = DSIM_MAIN_HFP(vm->hfront_porch)
909 | DSIM_MAIN_HBP(vm->hback_porch);
910 exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
911
912 reg = DSIM_MAIN_VSA(vm->vsync_len)
913 | DSIM_MAIN_HSA(vm->hsync_len);
914 exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
915 }
916 reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) |
917 DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol);
918
919 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
920
921 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
922 }
923
924 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
925 {
926 u32 reg;
927
928 reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
929 if (enable)
930 reg |= DSIM_MAIN_STAND_BY;
931 else
932 reg &= ~DSIM_MAIN_STAND_BY;
933 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
934 }
935
936 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
937 {
938 int timeout = 2000;
939
940 do {
941 u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
942
943 if (!(reg & DSIM_SFR_HEADER_FULL))
944 return 0;
945
946 if (!cond_resched())
947 usleep_range(950, 1050);
948 } while (--timeout);
949
950 return -ETIMEDOUT;
951 }
952
953 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
954 {
955 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
956
957 if (lpm)
958 v |= DSIM_CMD_LPDT_LP;
959 else
960 v &= ~DSIM_CMD_LPDT_LP;
961
962 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
963 }
964
965 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
966 {
967 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
968 v |= DSIM_FORCE_BTA;
969 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
970 }
971
972 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
973 struct exynos_dsi_transfer *xfer)
974 {
975 struct device *dev = dsi->dev;
976 struct mipi_dsi_packet *pkt = &xfer->packet;
977 const u8 *payload = pkt->payload + xfer->tx_done;
978 u16 length = pkt->payload_length - xfer->tx_done;
979 bool first = !xfer->tx_done;
980 u32 reg;
981
982 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
983 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
984
985 if (length > DSI_TX_FIFO_SIZE)
986 length = DSI_TX_FIFO_SIZE;
987
988 xfer->tx_done += length;
989
990 /* Send payload */
991 while (length >= 4) {
992 reg = get_unaligned_le32(payload);
993 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
994 payload += 4;
995 length -= 4;
996 }
997
998 reg = 0;
999 switch (length) {
1000 case 3:
1001 reg |= payload[2] << 16;
1002 /* Fall through */
1003 case 2:
1004 reg |= payload[1] << 8;
1005 /* Fall through */
1006 case 1:
1007 reg |= payload[0];
1008 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
1009 break;
1010 }
1011
1012 /* Send packet header */
1013 if (!first)
1014 return;
1015
1016 reg = get_unaligned_le32(pkt->header);
1017 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
1018 dev_err(dev, "waiting for header FIFO timed out\n");
1019 return;
1020 }
1021
1022 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1023 dsi->state & DSIM_STATE_CMD_LPM)) {
1024 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1025 dsi->state ^= DSIM_STATE_CMD_LPM;
1026 }
1027
1028 exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
1029
1030 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1031 exynos_dsi_force_bta(dsi);
1032 }
1033
1034 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
1035 struct exynos_dsi_transfer *xfer)
1036 {
1037 u8 *payload = xfer->rx_payload + xfer->rx_done;
1038 bool first = !xfer->rx_done;
1039 struct device *dev = dsi->dev;
1040 u16 length;
1041 u32 reg;
1042
1043 if (first) {
1044 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1045
1046 switch (reg & 0x3f) {
1047 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1048 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1049 if (xfer->rx_len >= 2) {
1050 payload[1] = reg >> 16;
1051 ++xfer->rx_done;
1052 }
1053 /* Fall through */
1054 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1055 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1056 payload[0] = reg >> 8;
1057 ++xfer->rx_done;
1058 xfer->rx_len = xfer->rx_done;
1059 xfer->result = 0;
1060 goto clear_fifo;
1061 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1062 dev_err(dev, "DSI Error Report: 0x%04x\n",
1063 (reg >> 8) & 0xffff);
1064 xfer->result = 0;
1065 goto clear_fifo;
1066 }
1067
1068 length = (reg >> 8) & 0xffff;
1069 if (length > xfer->rx_len) {
1070 dev_err(dev,
1071 "response too long (%u > %u bytes), stripping\n",
1072 xfer->rx_len, length);
1073 length = xfer->rx_len;
1074 } else if (length < xfer->rx_len)
1075 xfer->rx_len = length;
1076 }
1077
1078 length = xfer->rx_len - xfer->rx_done;
1079 xfer->rx_done += length;
1080
1081 /* Receive payload */
1082 while (length >= 4) {
1083 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1084 payload[0] = (reg >> 0) & 0xff;
1085 payload[1] = (reg >> 8) & 0xff;
1086 payload[2] = (reg >> 16) & 0xff;
1087 payload[3] = (reg >> 24) & 0xff;
1088 payload += 4;
1089 length -= 4;
1090 }
1091
1092 if (length) {
1093 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1094 switch (length) {
1095 case 3:
1096 payload[2] = (reg >> 16) & 0xff;
1097 /* Fall through */
1098 case 2:
1099 payload[1] = (reg >> 8) & 0xff;
1100 /* Fall through */
1101 case 1:
1102 payload[0] = reg & 0xff;
1103 }
1104 }
1105
1106 if (xfer->rx_done == xfer->rx_len)
1107 xfer->result = 0;
1108
1109 clear_fifo:
1110 length = DSI_RX_FIFO_SIZE / 4;
1111 do {
1112 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1113 if (reg == DSI_RX_FIFO_EMPTY)
1114 break;
1115 } while (--length);
1116 }
1117
1118 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1119 {
1120 unsigned long flags;
1121 struct exynos_dsi_transfer *xfer;
1122 bool start = false;
1123
1124 again:
1125 spin_lock_irqsave(&dsi->transfer_lock, flags);
1126
1127 if (list_empty(&dsi->transfer_list)) {
1128 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1129 return;
1130 }
1131
1132 xfer = list_first_entry(&dsi->transfer_list,
1133 struct exynos_dsi_transfer, list);
1134
1135 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1136
1137 if (xfer->packet.payload_length &&
1138 xfer->tx_done == xfer->packet.payload_length)
1139 /* waiting for RX */
1140 return;
1141
1142 exynos_dsi_send_to_fifo(dsi, xfer);
1143
1144 if (xfer->packet.payload_length || xfer->rx_len)
1145 return;
1146
1147 xfer->result = 0;
1148 complete(&xfer->completed);
1149
1150 spin_lock_irqsave(&dsi->transfer_lock, flags);
1151
1152 list_del_init(&xfer->list);
1153 start = !list_empty(&dsi->transfer_list);
1154
1155 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1156
1157 if (start)
1158 goto again;
1159 }
1160
1161 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1162 {
1163 struct exynos_dsi_transfer *xfer;
1164 unsigned long flags;
1165 bool start = true;
1166
1167 spin_lock_irqsave(&dsi->transfer_lock, flags);
1168
1169 if (list_empty(&dsi->transfer_list)) {
1170 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1171 return false;
1172 }
1173
1174 xfer = list_first_entry(&dsi->transfer_list,
1175 struct exynos_dsi_transfer, list);
1176
1177 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1178
1179 dev_dbg(dsi->dev,
1180 "> xfer %p, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1181 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1182 xfer->rx_done);
1183
1184 if (xfer->tx_done != xfer->packet.payload_length)
1185 return true;
1186
1187 if (xfer->rx_done != xfer->rx_len)
1188 exynos_dsi_read_from_fifo(dsi, xfer);
1189
1190 if (xfer->rx_done != xfer->rx_len)
1191 return true;
1192
1193 spin_lock_irqsave(&dsi->transfer_lock, flags);
1194
1195 list_del_init(&xfer->list);
1196 start = !list_empty(&dsi->transfer_list);
1197
1198 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1199
1200 if (!xfer->rx_len)
1201 xfer->result = 0;
1202 complete(&xfer->completed);
1203
1204 return start;
1205 }
1206
1207 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1208 struct exynos_dsi_transfer *xfer)
1209 {
1210 unsigned long flags;
1211 bool start;
1212
1213 spin_lock_irqsave(&dsi->transfer_lock, flags);
1214
1215 if (!list_empty(&dsi->transfer_list) &&
1216 xfer == list_first_entry(&dsi->transfer_list,
1217 struct exynos_dsi_transfer, list)) {
1218 list_del_init(&xfer->list);
1219 start = !list_empty(&dsi->transfer_list);
1220 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1221 if (start)
1222 exynos_dsi_transfer_start(dsi);
1223 return;
1224 }
1225
1226 list_del_init(&xfer->list);
1227
1228 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1229 }
1230
1231 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1232 struct exynos_dsi_transfer *xfer)
1233 {
1234 unsigned long flags;
1235 bool stopped;
1236
1237 xfer->tx_done = 0;
1238 xfer->rx_done = 0;
1239 xfer->result = -ETIMEDOUT;
1240 init_completion(&xfer->completed);
1241
1242 spin_lock_irqsave(&dsi->transfer_lock, flags);
1243
1244 stopped = list_empty(&dsi->transfer_list);
1245 list_add_tail(&xfer->list, &dsi->transfer_list);
1246
1247 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1248
1249 if (stopped)
1250 exynos_dsi_transfer_start(dsi);
1251
1252 wait_for_completion_timeout(&xfer->completed,
1253 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1254 if (xfer->result == -ETIMEDOUT) {
1255 struct mipi_dsi_packet *pkt = &xfer->packet;
1256 exynos_dsi_remove_transfer(dsi, xfer);
1257 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1258 (int)pkt->payload_length, pkt->payload);
1259 return -ETIMEDOUT;
1260 }
1261
1262 /* Also covers hardware timeout condition */
1263 return xfer->result;
1264 }
1265
1266 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1267 {
1268 struct exynos_dsi *dsi = dev_id;
1269 u32 status;
1270
1271 status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
1272 if (!status) {
1273 static unsigned long int j;
1274 if (printk_timed_ratelimit(&j, 500))
1275 dev_warn(dsi->dev, "spurious interrupt\n");
1276 return IRQ_HANDLED;
1277 }
1278 exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
1279
1280 if (status & DSIM_INT_SW_RST_RELEASE) {
1281 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1282 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE |
1283 DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE);
1284 exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
1285 complete(&dsi->completed);
1286 return IRQ_HANDLED;
1287 }
1288
1289 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1290 DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE)))
1291 return IRQ_HANDLED;
1292
1293 if (exynos_dsi_transfer_finish(dsi))
1294 exynos_dsi_transfer_start(dsi);
1295
1296 return IRQ_HANDLED;
1297 }
1298
1299 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1300 {
1301 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1302 struct drm_encoder *encoder = &dsi->encoder;
1303
1304 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1305 exynos_drm_crtc_te_handler(encoder->crtc);
1306
1307 return IRQ_HANDLED;
1308 }
1309
1310 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1311 {
1312 enable_irq(dsi->irq);
1313
1314 if (gpio_is_valid(dsi->te_gpio))
1315 enable_irq(gpio_to_irq(dsi->te_gpio));
1316 }
1317
1318 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1319 {
1320 if (gpio_is_valid(dsi->te_gpio))
1321 disable_irq(gpio_to_irq(dsi->te_gpio));
1322
1323 disable_irq(dsi->irq);
1324 }
1325
1326 static int exynos_dsi_init(struct exynos_dsi *dsi)
1327 {
1328 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1329
1330 exynos_dsi_reset(dsi);
1331 exynos_dsi_enable_irq(dsi);
1332
1333 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1334 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1335
1336 exynos_dsi_enable_clock(dsi);
1337 if (driver_data->wait_for_reset)
1338 exynos_dsi_wait_for_reset(dsi);
1339 exynos_dsi_set_phy_ctrl(dsi);
1340 exynos_dsi_init_link(dsi);
1341
1342 return 0;
1343 }
1344
1345 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
1346 {
1347 int ret;
1348 int te_gpio_irq;
1349
1350 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
1351 if (!gpio_is_valid(dsi->te_gpio)) {
1352 dev_err(dsi->dev, "no te-gpios specified\n");
1353 ret = dsi->te_gpio;
1354 goto out;
1355 }
1356
1357 ret = gpio_request(dsi->te_gpio, "te_gpio");
1358 if (ret) {
1359 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1360 goto out;
1361 }
1362
1363 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1364 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1365
1366 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1367 IRQF_TRIGGER_RISING, "TE", dsi);
1368 if (ret) {
1369 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1370 gpio_free(dsi->te_gpio);
1371 goto out;
1372 }
1373
1374 out:
1375 return ret;
1376 }
1377
1378 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1379 {
1380 if (gpio_is_valid(dsi->te_gpio)) {
1381 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1382 gpio_free(dsi->te_gpio);
1383 dsi->te_gpio = -ENOENT;
1384 }
1385 }
1386
1387 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1388 struct mipi_dsi_device *device)
1389 {
1390 struct exynos_dsi *dsi = host_to_dsi(host);
1391
1392 dsi->lanes = device->lanes;
1393 dsi->format = device->format;
1394 dsi->mode_flags = device->mode_flags;
1395 dsi->panel_node = device->dev.of_node;
1396
1397 /*
1398 * This is a temporary solution and should be made by more generic way.
1399 *
1400 * If attached panel device is for command mode one, dsi should register
1401 * TE interrupt handler.
1402 */
1403 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1404 int ret = exynos_dsi_register_te_irq(dsi);
1405
1406 if (ret)
1407 return ret;
1408 }
1409
1410 if (dsi->connector.dev)
1411 drm_helper_hpd_irq_event(dsi->connector.dev);
1412
1413 return 0;
1414 }
1415
1416 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1417 struct mipi_dsi_device *device)
1418 {
1419 struct exynos_dsi *dsi = host_to_dsi(host);
1420
1421 exynos_dsi_unregister_te_irq(dsi);
1422
1423 dsi->panel_node = NULL;
1424
1425 if (dsi->connector.dev)
1426 drm_helper_hpd_irq_event(dsi->connector.dev);
1427
1428 return 0;
1429 }
1430
1431 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1432 const struct mipi_dsi_msg *msg)
1433 {
1434 struct exynos_dsi *dsi = host_to_dsi(host);
1435 struct exynos_dsi_transfer xfer;
1436 int ret;
1437
1438 if (!(dsi->state & DSIM_STATE_ENABLED))
1439 return -EINVAL;
1440
1441 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1442 ret = exynos_dsi_init(dsi);
1443 if (ret)
1444 return ret;
1445 dsi->state |= DSIM_STATE_INITIALIZED;
1446 }
1447
1448 ret = mipi_dsi_create_packet(&xfer.packet, msg);
1449 if (ret < 0)
1450 return ret;
1451
1452 xfer.rx_len = msg->rx_len;
1453 xfer.rx_payload = msg->rx_buf;
1454 xfer.flags = msg->flags;
1455
1456 ret = exynos_dsi_transfer(dsi, &xfer);
1457 return (ret < 0) ? ret : xfer.rx_done;
1458 }
1459
1460 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1461 .attach = exynos_dsi_host_attach,
1462 .detach = exynos_dsi_host_detach,
1463 .transfer = exynos_dsi_host_transfer,
1464 };
1465
1466 static void exynos_dsi_enable(struct drm_encoder *encoder)
1467 {
1468 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1469 int ret;
1470
1471 if (dsi->state & DSIM_STATE_ENABLED)
1472 return;
1473
1474 pm_runtime_get_sync(dsi->dev);
1475
1476 dsi->state |= DSIM_STATE_ENABLED;
1477
1478 ret = drm_panel_prepare(dsi->panel);
1479 if (ret < 0) {
1480 dsi->state &= ~DSIM_STATE_ENABLED;
1481 pm_runtime_put_sync(dsi->dev);
1482 return;
1483 }
1484
1485 exynos_dsi_set_display_mode(dsi);
1486 exynos_dsi_set_display_enable(dsi, true);
1487
1488 ret = drm_panel_enable(dsi->panel);
1489 if (ret < 0) {
1490 dsi->state &= ~DSIM_STATE_ENABLED;
1491 exynos_dsi_set_display_enable(dsi, false);
1492 drm_panel_unprepare(dsi->panel);
1493 pm_runtime_put_sync(dsi->dev);
1494 return;
1495 }
1496
1497 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1498 }
1499
1500 static void exynos_dsi_disable(struct drm_encoder *encoder)
1501 {
1502 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1503
1504 if (!(dsi->state & DSIM_STATE_ENABLED))
1505 return;
1506
1507 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1508
1509 drm_panel_disable(dsi->panel);
1510 exynos_dsi_set_display_enable(dsi, false);
1511 drm_panel_unprepare(dsi->panel);
1512
1513 dsi->state &= ~DSIM_STATE_ENABLED;
1514
1515 pm_runtime_put_sync(dsi->dev);
1516 }
1517
1518 static enum drm_connector_status
1519 exynos_dsi_detect(struct drm_connector *connector, bool force)
1520 {
1521 struct exynos_dsi *dsi = connector_to_dsi(connector);
1522
1523 if (!dsi->panel) {
1524 dsi->panel = of_drm_find_panel(dsi->panel_node);
1525 if (dsi->panel)
1526 drm_panel_attach(dsi->panel, &dsi->connector);
1527 } else if (!dsi->panel_node) {
1528 struct drm_encoder *encoder;
1529
1530 encoder = platform_get_drvdata(to_platform_device(dsi->dev));
1531 exynos_dsi_disable(encoder);
1532 drm_panel_detach(dsi->panel);
1533 dsi->panel = NULL;
1534 }
1535
1536 if (dsi->panel)
1537 return connector_status_connected;
1538
1539 return connector_status_disconnected;
1540 }
1541
1542 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1543 {
1544 drm_connector_unregister(connector);
1545 drm_connector_cleanup(connector);
1546 connector->dev = NULL;
1547 }
1548
1549 static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
1550 .dpms = drm_atomic_helper_connector_dpms,
1551 .detect = exynos_dsi_detect,
1552 .fill_modes = drm_helper_probe_single_connector_modes,
1553 .destroy = exynos_dsi_connector_destroy,
1554 .reset = drm_atomic_helper_connector_reset,
1555 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1556 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1557 };
1558
1559 static int exynos_dsi_get_modes(struct drm_connector *connector)
1560 {
1561 struct exynos_dsi *dsi = connector_to_dsi(connector);
1562
1563 if (dsi->panel)
1564 return dsi->panel->funcs->get_modes(dsi->panel);
1565
1566 return 0;
1567 }
1568
1569 static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1570 .get_modes = exynos_dsi_get_modes,
1571 };
1572
1573 static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1574 {
1575 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1576 struct drm_connector *connector = &dsi->connector;
1577 int ret;
1578
1579 connector->polled = DRM_CONNECTOR_POLL_HPD;
1580
1581 ret = drm_connector_init(encoder->dev, connector,
1582 &exynos_dsi_connector_funcs,
1583 DRM_MODE_CONNECTOR_DSI);
1584 if (ret) {
1585 DRM_ERROR("Failed to initialize connector with drm\n");
1586 return ret;
1587 }
1588
1589 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1590 drm_connector_register(connector);
1591 drm_mode_connector_attach_encoder(connector, encoder);
1592
1593 return 0;
1594 }
1595
1596 static void exynos_dsi_mode_set(struct drm_encoder *encoder,
1597 struct drm_display_mode *mode,
1598 struct drm_display_mode *adjusted_mode)
1599 {
1600 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1601 struct videomode *vm = &dsi->vm;
1602 struct drm_display_mode *m = adjusted_mode;
1603
1604 vm->hactive = m->hdisplay;
1605 vm->vactive = m->vdisplay;
1606 vm->vfront_porch = m->vsync_start - m->vdisplay;
1607 vm->vback_porch = m->vtotal - m->vsync_end;
1608 vm->vsync_len = m->vsync_end - m->vsync_start;
1609 vm->hfront_porch = m->hsync_start - m->hdisplay;
1610 vm->hback_porch = m->htotal - m->hsync_end;
1611 vm->hsync_len = m->hsync_end - m->hsync_start;
1612 }
1613
1614 static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
1615 .mode_set = exynos_dsi_mode_set,
1616 .enable = exynos_dsi_enable,
1617 .disable = exynos_dsi_disable,
1618 };
1619
1620 static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = {
1621 .destroy = drm_encoder_cleanup,
1622 };
1623
1624 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1625
1626 static int exynos_dsi_of_read_u32(const struct device_node *np,
1627 const char *propname, u32 *out_value)
1628 {
1629 int ret = of_property_read_u32(np, propname, out_value);
1630
1631 if (ret < 0)
1632 pr_err("%s: failed to get '%s' property\n", np->full_name,
1633 propname);
1634
1635 return ret;
1636 }
1637
1638 enum {
1639 DSI_PORT_IN,
1640 DSI_PORT_OUT
1641 };
1642
1643 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1644 {
1645 struct device *dev = dsi->dev;
1646 struct device_node *node = dev->of_node;
1647 struct device_node *ep;
1648 int ret;
1649
1650 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1651 &dsi->pll_clk_rate);
1652 if (ret < 0)
1653 return ret;
1654
1655 ep = of_graph_get_endpoint_by_regs(node, DSI_PORT_OUT, 0);
1656 if (!ep) {
1657 dev_err(dev, "no output port with endpoint specified\n");
1658 return -EINVAL;
1659 }
1660
1661 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1662 &dsi->burst_clk_rate);
1663 if (ret < 0)
1664 goto end;
1665
1666 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1667 &dsi->esc_clk_rate);
1668 if (ret < 0)
1669 goto end;
1670
1671 of_node_put(ep);
1672
1673 ep = of_graph_get_next_endpoint(node, NULL);
1674 if (!ep) {
1675 ret = -EINVAL;
1676 goto end;
1677 }
1678
1679 dsi->bridge_node = of_graph_get_remote_port_parent(ep);
1680 if (!dsi->bridge_node) {
1681 ret = -EINVAL;
1682 goto end;
1683 }
1684 end:
1685 of_node_put(ep);
1686
1687 return ret;
1688 }
1689
1690 static int exynos_dsi_bind(struct device *dev, struct device *master,
1691 void *data)
1692 {
1693 struct drm_encoder *encoder = dev_get_drvdata(dev);
1694 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1695 struct drm_device *drm_dev = data;
1696 struct drm_bridge *bridge;
1697 int ret;
1698
1699 ret = exynos_drm_crtc_get_pipe_from_type(drm_dev,
1700 EXYNOS_DISPLAY_TYPE_LCD);
1701 if (ret < 0)
1702 return ret;
1703
1704 encoder->possible_crtcs = 1 << ret;
1705
1706 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
1707
1708 drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs,
1709 DRM_MODE_ENCODER_TMDS, NULL);
1710
1711 drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
1712
1713 ret = exynos_dsi_create_connector(encoder);
1714 if (ret) {
1715 DRM_ERROR("failed to create connector ret = %d\n", ret);
1716 drm_encoder_cleanup(encoder);
1717 return ret;
1718 }
1719
1720 bridge = of_drm_find_bridge(dsi->bridge_node);
1721 if (bridge) {
1722 encoder->bridge = bridge;
1723 drm_bridge_attach(drm_dev, bridge);
1724 }
1725
1726 return mipi_dsi_host_register(&dsi->dsi_host);
1727 }
1728
1729 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1730 void *data)
1731 {
1732 struct drm_encoder *encoder = dev_get_drvdata(dev);
1733 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1734
1735 exynos_dsi_disable(encoder);
1736
1737 mipi_dsi_host_unregister(&dsi->dsi_host);
1738 }
1739
1740 static const struct component_ops exynos_dsi_component_ops = {
1741 .bind = exynos_dsi_bind,
1742 .unbind = exynos_dsi_unbind,
1743 };
1744
1745 static int exynos_dsi_probe(struct platform_device *pdev)
1746 {
1747 struct device *dev = &pdev->dev;
1748 struct resource *res;
1749 struct exynos_dsi *dsi;
1750 int ret, i;
1751
1752 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1753 if (!dsi)
1754 return -ENOMEM;
1755
1756 /* To be checked as invalid one */
1757 dsi->te_gpio = -ENOENT;
1758
1759 init_completion(&dsi->completed);
1760 spin_lock_init(&dsi->transfer_lock);
1761 INIT_LIST_HEAD(&dsi->transfer_list);
1762
1763 dsi->dsi_host.ops = &exynos_dsi_ops;
1764 dsi->dsi_host.dev = dev;
1765
1766 dsi->dev = dev;
1767 dsi->driver_data = of_device_get_match_data(dev);
1768
1769 ret = exynos_dsi_parse_dt(dsi);
1770 if (ret)
1771 return ret;
1772
1773 dsi->supplies[0].supply = "vddcore";
1774 dsi->supplies[1].supply = "vddio";
1775 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1776 dsi->supplies);
1777 if (ret) {
1778 dev_info(dev, "failed to get regulators: %d\n", ret);
1779 return -EPROBE_DEFER;
1780 }
1781
1782 dsi->clks = devm_kzalloc(dev,
1783 sizeof(*dsi->clks) * dsi->driver_data->num_clks,
1784 GFP_KERNEL);
1785 if (!dsi->clks)
1786 return -ENOMEM;
1787
1788 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1789 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1790 if (IS_ERR(dsi->clks[i])) {
1791 if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1792 strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
1793 i--;
1794 continue;
1795 }
1796
1797 dev_info(dev, "failed to get the clock: %s\n",
1798 clk_names[i]);
1799 return PTR_ERR(dsi->clks[i]);
1800 }
1801 }
1802
1803 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1804 dsi->reg_base = devm_ioremap_resource(dev, res);
1805 if (IS_ERR(dsi->reg_base)) {
1806 dev_err(dev, "failed to remap io region\n");
1807 return PTR_ERR(dsi->reg_base);
1808 }
1809
1810 dsi->phy = devm_phy_get(dev, "dsim");
1811 if (IS_ERR(dsi->phy)) {
1812 dev_info(dev, "failed to get dsim phy\n");
1813 return PTR_ERR(dsi->phy);
1814 }
1815
1816 dsi->irq = platform_get_irq(pdev, 0);
1817 if (dsi->irq < 0) {
1818 dev_err(dev, "failed to request dsi irq resource\n");
1819 return dsi->irq;
1820 }
1821
1822 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1823 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1824 exynos_dsi_irq, IRQF_ONESHOT,
1825 dev_name(dev), dsi);
1826 if (ret) {
1827 dev_err(dev, "failed to request dsi irq\n");
1828 return ret;
1829 }
1830
1831 platform_set_drvdata(pdev, &dsi->encoder);
1832
1833 pm_runtime_enable(dev);
1834
1835 return component_add(dev, &exynos_dsi_component_ops);
1836 }
1837
1838 static int exynos_dsi_remove(struct platform_device *pdev)
1839 {
1840 pm_runtime_disable(&pdev->dev);
1841
1842 component_del(&pdev->dev, &exynos_dsi_component_ops);
1843
1844 return 0;
1845 }
1846
1847 static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1848 {
1849 struct drm_encoder *encoder = dev_get_drvdata(dev);
1850 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1851 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1852 int ret, i;
1853
1854 usleep_range(10000, 20000);
1855
1856 if (dsi->state & DSIM_STATE_INITIALIZED) {
1857 dsi->state &= ~DSIM_STATE_INITIALIZED;
1858
1859 exynos_dsi_disable_clock(dsi);
1860
1861 exynos_dsi_disable_irq(dsi);
1862 }
1863
1864 dsi->state &= ~DSIM_STATE_CMD_LPM;
1865
1866 phy_power_off(dsi->phy);
1867
1868 for (i = driver_data->num_clks - 1; i > -1; i--)
1869 clk_disable_unprepare(dsi->clks[i]);
1870
1871 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1872 if (ret < 0)
1873 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1874
1875 return 0;
1876 }
1877
1878 static int __maybe_unused exynos_dsi_resume(struct device *dev)
1879 {
1880 struct drm_encoder *encoder = dev_get_drvdata(dev);
1881 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1882 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1883 int ret, i;
1884
1885 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1886 if (ret < 0) {
1887 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1888 return ret;
1889 }
1890
1891 for (i = 0; i < driver_data->num_clks; i++) {
1892 ret = clk_prepare_enable(dsi->clks[i]);
1893 if (ret < 0)
1894 goto err_clk;
1895 }
1896
1897 ret = phy_power_on(dsi->phy);
1898 if (ret < 0) {
1899 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1900 goto err_clk;
1901 }
1902
1903 return 0;
1904
1905 err_clk:
1906 while (--i > -1)
1907 clk_disable_unprepare(dsi->clks[i]);
1908 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1909
1910 return ret;
1911 }
1912
1913 static const struct dev_pm_ops exynos_dsi_pm_ops = {
1914 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
1915 };
1916
1917 struct platform_driver dsi_driver = {
1918 .probe = exynos_dsi_probe,
1919 .remove = exynos_dsi_remove,
1920 .driver = {
1921 .name = "exynos-dsi",
1922 .owner = THIS_MODULE,
1923 .pm = &exynos_dsi_pm_ops,
1924 .of_match_table = exynos_dsi_of_match,
1925 },
1926 };
1927
1928 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1929 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1930 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1931 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support