2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <subdev/timer.h>
28 static const struct nvkm_bitfield nv50_gr_status
[] = {
29 { 0x00000001, "BUSY" }, /* set when any bit is set */
30 { 0x00000002, "DISPATCH" },
31 { 0x00000004, "UNK2" },
32 { 0x00000008, "UNK3" },
33 { 0x00000010, "UNK4" },
34 { 0x00000020, "UNK5" },
35 { 0x00000040, "M2MF" },
36 { 0x00000080, "UNK7" },
37 { 0x00000100, "CTXPROG" },
38 { 0x00000200, "VFETCH" },
39 { 0x00000400, "CCACHE_PREGEOM" },
40 { 0x00000800, "STRMOUT_VATTR_POSTGEOM" },
41 { 0x00001000, "VCLIP" },
42 { 0x00002000, "RATTR_APLANE" },
43 { 0x00004000, "TRAST" },
44 { 0x00008000, "CLIPID" },
45 { 0x00010000, "ZCULL" },
46 { 0x00020000, "ENG2D" },
47 { 0x00040000, "RMASK" },
48 { 0x00080000, "TPC_RAST" },
49 { 0x00100000, "TPC_PROP" },
50 { 0x00200000, "TPC_TEX" },
51 { 0x00400000, "TPC_GEOM" },
52 { 0x00800000, "TPC_MP" },
53 { 0x01000000, "ROP" },
57 static const struct nvkm_bitfield
58 nv50_gr_vstatus_0
[] = {
69 static const struct nvkm_bitfield
70 nv50_gr_vstatus_1
[] = {
79 static const struct nvkm_bitfield
80 nv50_gr_vstatus_2
[] = {
93 nvkm_gr_vstatus_print(struct nv50_gr
*gr
, int r
,
94 const struct nvkm_bitfield
*units
, u32 status
)
96 struct nvkm_subdev
*subdev
= &gr
->base
.engine
.subdev
;
102 for (i
= 0; units
[i
].name
&& status
; i
++) {
103 if ((status
& 7) == 1)
108 nvkm_snprintbf(msg
, sizeof(msg
), units
, mask
);
109 nvkm_error(subdev
, "PGRAPH_VSTATUS%d: %08x [%s]\n", r
, stat
, msg
);
113 g84_gr_tlb_flush(struct nvkm_gr
*base
)
115 struct nv50_gr
*gr
= nv50_gr(base
);
116 struct nvkm_subdev
*subdev
= &gr
->base
.engine
.subdev
;
117 struct nvkm_device
*device
= subdev
->device
;
118 struct nvkm_timer
*tmr
= device
->timer
;
119 bool idle
, timeout
= false;
125 spin_lock_irqsave(&gr
->lock
, flags
);
126 nvkm_mask(device
, 0x400500, 0x00000001, 0x00000000);
128 start
= nvkm_timer_read(tmr
);
132 for (tmp
= nvkm_rd32(device
, 0x400380); tmp
&& idle
; tmp
>>= 3) {
137 for (tmp
= nvkm_rd32(device
, 0x400384); tmp
&& idle
; tmp
>>= 3) {
142 for (tmp
= nvkm_rd32(device
, 0x400388); tmp
&& idle
; tmp
>>= 3) {
147 !(timeout
= nvkm_timer_read(tmr
) - start
> 2000000000));
150 nvkm_error(subdev
, "PGRAPH TLB flush idle timeout fail\n");
152 tmp
= nvkm_rd32(device
, 0x400700);
153 nvkm_snprintbf(status
, sizeof(status
), nv50_gr_status
, tmp
);
154 nvkm_error(subdev
, "PGRAPH_STATUS %08x [%s]\n", tmp
, status
);
156 nvkm_gr_vstatus_print(gr
, 0, nv50_gr_vstatus_0
,
157 nvkm_rd32(device
, 0x400380));
158 nvkm_gr_vstatus_print(gr
, 1, nv50_gr_vstatus_1
,
159 nvkm_rd32(device
, 0x400384));
160 nvkm_gr_vstatus_print(gr
, 2, nv50_gr_vstatus_2
,
161 nvkm_rd32(device
, 0x400388));
165 nvkm_wr32(device
, 0x100c80, 0x00000001);
166 nvkm_msec(device
, 2000,
167 if (!(nvkm_rd32(device
, 0x100c80) & 0x00000001))
170 nvkm_mask(device
, 0x400500, 0x00000001, 0x00000001);
171 spin_unlock_irqrestore(&gr
->lock
, flags
);
172 return timeout
? -EBUSY
: 0;
175 static const struct nvkm_gr_func
177 .init
= nv50_gr_init
,
178 .intr
= nv50_gr_intr
,
179 .chan_new
= nv50_gr_chan_new
,
180 .tlb_flush
= g84_gr_tlb_flush
,
181 .units
= nv50_gr_units
,
183 { -1, -1, 0x0030, &nv50_gr_object
},
184 { -1, -1, 0x502d, &nv50_gr_object
},
185 { -1, -1, 0x5039, &nv50_gr_object
},
186 { -1, -1, 0x50c0, &nv50_gr_object
},
187 { -1, -1, 0x8297, &nv50_gr_object
},
193 g84_gr_new(struct nvkm_device
*device
, int index
, struct nvkm_gr
**pgr
)
195 return nv50_gr_new_(&g84_gr
, device
, index
, pgr
);