drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c

   1 /*
   2  * Copyright 2016 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "gf100.h"
  25 #include "ctxgf100.h"
  26
  27 #include <nvif/class.h>
  28
  29 /*******************************************************************************
  30  * PGRAPH engine/subdev functions
  31  ******************************************************************************/
  32
  33 static void
  34 gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)
  35 {
  36         struct nvkm_device *device = gr->base.engine.subdev.device;
  37         /*XXX: otherwise identical to gm200 aside from mask.. do everywhere? */
  38         const u32 fbp_count = nvkm_rd32(device, 0x12006c) & 0x0000000f;
  39         nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
  40         nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
  41 }
  42
  43 static int
  44 gp100_gr_init(struct gf100_gr *gr)
  45 {
  46         struct nvkm_device *device = gr->base.engine.subdev.device;
  47         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
  48         u32 data[TPC_MAX / 8] = {};
  49         u8  tpcnr[GPC_MAX];
  50         int gpc, tpc, rop;
  51         int i;
  52
  53         gr->func->init_gpc_mmu(gr);
  54
  55         gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
  56
  57         nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
  58
  59         memset(data, 0x00, sizeof(data));
  60         memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
  61         for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
  62                 do {
  63                         gpc = (gpc + 1) % gr->gpc_nr;
  64                 } while (!tpcnr[gpc]);
  65                 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
  66
  67                 data[i / 8] |= tpc << ((i % 8) * 4);
  68         }
  69
  70         nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
  71         nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
  72         nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
  73         nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
  74
  75         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
  76                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
  77                           gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
  78                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
  79                                                          gr->tpc_total);
  80                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
  81         }
  82
  83         nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
  84         nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
  85         nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
  86
  87         gr->func->init_rop_active_fbps(gr);
  88
  89         nvkm_wr32(device, 0x400500, 0x00010001);
  90         nvkm_wr32(device, 0x400100, 0xffffffff);
  91         nvkm_wr32(device, 0x40013c, 0xffffffff);
  92         nvkm_wr32(device, 0x400124, 0x00000002);
  93         nvkm_wr32(device, 0x409c24, 0x000f0002);
  94         nvkm_wr32(device, 0x405848, 0xc0000000);
  95         nvkm_mask(device, 0x40584c, 0x00000000, 0x00000001);
  96         nvkm_wr32(device, 0x404000, 0xc0000000);
  97         nvkm_wr32(device, 0x404600, 0xc0000000);
  98         nvkm_wr32(device, 0x408030, 0xc0000000);
  99         nvkm_wr32(device, 0x404490, 0xc0000000);
 100         nvkm_wr32(device, 0x406018, 0xc0000000);
 101         nvkm_wr32(device, 0x407020, 0x40000000);
 102         nvkm_wr32(device, 0x405840, 0xc0000000);
 103         nvkm_wr32(device, 0x405844, 0x00ffffff);
 104         nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
 105
 106         nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000);
 107         nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000);
 108
 109         gr->func->init_ppc_exceptions(gr);
 110
 111         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
 112                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 113                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 114                 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 115                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 116                 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
 117                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
 118                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
 119                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
 120                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
 121                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
 122                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
 123                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
 124                         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);
 125                 }
 126                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 127                 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 128         }
 129
 130         for (rop = 0; rop < gr->rop_nr; rop++) {
 131                 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
 132                 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
 133                 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
 134                 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
 135         }
 136
 137         nvkm_wr32(device, 0x400108, 0xffffffff);
 138         nvkm_wr32(device, 0x400138, 0xffffffff);
 139         nvkm_wr32(device, 0x400118, 0xffffffff);
 140         nvkm_wr32(device, 0x400130, 0xffffffff);
 141         nvkm_wr32(device, 0x40011c, 0xffffffff);
 142         nvkm_wr32(device, 0x400134, 0xffffffff);
 143
 144         gf100_gr_zbc_init(gr);
 145
 146         return gf100_gr_init_ctxctl(gr);
 147 }
 148
 149 static const struct gf100_gr_func
 150 gp100_gr = {
 151         .init = gp100_gr_init,
 152         .init_gpc_mmu = gm200_gr_init_gpc_mmu,
 153         .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
 154         .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
 155         .rops = gm200_gr_rops,
 156         .ppc_nr = 2,
 157         .grctx = &gp100_grctx,
 158         .sclass = {
 159                 { -1, -1, FERMI_TWOD_A },
 160                 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
 161                 { -1, -1, PASCAL_A, &gf100_fermi },
 162                 { -1, -1, PASCAL_COMPUTE_A },
 163                 {}
 164         }
 165 };
 166
 167 int
 168 gp100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 169 {
 170         return gm200_gr_new_(&gp100_gr, device, index, pgr);
 171 }