drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c

   1 #include "nv20.h"
   2 #include "regs.h"
   3
   4 #include <core/gpuobj.h>
   5 #include <engine/fifo.h>
   6 #include <engine/fifo/chan.h>
   7
   8 /*******************************************************************************
   9  * PGRAPH context
  10  ******************************************************************************/
  11
  12 static const struct nvkm_object_func
  13 nv2a_gr_chan = {
  14         .dtor = nv20_gr_chan_dtor,
  15         .init = nv20_gr_chan_init,
  16         .fini = nv20_gr_chan_fini,
  17 };
  18
  19 static int
  20 nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
  21                  const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
  22 {
  23         struct nv20_gr *gr = nv20_gr(base);
  24         struct nv20_gr_chan *chan;
  25         int ret, i;
  26
  27         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
  28                 return -ENOMEM;
  29         nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object);
  30         chan->gr = gr;
  31         chan->chid = fifoch->chid;
  32         *pobject = &chan->object;
  33
  34         ret = nvkm_memory_new(gr->base.engine.subdev.device,
  35                               NVKM_MEM_TARGET_INST, 0x36b0, 16, true,
  36                               &chan->inst);
  37         if (ret)
  38                 return ret;
  39
  40         nvkm_kmap(chan->inst);
  41         nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
  42         nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
  43         nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
  44         nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
  45         nvkm_wo32(chan->inst, 0x047c, 0x00000101);
  46         nvkm_wo32(chan->inst, 0x0490, 0x00000111);
  47         nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
  48         for (i = 0x04d4; i <= 0x04e0; i += 4)
  49                 nvkm_wo32(chan->inst, i, 0x00030303);
  50         for (i = 0x04f4; i <= 0x0500; i += 4)
  51                 nvkm_wo32(chan->inst, i, 0x00080000);
  52         for (i = 0x050c; i <= 0x0518; i += 4)
  53                 nvkm_wo32(chan->inst, i, 0x01012000);
  54         for (i = 0x051c; i <= 0x0528; i += 4)
  55                 nvkm_wo32(chan->inst, i, 0x000105b8);
  56         for (i = 0x052c; i <= 0x0538; i += 4)
  57                 nvkm_wo32(chan->inst, i, 0x00080008);
  58         for (i = 0x055c; i <= 0x0598; i += 4)
  59                 nvkm_wo32(chan->inst, i, 0x07ff0000);
  60         nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
  61         nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
  62         nvkm_wo32(chan->inst, 0x0604, 0x00004000);
  63         nvkm_wo32(chan->inst, 0x0610, 0x00000001);
  64         nvkm_wo32(chan->inst, 0x0618, 0x00040000);
  65         nvkm_wo32(chan->inst, 0x061c, 0x00010000);
  66         for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
  67                 nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
  68                 nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
  69                 nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
  70         }
  71         nvkm_wo32(chan->inst, 0x269c, 0x3f800000);
  72         nvkm_wo32(chan->inst, 0x26b0, 0x3f800000);
  73         nvkm_wo32(chan->inst, 0x26dc, 0x40000000);
  74         nvkm_wo32(chan->inst, 0x26e0, 0x3f800000);
  75         nvkm_wo32(chan->inst, 0x26e4, 0x3f000000);
  76         nvkm_wo32(chan->inst, 0x26ec, 0x40000000);
  77         nvkm_wo32(chan->inst, 0x26f0, 0x3f800000);
  78         nvkm_wo32(chan->inst, 0x26f8, 0xbf800000);
  79         nvkm_wo32(chan->inst, 0x2700, 0xbf800000);
  80         nvkm_wo32(chan->inst, 0x3024, 0x000fe000);
  81         nvkm_wo32(chan->inst, 0x30a0, 0x000003f8);
  82         nvkm_wo32(chan->inst, 0x33fc, 0x002fe000);
  83         for (i = 0x341c; i <= 0x3438; i += 4)
  84                 nvkm_wo32(chan->inst, i, 0x001c527c);
  85         nvkm_done(chan->inst);
  86         return 0;
  87 }
  88
  89 /*******************************************************************************
  90  * PGRAPH engine/subdev functions
  91  ******************************************************************************/
  92
  93 static const struct nvkm_gr_func
  94 nv2a_gr = {
  95         .dtor = nv20_gr_dtor,
  96         .oneinit = nv20_gr_oneinit,
  97         .init = nv20_gr_init,
  98         .intr = nv20_gr_intr,
  99         .tile = nv20_gr_tile,
 100         .chan_new = nv2a_gr_chan_new,
 101         .sclass = {
 102                 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
 103                 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
 104                 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
 105                 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
 106                 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
 107                 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */
 108                 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
 109                 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
 110                 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
 111                 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
 112                 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
 113                 { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
 114                 { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
 115                 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
 116                 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
 117                 {}
 118         }
 119 };
 120
 121 int
 122 nv2a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 123 {
 124         return nv20_gr_new_(&nv2a_gr, device, index, pgr);
 125 }