drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c

   1 /*
   2  * Toppoly TD028TTEC1 panel support
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Neo 1973 code (jbt6k74.c):
   8  * Copyright (C) 2006-2007 by OpenMoko, Inc.
   9  * Author: Harald Welte <laforge@openmoko.org>
  10  *
  11  * Ported and adapted from Neo 1973 U-Boot by:
  12  * H. Nikolaus Schaller <hns@goldelico.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of the GNU General Public License version 2 as published by
  16  * the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  21  * more details.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program.  If not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/delay.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/gpio.h>
  31
  32 #include "../dss/omapdss.h"
  33
  34 struct panel_drv_data {
  35         struct omap_dss_device dssdev;
  36         struct omap_dss_device *in;
  37
  38         int data_lines;
  39
  40         struct videomode vm;
  41
  42         struct spi_device *spi_dev;
  43 };
  44
  45 static struct videomode td028ttec1_panel_vm = {
  46         .hactive        = 480,
  47         .vactive        = 640,
  48         .pixelclock     = 22153000,
  49         .hfront_porch   = 24,
  50         .hsync_len      = 8,
  51         .hback_porch    = 8,
  52         .vfront_porch   = 4,
  53         .vsync_len      = 2,
  54         .vback_porch    = 2,
  55
  56         .flags          = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
  57                           DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
  58                           DISPLAY_FLAGS_PIXDATA_NEGEDGE,
  59         /*
  60          * Note: According to the panel documentation:
  61          * SYNC needs to be driven on the FALLING edge
  62          */
  63 };
  64
  65 #define JBT_COMMAND     0x000
  66 #define JBT_DATA        0x100
  67
  68 static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
  69 {
  70         int rc;
  71         u16 tx_buf = JBT_COMMAND | reg;
  72
  73         rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
  74                         1*sizeof(u16));
  75         if (rc != 0)
  76                 dev_err(&ddata->spi_dev->dev,
  77                         "jbt_ret_write_0 spi_write ret %d\n", rc);
  78
  79         return rc;
  80 }
  81
  82 static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
  83 {
  84         int rc;
  85         u16 tx_buf[2];
  86
  87         tx_buf[0] = JBT_COMMAND | reg;
  88         tx_buf[1] = JBT_DATA | data;
  89         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
  90                         2*sizeof(u16));
  91         if (rc != 0)
  92                 dev_err(&ddata->spi_dev->dev,
  93                         "jbt_reg_write_1 spi_write ret %d\n", rc);
  94
  95         return rc;
  96 }
  97
  98 static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
  99 {
 100         int rc;
 101         u16 tx_buf[3];
 102
 103         tx_buf[0] = JBT_COMMAND | reg;
 104         tx_buf[1] = JBT_DATA | (data >> 8);
 105         tx_buf[2] = JBT_DATA | (data & 0xff);
 106
 107         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
 108                         3*sizeof(u16));
 109
 110         if (rc != 0)
 111                 dev_err(&ddata->spi_dev->dev,
 112                         "jbt_reg_write_2 spi_write ret %d\n", rc);
 113
 114         return rc;
 115 }
 116
 117 enum jbt_register {
 118         JBT_REG_SLEEP_IN                = 0x10,
 119         JBT_REG_SLEEP_OUT               = 0x11,
 120
 121         JBT_REG_DISPLAY_OFF             = 0x28,
 122         JBT_REG_DISPLAY_ON              = 0x29,
 123
 124         JBT_REG_RGB_FORMAT              = 0x3a,
 125         JBT_REG_QUAD_RATE               = 0x3b,
 126
 127         JBT_REG_POWER_ON_OFF            = 0xb0,
 128         JBT_REG_BOOSTER_OP              = 0xb1,
 129         JBT_REG_BOOSTER_MODE            = 0xb2,
 130         JBT_REG_BOOSTER_FREQ            = 0xb3,
 131         JBT_REG_OPAMP_SYSCLK            = 0xb4,
 132         JBT_REG_VSC_VOLTAGE             = 0xb5,
 133         JBT_REG_VCOM_VOLTAGE            = 0xb6,
 134         JBT_REG_EXT_DISPL               = 0xb7,
 135         JBT_REG_OUTPUT_CONTROL          = 0xb8,
 136         JBT_REG_DCCLK_DCEV              = 0xb9,
 137         JBT_REG_DISPLAY_MODE1           = 0xba,
 138         JBT_REG_DISPLAY_MODE2           = 0xbb,
 139         JBT_REG_DISPLAY_MODE            = 0xbc,
 140         JBT_REG_ASW_SLEW                = 0xbd,
 141         JBT_REG_DUMMY_DISPLAY           = 0xbe,
 142         JBT_REG_DRIVE_SYSTEM            = 0xbf,
 143
 144         JBT_REG_SLEEP_OUT_FR_A          = 0xc0,
 145         JBT_REG_SLEEP_OUT_FR_B          = 0xc1,
 146         JBT_REG_SLEEP_OUT_FR_C          = 0xc2,
 147         JBT_REG_SLEEP_IN_LCCNT_D        = 0xc3,
 148         JBT_REG_SLEEP_IN_LCCNT_E        = 0xc4,
 149         JBT_REG_SLEEP_IN_LCCNT_F        = 0xc5,
 150         JBT_REG_SLEEP_IN_LCCNT_G        = 0xc6,
 151
 152         JBT_REG_GAMMA1_FINE_1           = 0xc7,
 153         JBT_REG_GAMMA1_FINE_2           = 0xc8,
 154         JBT_REG_GAMMA1_INCLINATION      = 0xc9,
 155         JBT_REG_GAMMA1_BLUE_OFFSET      = 0xca,
 156
 157         JBT_REG_BLANK_CONTROL           = 0xcf,
 158         JBT_REG_BLANK_TH_TV             = 0xd0,
 159         JBT_REG_CKV_ON_OFF              = 0xd1,
 160         JBT_REG_CKV_1_2                 = 0xd2,
 161         JBT_REG_OEV_TIMING              = 0xd3,
 162         JBT_REG_ASW_TIMING_1            = 0xd4,
 163         JBT_REG_ASW_TIMING_2            = 0xd5,
 164
 165         JBT_REG_HCLOCK_VGA              = 0xec,
 166         JBT_REG_HCLOCK_QVGA             = 0xed,
 167 };
 168
 169 #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
 170
 171 static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
 172 {
 173         struct panel_drv_data *ddata = to_panel_data(dssdev);
 174         struct omap_dss_device *in = ddata->in;
 175         int r;
 176
 177         if (omapdss_device_is_connected(dssdev))
 178                 return 0;
 179
 180         r = in->ops.dpi->connect(in, dssdev);
 181         if (r)
 182                 return r;
 183
 184         return 0;
 185 }
 186
 187 static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
 188 {
 189         struct panel_drv_data *ddata = to_panel_data(dssdev);
 190         struct omap_dss_device *in = ddata->in;
 191
 192         if (!omapdss_device_is_connected(dssdev))
 193                 return;
 194
 195         in->ops.dpi->disconnect(in, dssdev);
 196 }
 197
 198 static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
 199 {
 200         struct panel_drv_data *ddata = to_panel_data(dssdev);
 201         struct omap_dss_device *in = ddata->in;
 202         int r;
 203
 204         if (!omapdss_device_is_connected(dssdev))
 205                 return -ENODEV;
 206
 207         if (omapdss_device_is_enabled(dssdev))
 208                 return 0;
 209
 210         if (ddata->data_lines)
 211                 in->ops.dpi->set_data_lines(in, ddata->data_lines);
 212         in->ops.dpi->set_timings(in, &ddata->vm);
 213
 214         r = in->ops.dpi->enable(in);
 215         if (r)
 216                 return r;
 217
 218         dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
 219                 dssdev->state);
 220
 221         /* three times command zero */
 222         r |= jbt_ret_write_0(ddata, 0x00);
 223         usleep_range(1000, 2000);
 224         r |= jbt_ret_write_0(ddata, 0x00);
 225         usleep_range(1000, 2000);
 226         r |= jbt_ret_write_0(ddata, 0x00);
 227         usleep_range(1000, 2000);
 228
 229         if (r) {
 230                 dev_warn(dssdev->dev, "transfer error\n");
 231                 goto transfer_err;
 232         }
 233
 234         /* deep standby out */
 235         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
 236
 237         /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
 238         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
 239
 240         /* Quad mode off */
 241         r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
 242
 243         /* AVDD on, XVDD on */
 244         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
 245
 246         /* Output control */
 247         r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
 248
 249         /* Sleep mode off */
 250         r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
 251
 252         /* at this point we have like 50% grey */
 253
 254         /* initialize register set */
 255         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
 256         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
 257         r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
 258         r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
 259         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
 260         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
 261         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 262         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 263         r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
 264         r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
 265         r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
 266         r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
 267         r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
 268         /*
 269          * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
 270          * to avoid red / blue flicker
 271          */
 272         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
 273         r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
 274
 275         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
 276         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
 277         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
 278         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
 279         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
 280         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
 281         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
 282
 283         r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
 284         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
 285         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
 286         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
 287
 288         r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
 289         r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
 290         r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
 291
 292         r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
 293         r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
 294
 295         r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
 296         r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
 297         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
 298
 299         r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
 300
 301         dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
 302
 303 transfer_err:
 304
 305         return r ? -EIO : 0;
 306 }
 307
 308 static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
 309 {
 310         struct panel_drv_data *ddata = to_panel_data(dssdev);
 311         struct omap_dss_device *in = ddata->in;
 312
 313         if (!omapdss_device_is_enabled(dssdev))
 314                 return;
 315
 316         dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
 317
 318         jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
 319         jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
 320         jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
 321         jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
 322
 323         in->ops.dpi->disable(in);
 324
 325         dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
 326 }
 327
 328 static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
 329                                          struct videomode *vm)
 330 {
 331         struct panel_drv_data *ddata = to_panel_data(dssdev);
 332         struct omap_dss_device *in = ddata->in;
 333
 334         ddata->vm = *vm;
 335         dssdev->panel.vm = *vm;
 336
 337         in->ops.dpi->set_timings(in, vm);
 338 }
 339
 340 static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
 341                                          struct videomode *vm)
 342 {
 343         struct panel_drv_data *ddata = to_panel_data(dssdev);
 344
 345         *vm = ddata->vm;
 346 }
 347
 348 static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
 349                                           struct videomode *vm)
 350 {
 351         struct panel_drv_data *ddata = to_panel_data(dssdev);
 352         struct omap_dss_device *in = ddata->in;
 353
 354         return in->ops.dpi->check_timings(in, vm);
 355 }
 356
 357 static struct omap_dss_driver td028ttec1_ops = {
 358         .connect        = td028ttec1_panel_connect,
 359         .disconnect     = td028ttec1_panel_disconnect,
 360
 361         .enable         = td028ttec1_panel_enable,
 362         .disable        = td028ttec1_panel_disable,
 363
 364         .set_timings    = td028ttec1_panel_set_timings,
 365         .get_timings    = td028ttec1_panel_get_timings,
 366         .check_timings  = td028ttec1_panel_check_timings,
 367 };
 368
 369 static int td028ttec1_probe_of(struct spi_device *spi)
 370 {
 371         struct device_node *node = spi->dev.of_node;
 372         struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
 373         struct omap_dss_device *in;
 374
 375         in = omapdss_of_find_source_for_first_ep(node);
 376         if (IS_ERR(in)) {
 377                 dev_err(&spi->dev, "failed to find video source\n");
 378                 return PTR_ERR(in);
 379         }
 380
 381         ddata->in = in;
 382
 383         return 0;
 384 }
 385
 386 static int td028ttec1_panel_probe(struct spi_device *spi)
 387 {
 388         struct panel_drv_data *ddata;
 389         struct omap_dss_device *dssdev;
 390         int r;
 391
 392         dev_dbg(&spi->dev, "%s\n", __func__);
 393
 394         spi->bits_per_word = 9;
 395         spi->mode = SPI_MODE_3;
 396
 397         r = spi_setup(spi);
 398         if (r < 0) {
 399                 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
 400                 return r;
 401         }
 402
 403         ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
 404         if (ddata == NULL)
 405                 return -ENOMEM;
 406
 407         dev_set_drvdata(&spi->dev, ddata);
 408
 409         ddata->spi_dev = spi;
 410
 411         if (!spi->dev.of_node)
 412                 return -ENODEV;
 413
 414         r = td028ttec1_probe_of(spi);
 415         if (r)
 416                 return r;
 417
 418         ddata->vm = td028ttec1_panel_vm;
 419
 420         dssdev = &ddata->dssdev;
 421         dssdev->dev = &spi->dev;
 422         dssdev->driver = &td028ttec1_ops;
 423         dssdev->type = OMAP_DISPLAY_TYPE_DPI;
 424         dssdev->owner = THIS_MODULE;
 425         dssdev->panel.vm = ddata->vm;
 426         dssdev->phy.dpi.data_lines = ddata->data_lines;
 427
 428         r = omapdss_register_display(dssdev);
 429         if (r) {
 430                 dev_err(&spi->dev, "Failed to register panel\n");
 431                 goto err_reg;
 432         }
 433
 434         return 0;
 435
 436 err_reg:
 437         omap_dss_put_device(ddata->in);
 438         return r;
 439 }
 440
 441 static int td028ttec1_panel_remove(struct spi_device *spi)
 442 {
 443         struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
 444         struct omap_dss_device *dssdev = &ddata->dssdev;
 445         struct omap_dss_device *in = ddata->in;
 446
 447         dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
 448
 449         omapdss_unregister_display(dssdev);
 450
 451         td028ttec1_panel_disable(dssdev);
 452         td028ttec1_panel_disconnect(dssdev);
 453
 454         omap_dss_put_device(in);
 455
 456         return 0;
 457 }
 458
 459 static const struct of_device_id td028ttec1_of_match[] = {
 460         { .compatible = "omapdss,toppoly,td028ttec1", },
 461         {},
 462 };
 463
 464 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
 465
 466 static struct spi_driver td028ttec1_spi_driver = {
 467         .probe          = td028ttec1_panel_probe,
 468         .remove         = td028ttec1_panel_remove,
 469
 470         .driver         = {
 471                 .name   = "panel-tpo-td028ttec1",
 472                 .of_match_table = td028ttec1_of_match,
 473                 .suppress_bind_attrs = true,
 474         },
 475 };
 476
 477 module_spi_driver(td028ttec1_spi_driver);
 478
 479 MODULE_ALIAS("spi:toppoly,td028ttec1");
 480 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
 481 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
 482 MODULE_LICENSE("GPL");