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mei: me: add cannon point device ids
[linux/fpc-iii.git] / drivers / net / can / flexcan.c
blob760d2c07e3a2c1edd15a2f70d20d1272adb3fd8a
1 /*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
7 * Copyright (c) 2014 David Jander, Protonic Holland
8 *
9 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
10 *
11 * LICENCE:
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 #include <linux/netdevice.h>
24 #include <linux/can.h>
25 #include <linux/can/dev.h>
26 #include <linux/can/error.h>
27 #include <linux/can/led.h>
28 #include <linux/can/rx-offload.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/module.h>
34 #include <linux/of.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/regulator/consumer.h>
38
39 #define DRV_NAME "flexcan"
40
41 /* 8 for RX fifo and 2 error handling */
42 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
43
44 /* FLEXCAN module configuration register (CANMCR) bits */
45 #define FLEXCAN_MCR_MDIS BIT(31)
46 #define FLEXCAN_MCR_FRZ BIT(30)
47 #define FLEXCAN_MCR_FEN BIT(29)
48 #define FLEXCAN_MCR_HALT BIT(28)
49 #define FLEXCAN_MCR_NOT_RDY BIT(27)
50 #define FLEXCAN_MCR_WAK_MSK BIT(26)
51 #define FLEXCAN_MCR_SOFTRST BIT(25)
52 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
53 #define FLEXCAN_MCR_SUPV BIT(23)
54 #define FLEXCAN_MCR_SLF_WAK BIT(22)
55 #define FLEXCAN_MCR_WRN_EN BIT(21)
56 #define FLEXCAN_MCR_LPM_ACK BIT(20)
57 #define FLEXCAN_MCR_WAK_SRC BIT(19)
58 #define FLEXCAN_MCR_DOZE BIT(18)
59 #define FLEXCAN_MCR_SRX_DIS BIT(17)
60 #define FLEXCAN_MCR_IRMQ BIT(16)
61 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
62 #define FLEXCAN_MCR_AEN BIT(12)
63 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
64 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
65 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
66 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
67 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
68 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
69
70 /* FLEXCAN control register (CANCTRL) bits */
71 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
72 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
73 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
74 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
75 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
76 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
77 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
78 #define FLEXCAN_CTRL_LPB BIT(12)
79 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
80 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
81 #define FLEXCAN_CTRL_SMP BIT(7)
82 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
83 #define FLEXCAN_CTRL_TSYN BIT(5)
84 #define FLEXCAN_CTRL_LBUF BIT(4)
85 #define FLEXCAN_CTRL_LOM BIT(3)
86 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
87 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
88 #define FLEXCAN_CTRL_ERR_STATE \
89 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
90 FLEXCAN_CTRL_BOFF_MSK)
91 #define FLEXCAN_CTRL_ERR_ALL \
92 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
93
94 /* FLEXCAN control register 2 (CTRL2) bits */
95 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
96 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
97 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
98 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
99 #define FLEXCAN_CTRL2_MRP BIT(18)
100 #define FLEXCAN_CTRL2_RRS BIT(17)
101 #define FLEXCAN_CTRL2_EACEN BIT(16)
102
103 /* FLEXCAN memory error control register (MECR) bits */
104 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
105 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
106 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
107 #define FLEXCAN_MECR_CEI_MSK BIT(16)
108 #define FLEXCAN_MECR_HAERRIE BIT(15)
109 #define FLEXCAN_MECR_FAERRIE BIT(14)
110 #define FLEXCAN_MECR_EXTERRIE BIT(13)
111 #define FLEXCAN_MECR_RERRDIS BIT(9)
112 #define FLEXCAN_MECR_ECCDIS BIT(8)
113 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
114
115 /* FLEXCAN error and status register (ESR) bits */
116 #define FLEXCAN_ESR_TWRN_INT BIT(17)
117 #define FLEXCAN_ESR_RWRN_INT BIT(16)
118 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
119 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
120 #define FLEXCAN_ESR_ACK_ERR BIT(13)
121 #define FLEXCAN_ESR_CRC_ERR BIT(12)
122 #define FLEXCAN_ESR_FRM_ERR BIT(11)
123 #define FLEXCAN_ESR_STF_ERR BIT(10)
124 #define FLEXCAN_ESR_TX_WRN BIT(9)
125 #define FLEXCAN_ESR_RX_WRN BIT(8)
126 #define FLEXCAN_ESR_IDLE BIT(7)
127 #define FLEXCAN_ESR_TXRX BIT(6)
128 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
129 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_BOFF_INT BIT(2)
133 #define FLEXCAN_ESR_ERR_INT BIT(1)
134 #define FLEXCAN_ESR_WAK_INT BIT(0)
135 #define FLEXCAN_ESR_ERR_BUS \
136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139 #define FLEXCAN_ESR_ERR_STATE \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141 #define FLEXCAN_ESR_ERR_ALL \
142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143 #define FLEXCAN_ESR_ALL_INT \
144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
146
147 /* FLEXCAN interrupt flag register (IFLAG) bits */
148 /* Errata ERR005829 step7: Reserve first valid MB */
149 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
150 #define FLEXCAN_TX_MB_OFF_FIFO 9
151 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
152 #define FLEXCAN_TX_MB_OFF_TIMESTAMP 1
153 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_OFF_TIMESTAMP + 1)
154 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST 63
155 #define FLEXCAN_IFLAG_MB(x) BIT(x)
156 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
157 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
158 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
159
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
162 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
163 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
164 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
165 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
166 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
167 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
168
169 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
170 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
171 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
172 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
173
174 #define FLEXCAN_MB_CNT_SRR BIT(22)
175 #define FLEXCAN_MB_CNT_IDE BIT(21)
176 #define FLEXCAN_MB_CNT_RTR BIT(20)
177 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
178 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
179
180 #define FLEXCAN_TIMEOUT_US (50)
181
182 /* FLEXCAN hardware feature flags
183 *
184 * Below is some version info we got:
185 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
186 * Filter? connected? Passive detection ception in MB
187 * MX25 FlexCAN2 03.00.00.00 no no no no no
188 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
189 * MX35 FlexCAN2 03.00.00.00 no no no no no
190 * MX53 FlexCAN2 03.00.00.00 yes no no no no
191 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
192 * VF610 FlexCAN3 ? no yes no yes yes?
193 *
194 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
195 */
196 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
197 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
198 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
199 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
200 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
201 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
202
203 /* Structure of the message buffer */
204 struct flexcan_mb {
205 u32 can_ctrl;
206 u32 can_id;
207 u32 data[2];
208 };
209
210 /* Structure of the hardware registers */
211 struct flexcan_regs {
212 u32 mcr; /* 0x00 */
213 u32 ctrl; /* 0x04 */
214 u32 timer; /* 0x08 */
215 u32 _reserved1; /* 0x0c */
216 u32 rxgmask; /* 0x10 */
217 u32 rx14mask; /* 0x14 */
218 u32 rx15mask; /* 0x18 */
219 u32 ecr; /* 0x1c */
220 u32 esr; /* 0x20 */
221 u32 imask2; /* 0x24 */
222 u32 imask1; /* 0x28 */
223 u32 iflag2; /* 0x2c */
224 u32 iflag1; /* 0x30 */
225 union { /* 0x34 */
226 u32 gfwr_mx28; /* MX28, MX53 */
227 u32 ctrl2; /* MX6, VF610 */
228 };
229 u32 esr2; /* 0x38 */
230 u32 imeur; /* 0x3c */
231 u32 lrfr; /* 0x40 */
232 u32 crcr; /* 0x44 */
233 u32 rxfgmask; /* 0x48 */
234 u32 rxfir; /* 0x4c */
235 u32 _reserved3[12]; /* 0x50 */
236 struct flexcan_mb mb[64]; /* 0x80 */
237 /* FIFO-mode:
238 * MB
239 * 0x080...0x08f 0 RX message buffer
240 * 0x090...0x0df 1-5 reserverd
241 * 0x0e0...0x0ff 6-7 8 entry ID table
242 * (mx25, mx28, mx35, mx53)
243 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
244 * size conf'ed via ctrl2::RFFN
245 * (mx6, vf610)
246 */
247 u32 _reserved4[256]; /* 0x480 */
248 u32 rximr[64]; /* 0x880 */
249 u32 _reserved5[24]; /* 0x980 */
250 u32 gfwr_mx6; /* 0x9e0 - MX6 */
251 u32 _reserved6[63]; /* 0x9e4 */
252 u32 mecr; /* 0xae0 */
253 u32 erriar; /* 0xae4 */
254 u32 erridpr; /* 0xae8 */
255 u32 errippr; /* 0xaec */
256 u32 rerrar; /* 0xaf0 */
257 u32 rerrdr; /* 0xaf4 */
258 u32 rerrsynr; /* 0xaf8 */
259 u32 errsr; /* 0xafc */
260 };
261
262 struct flexcan_devtype_data {
263 u32 quirks; /* quirks needed for different IP cores */
264 };
265
266 struct flexcan_priv {
267 struct can_priv can;
268 struct can_rx_offload offload;
269
270 struct flexcan_regs __iomem *regs;
271 struct flexcan_mb __iomem *tx_mb;
272 struct flexcan_mb __iomem *tx_mb_reserved;
273 u8 tx_mb_idx;
274 u32 reg_ctrl_default;
275 u32 reg_imask1_default;
276 u32 reg_imask2_default;
277
278 struct clk *clk_ipg;
279 struct clk *clk_per;
280 const struct flexcan_devtype_data *devtype_data;
281 struct regulator *reg_xceiver;
282 };
283
284 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
285 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
286 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
287 };
288
289 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
290 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
291 };
292
293 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
294 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
295 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
296 };
297
298 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
299 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
300 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
301 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
302 };
303
304 static const struct can_bittiming_const flexcan_bittiming_const = {
305 .name = DRV_NAME,
306 .tseg1_min = 4,
307 .tseg1_max = 16,
308 .tseg2_min = 2,
309 .tseg2_max = 8,
310 .sjw_max = 4,
311 .brp_min = 1,
312 .brp_max = 256,
313 .brp_inc = 1,
314 };
315
316 /* Abstract off the read/write for arm versus ppc. This
317 * assumes that PPC uses big-endian registers and everything
318 * else uses little-endian registers, independent of CPU
319 * endianness.
320 */
321 #if defined(CONFIG_PPC)
322 static inline u32 flexcan_read(void __iomem *addr)
323 {
324 return in_be32(addr);
325 }
326
327 static inline void flexcan_write(u32 val, void __iomem *addr)
328 {
329 out_be32(addr, val);
330 }
331 #else
332 static inline u32 flexcan_read(void __iomem *addr)
333 {
334 return readl(addr);
335 }
336
337 static inline void flexcan_write(u32 val, void __iomem *addr)
338 {
339 writel(val, addr);
340 }
341 #endif
342
343 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
344 {
345 struct flexcan_regs __iomem *regs = priv->regs;
346 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
347
348 flexcan_write(reg_ctrl, &regs->ctrl);
349 }
350
351 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
352 {
353 struct flexcan_regs __iomem *regs = priv->regs;
354 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
355
356 flexcan_write(reg_ctrl, &regs->ctrl);
357 }
358
359 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
360 {
361 if (!priv->reg_xceiver)
362 return 0;
363
364 return regulator_enable(priv->reg_xceiver);
365 }
366
367 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
368 {
369 if (!priv->reg_xceiver)
370 return 0;
371
372 return regulator_disable(priv->reg_xceiver);
373 }
374
375 static int flexcan_chip_enable(struct flexcan_priv *priv)
376 {
377 struct flexcan_regs __iomem *regs = priv->regs;
378 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
379 u32 reg;
380
381 reg = flexcan_read(&regs->mcr);
382 reg &= ~FLEXCAN_MCR_MDIS;
383 flexcan_write(reg, &regs->mcr);
384
385 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
386 udelay(10);
387
388 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
389 return -ETIMEDOUT;
390
391 return 0;
392 }
393
394 static int flexcan_chip_disable(struct flexcan_priv *priv)
395 {
396 struct flexcan_regs __iomem *regs = priv->regs;
397 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
398 u32 reg;
399
400 reg = flexcan_read(&regs->mcr);
401 reg |= FLEXCAN_MCR_MDIS;
402 flexcan_write(reg, &regs->mcr);
403
404 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
405 udelay(10);
406
407 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
408 return -ETIMEDOUT;
409
410 return 0;
411 }
412
413 static int flexcan_chip_freeze(struct flexcan_priv *priv)
414 {
415 struct flexcan_regs __iomem *regs = priv->regs;
416 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
417 u32 reg;
418
419 reg = flexcan_read(&regs->mcr);
420 reg |= FLEXCAN_MCR_HALT;
421 flexcan_write(reg, &regs->mcr);
422
423 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
424 udelay(100);
425
426 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
427 return -ETIMEDOUT;
428
429 return 0;
430 }
431
432 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
433 {
434 struct flexcan_regs __iomem *regs = priv->regs;
435 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
436 u32 reg;
437
438 reg = flexcan_read(&regs->mcr);
439 reg &= ~FLEXCAN_MCR_HALT;
440 flexcan_write(reg, &regs->mcr);
441
442 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
443 udelay(10);
444
445 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
446 return -ETIMEDOUT;
447
448 return 0;
449 }
450
451 static int flexcan_chip_softreset(struct flexcan_priv *priv)
452 {
453 struct flexcan_regs __iomem *regs = priv->regs;
454 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
455
456 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
457 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
458 udelay(10);
459
460 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
461 return -ETIMEDOUT;
462
463 return 0;
464 }
465
466 static int __flexcan_get_berr_counter(const struct net_device *dev,
467 struct can_berr_counter *bec)
468 {
469 const struct flexcan_priv *priv = netdev_priv(dev);
470 struct flexcan_regs __iomem *regs = priv->regs;
471 u32 reg = flexcan_read(&regs->ecr);
472
473 bec->txerr = (reg >> 0) & 0xff;
474 bec->rxerr = (reg >> 8) & 0xff;
475
476 return 0;
477 }
478
479 static int flexcan_get_berr_counter(const struct net_device *dev,
480 struct can_berr_counter *bec)
481 {
482 const struct flexcan_priv *priv = netdev_priv(dev);
483 int err;
484
485 err = clk_prepare_enable(priv->clk_ipg);
486 if (err)
487 return err;
488
489 err = clk_prepare_enable(priv->clk_per);
490 if (err)
491 goto out_disable_ipg;
492
493 err = __flexcan_get_berr_counter(dev, bec);
494
495 clk_disable_unprepare(priv->clk_per);
496 out_disable_ipg:
497 clk_disable_unprepare(priv->clk_ipg);
498
499 return err;
500 }
501
502 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
503 {
504 const struct flexcan_priv *priv = netdev_priv(dev);
505 struct can_frame *cf = (struct can_frame *)skb->data;
506 u32 can_id;
507 u32 data;
508 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
509
510 if (can_dropped_invalid_skb(dev, skb))
511 return NETDEV_TX_OK;
512
513 netif_stop_queue(dev);
514
515 if (cf->can_id & CAN_EFF_FLAG) {
516 can_id = cf->can_id & CAN_EFF_MASK;
517 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
518 } else {
519 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
520 }
521
522 if (cf->can_id & CAN_RTR_FLAG)
523 ctrl |= FLEXCAN_MB_CNT_RTR;
524
525 if (cf->can_dlc > 0) {
526 data = be32_to_cpup((__be32 *)&cf->data[0]);
527 flexcan_write(data, &priv->tx_mb->data[0]);
528 }
529 if (cf->can_dlc > 4) {
530 data = be32_to_cpup((__be32 *)&cf->data[4]);
531 flexcan_write(data, &priv->tx_mb->data[1]);
532 }
533
534 can_put_echo_skb(skb, dev, 0);
535
536 flexcan_write(can_id, &priv->tx_mb->can_id);
537 flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
538
539 /* Errata ERR005829 step8:
540 * Write twice INACTIVE(0x8) code to first MB.
541 */
542 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
543 &priv->tx_mb_reserved->can_ctrl);
544 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
545 &priv->tx_mb_reserved->can_ctrl);
546
547 return NETDEV_TX_OK;
548 }
549
550 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
551 {
552 struct flexcan_priv *priv = netdev_priv(dev);
553 struct sk_buff *skb;
554 struct can_frame *cf;
555 bool rx_errors = false, tx_errors = false;
556
557 skb = alloc_can_err_skb(dev, &cf);
558 if (unlikely(!skb))
559 return;
560
561 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
562
563 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
564 netdev_dbg(dev, "BIT1_ERR irq\n");
565 cf->data[2] |= CAN_ERR_PROT_BIT1;
566 tx_errors = true;
567 }
568 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
569 netdev_dbg(dev, "BIT0_ERR irq\n");
570 cf->data[2] |= CAN_ERR_PROT_BIT0;
571 tx_errors = true;
572 }
573 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
574 netdev_dbg(dev, "ACK_ERR irq\n");
575 cf->can_id |= CAN_ERR_ACK;
576 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
577 tx_errors = true;
578 }
579 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
580 netdev_dbg(dev, "CRC_ERR irq\n");
581 cf->data[2] |= CAN_ERR_PROT_BIT;
582 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
583 rx_errors = true;
584 }
585 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
586 netdev_dbg(dev, "FRM_ERR irq\n");
587 cf->data[2] |= CAN_ERR_PROT_FORM;
588 rx_errors = true;
589 }
590 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
591 netdev_dbg(dev, "STF_ERR irq\n");
592 cf->data[2] |= CAN_ERR_PROT_STUFF;
593 rx_errors = true;
594 }
595
596 priv->can.can_stats.bus_error++;
597 if (rx_errors)
598 dev->stats.rx_errors++;
599 if (tx_errors)
600 dev->stats.tx_errors++;
601
602 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
603 }
604
605 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
606 {
607 struct flexcan_priv *priv = netdev_priv(dev);
608 struct sk_buff *skb;
609 struct can_frame *cf;
610 enum can_state new_state, rx_state, tx_state;
611 int flt;
612 struct can_berr_counter bec;
613
614 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
615 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
616 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
617 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
618 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
619 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
620 new_state = max(tx_state, rx_state);
621 } else {
622 __flexcan_get_berr_counter(dev, &bec);
623 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
624 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
625 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
626 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
627 }
628
629 /* state hasn't changed */
630 if (likely(new_state == priv->can.state))
631 return;
632
633 skb = alloc_can_err_skb(dev, &cf);
634 if (unlikely(!skb))
635 return;
636
637 can_change_state(dev, cf, tx_state, rx_state);
638
639 if (unlikely(new_state == CAN_STATE_BUS_OFF))
640 can_bus_off(dev);
641
642 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
643 }
644
645 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
646 {
647 return container_of(offload, struct flexcan_priv, offload);
648 }
649
650 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
651 struct can_frame *cf,
652 u32 *timestamp, unsigned int n)
653 {
654 struct flexcan_priv *priv = rx_offload_to_priv(offload);
655 struct flexcan_regs __iomem *regs = priv->regs;
656 struct flexcan_mb __iomem *mb = &regs->mb[n];
657 u32 reg_ctrl, reg_id, reg_iflag1;
658
659 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
660 u32 code;
661
662 do {
663 reg_ctrl = flexcan_read(&mb->can_ctrl);
664 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
665
666 /* is this MB empty? */
667 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
668 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
669 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
670 return 0;
671
672 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
673 /* This MB was overrun, we lost data */
674 offload->dev->stats.rx_over_errors++;
675 offload->dev->stats.rx_errors++;
676 }
677 } else {
678 reg_iflag1 = flexcan_read(&regs->iflag1);
679 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
680 return 0;
681
682 reg_ctrl = flexcan_read(&mb->can_ctrl);
683 }
684
685 /* increase timstamp to full 32 bit */
686 *timestamp = reg_ctrl << 16;
687
688 reg_id = flexcan_read(&mb->can_id);
689 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
690 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
691 else
692 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
693
694 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
695 cf->can_id |= CAN_RTR_FLAG;
696 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
697
698 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
699 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
700
701 /* mark as read */
702 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
703 /* Clear IRQ */
704 if (n < 32)
705 flexcan_write(BIT(n), &regs->iflag1);
706 else
707 flexcan_write(BIT(n - 32), &regs->iflag2);
708 } else {
709 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
710 flexcan_read(&regs->timer);
711 }
712
713 return 1;
714 }
715
716
717 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
718 {
719 struct flexcan_regs __iomem *regs = priv->regs;
720 u32 iflag1, iflag2;
721
722 iflag2 = flexcan_read(&regs->iflag2) & priv->reg_imask2_default;
723 iflag1 = flexcan_read(&regs->iflag1) & priv->reg_imask1_default &
724 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
725
726 return (u64)iflag2 << 32 | iflag1;
727 }
728
729 static irqreturn_t flexcan_irq(int irq, void *dev_id)
730 {
731 struct net_device *dev = dev_id;
732 struct net_device_stats *stats = &dev->stats;
733 struct flexcan_priv *priv = netdev_priv(dev);
734 struct flexcan_regs __iomem *regs = priv->regs;
735 irqreturn_t handled = IRQ_NONE;
736 u32 reg_iflag1, reg_esr;
737 enum can_state last_state = priv->can.state;
738
739 reg_iflag1 = flexcan_read(&regs->iflag1);
740
741 /* reception interrupt */
742 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
743 u64 reg_iflag;
744 int ret;
745
746 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
747 handled = IRQ_HANDLED;
748 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
749 reg_iflag);
750 if (!ret)
751 break;
752 }
753 } else {
754 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
755 handled = IRQ_HANDLED;
756 can_rx_offload_irq_offload_fifo(&priv->offload);
757 }
758
759 /* FIFO overflow interrupt */
760 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
761 handled = IRQ_HANDLED;
762 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
763 dev->stats.rx_over_errors++;
764 dev->stats.rx_errors++;
765 }
766 }
767
768 /* transmission complete interrupt */
769 if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
770 handled = IRQ_HANDLED;
771 stats->tx_bytes += can_get_echo_skb(dev, 0);
772 stats->tx_packets++;
773 can_led_event(dev, CAN_LED_EVENT_TX);
774
775 /* after sending a RTR frame MB is in RX mode */
776 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
777 &priv->tx_mb->can_ctrl);
778 flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
779 netif_wake_queue(dev);
780 }
781
782 reg_esr = flexcan_read(&regs->esr);
783
784 /* ACK all bus error and state change IRQ sources */
785 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
786 handled = IRQ_HANDLED;
787 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
788 }
789
790 /* state change interrupt or broken error state quirk fix is enabled */
791 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
792 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
793 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
794 flexcan_irq_state(dev, reg_esr);
795
796 /* bus error IRQ - handle if bus error reporting is activated */
797 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
798 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
799 flexcan_irq_bus_err(dev, reg_esr);
800
801 /* availability of error interrupt among state transitions in case
802 * bus error reporting is de-activated and
803 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
804 * +--------------------------------------------------------------+
805 * | +----------------------------------------------+ [stopped / |
806 * | | | sleeping] -+
807 * +-+-> active <-> warning <-> passive -> bus off -+
808 * ___________^^^^^^^^^^^^_______________________________
809 * disabled(1) enabled disabled
810 *
811 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
812 */
813 if ((last_state != priv->can.state) &&
814 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
815 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
816 switch (priv->can.state) {
817 case CAN_STATE_ERROR_ACTIVE:
818 if (priv->devtype_data->quirks &
819 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
820 flexcan_error_irq_enable(priv);
821 else
822 flexcan_error_irq_disable(priv);
823 break;
824
825 case CAN_STATE_ERROR_WARNING:
826 flexcan_error_irq_enable(priv);
827 break;
828
829 case CAN_STATE_ERROR_PASSIVE:
830 case CAN_STATE_BUS_OFF:
831 flexcan_error_irq_disable(priv);
832 break;
833
834 default:
835 break;
836 }
837 }
838
839 return handled;
840 }
841
842 static void flexcan_set_bittiming(struct net_device *dev)
843 {
844 const struct flexcan_priv *priv = netdev_priv(dev);
845 const struct can_bittiming *bt = &priv->can.bittiming;
846 struct flexcan_regs __iomem *regs = priv->regs;
847 u32 reg;
848
849 reg = flexcan_read(&regs->ctrl);
850 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
851 FLEXCAN_CTRL_RJW(0x3) |
852 FLEXCAN_CTRL_PSEG1(0x7) |
853 FLEXCAN_CTRL_PSEG2(0x7) |
854 FLEXCAN_CTRL_PROPSEG(0x7) |
855 FLEXCAN_CTRL_LPB |
856 FLEXCAN_CTRL_SMP |
857 FLEXCAN_CTRL_LOM);
858
859 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
860 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
861 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
862 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
863 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
864
865 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
866 reg |= FLEXCAN_CTRL_LPB;
867 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
868 reg |= FLEXCAN_CTRL_LOM;
869 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
870 reg |= FLEXCAN_CTRL_SMP;
871
872 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
873 flexcan_write(reg, &regs->ctrl);
874
875 /* print chip status */
876 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
877 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
878 }
879
880 /* flexcan_chip_start
881 *
882 * this functions is entered with clocks enabled
883 *
884 */
885 static int flexcan_chip_start(struct net_device *dev)
886 {
887 struct flexcan_priv *priv = netdev_priv(dev);
888 struct flexcan_regs __iomem *regs = priv->regs;
889 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
890 int err, i;
891
892 /* enable module */
893 err = flexcan_chip_enable(priv);
894 if (err)
895 return err;
896
897 /* soft reset */
898 err = flexcan_chip_softreset(priv);
899 if (err)
900 goto out_chip_disable;
901
902 flexcan_set_bittiming(dev);
903
904 /* MCR
905 *
906 * enable freeze
907 * enable fifo
908 * halt now
909 * only supervisor access
910 * enable warning int
911 * disable local echo
912 * enable individual RX masking
913 * choose format C
914 * set max mailbox number
915 */
916 reg_mcr = flexcan_read(&regs->mcr);
917 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
918 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
919 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
920 FLEXCAN_MCR_IDAM_C;
921
922 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
923 reg_mcr &= ~FLEXCAN_MCR_FEN;
924 reg_mcr |= FLEXCAN_MCR_MAXMB(priv->offload.mb_last);
925 } else {
926 reg_mcr |= FLEXCAN_MCR_FEN |
927 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
928 }
929 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
930 flexcan_write(reg_mcr, &regs->mcr);
931
932 /* CTRL
933 *
934 * disable timer sync feature
935 *
936 * disable auto busoff recovery
937 * transmit lowest buffer first
938 *
939 * enable tx and rx warning interrupt
940 * enable bus off interrupt
941 * (== FLEXCAN_CTRL_ERR_STATE)
942 */
943 reg_ctrl = flexcan_read(&regs->ctrl);
944 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
945 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
946 FLEXCAN_CTRL_ERR_STATE;
947
948 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
949 * on most Flexcan cores, too. Otherwise we don't get
950 * any error warning or passive interrupts.
951 */
952 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
953 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
954 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
955 else
956 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
957
958 /* save for later use */
959 priv->reg_ctrl_default = reg_ctrl;
960 /* leave interrupts disabled for now */
961 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
962 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
963 flexcan_write(reg_ctrl, &regs->ctrl);
964
965 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
966 reg_ctrl2 = flexcan_read(&regs->ctrl2);
967 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
968 flexcan_write(reg_ctrl2, &regs->ctrl2);
969 }
970
971 /* clear and invalidate all mailboxes first */
972 for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
973 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
974 &regs->mb[i].can_ctrl);
975 }
976
977 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
978 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
979 flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
980 &regs->mb[i].can_ctrl);
981 }
982
983 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
984 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
985 &priv->tx_mb_reserved->can_ctrl);
986
987 /* mark TX mailbox as INACTIVE */
988 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
989 &priv->tx_mb->can_ctrl);
990
991 /* acceptance mask/acceptance code (accept everything) */
992 flexcan_write(0x0, &regs->rxgmask);
993 flexcan_write(0x0, &regs->rx14mask);
994 flexcan_write(0x0, &regs->rx15mask);
995
996 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
997 flexcan_write(0x0, &regs->rxfgmask);
998
999 /* clear acceptance filters */
1000 for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1001 flexcan_write(0, &regs->rximr[i]);
1002
1003 /* On Vybrid, disable memory error detection interrupts
1004 * and freeze mode.
1005 * This also works around errata e5295 which generates
1006 * false positive memory errors and put the device in
1007 * freeze mode.
1008 */
1009 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1010 /* Follow the protocol as described in "Detection
1011 * and Correction of Memory Errors" to write to
1012 * MECR register
1013 */
1014 reg_ctrl2 = flexcan_read(&regs->ctrl2);
1015 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1016 flexcan_write(reg_ctrl2, &regs->ctrl2);
1017
1018 reg_mecr = flexcan_read(&regs->mecr);
1019 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1020 flexcan_write(reg_mecr, &regs->mecr);
1021 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1022 FLEXCAN_MECR_FANCEI_MSK);
1023 flexcan_write(reg_mecr, &regs->mecr);
1024 }
1025
1026 err = flexcan_transceiver_enable(priv);
1027 if (err)
1028 goto out_chip_disable;
1029
1030 /* synchronize with the can bus */
1031 err = flexcan_chip_unfreeze(priv);
1032 if (err)
1033 goto out_transceiver_disable;
1034
1035 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1036
1037 /* enable interrupts atomically */
1038 disable_irq(dev->irq);
1039 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
1040 flexcan_write(priv->reg_imask1_default, &regs->imask1);
1041 flexcan_write(priv->reg_imask2_default, &regs->imask2);
1042 enable_irq(dev->irq);
1043
1044 /* print chip status */
1045 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1046 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
1047
1048 return 0;
1049
1050 out_transceiver_disable:
1051 flexcan_transceiver_disable(priv);
1052 out_chip_disable:
1053 flexcan_chip_disable(priv);
1054 return err;
1055 }
1056
1057 /* flexcan_chip_stop
1058 *
1059 * this functions is entered with clocks enabled
1060 */
1061 static void flexcan_chip_stop(struct net_device *dev)
1062 {
1063 struct flexcan_priv *priv = netdev_priv(dev);
1064 struct flexcan_regs __iomem *regs = priv->regs;
1065
1066 /* freeze + disable module */
1067 flexcan_chip_freeze(priv);
1068 flexcan_chip_disable(priv);
1069
1070 /* Disable all interrupts */
1071 flexcan_write(0, &regs->imask2);
1072 flexcan_write(0, &regs->imask1);
1073 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1074 &regs->ctrl);
1075
1076 flexcan_transceiver_disable(priv);
1077 priv->can.state = CAN_STATE_STOPPED;
1078 }
1079
1080 static int flexcan_open(struct net_device *dev)
1081 {
1082 struct flexcan_priv *priv = netdev_priv(dev);
1083 int err;
1084
1085 err = clk_prepare_enable(priv->clk_ipg);
1086 if (err)
1087 return err;
1088
1089 err = clk_prepare_enable(priv->clk_per);
1090 if (err)
1091 goto out_disable_ipg;
1092
1093 err = open_candev(dev);
1094 if (err)
1095 goto out_disable_per;
1096
1097 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1098 if (err)
1099 goto out_close;
1100
1101 /* start chip and queuing */
1102 err = flexcan_chip_start(dev);
1103 if (err)
1104 goto out_free_irq;
1105
1106 can_led_event(dev, CAN_LED_EVENT_OPEN);
1107
1108 can_rx_offload_enable(&priv->offload);
1109 netif_start_queue(dev);
1110
1111 return 0;
1112
1113 out_free_irq:
1114 free_irq(dev->irq, dev);
1115 out_close:
1116 close_candev(dev);
1117 out_disable_per:
1118 clk_disable_unprepare(priv->clk_per);
1119 out_disable_ipg:
1120 clk_disable_unprepare(priv->clk_ipg);
1121
1122 return err;
1123 }
1124
1125 static int flexcan_close(struct net_device *dev)
1126 {
1127 struct flexcan_priv *priv = netdev_priv(dev);
1128
1129 netif_stop_queue(dev);
1130 can_rx_offload_disable(&priv->offload);
1131 flexcan_chip_stop(dev);
1132
1133 free_irq(dev->irq, dev);
1134 clk_disable_unprepare(priv->clk_per);
1135 clk_disable_unprepare(priv->clk_ipg);
1136
1137 close_candev(dev);
1138
1139 can_led_event(dev, CAN_LED_EVENT_STOP);
1140
1141 return 0;
1142 }
1143
1144 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1145 {
1146 int err;
1147
1148 switch (mode) {
1149 case CAN_MODE_START:
1150 err = flexcan_chip_start(dev);
1151 if (err)
1152 return err;
1153
1154 netif_wake_queue(dev);
1155 break;
1156
1157 default:
1158 return -EOPNOTSUPP;
1159 }
1160
1161 return 0;
1162 }
1163
1164 static const struct net_device_ops flexcan_netdev_ops = {
1165 .ndo_open = flexcan_open,
1166 .ndo_stop = flexcan_close,
1167 .ndo_start_xmit = flexcan_start_xmit,
1168 .ndo_change_mtu = can_change_mtu,
1169 };
1170
1171 static int register_flexcandev(struct net_device *dev)
1172 {
1173 struct flexcan_priv *priv = netdev_priv(dev);
1174 struct flexcan_regs __iomem *regs = priv->regs;
1175 u32 reg, err;
1176
1177 err = clk_prepare_enable(priv->clk_ipg);
1178 if (err)
1179 return err;
1180
1181 err = clk_prepare_enable(priv->clk_per);
1182 if (err)
1183 goto out_disable_ipg;
1184
1185 /* select "bus clock", chip must be disabled */
1186 err = flexcan_chip_disable(priv);
1187 if (err)
1188 goto out_disable_per;
1189 reg = flexcan_read(&regs->ctrl);
1190 reg |= FLEXCAN_CTRL_CLK_SRC;
1191 flexcan_write(reg, &regs->ctrl);
1192
1193 err = flexcan_chip_enable(priv);
1194 if (err)
1195 goto out_chip_disable;
1196
1197 /* set freeze, halt and activate FIFO, restrict register access */
1198 reg = flexcan_read(&regs->mcr);
1199 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1200 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1201 flexcan_write(reg, &regs->mcr);
1202
1203 /* Currently we only support newer versions of this core
1204 * featuring a RX hardware FIFO (although this driver doesn't
1205 * make use of it on some cores). Older cores, found on some
1206 * Coldfire derivates are not tested.
1207 */
1208 reg = flexcan_read(&regs->mcr);
1209 if (!(reg & FLEXCAN_MCR_FEN)) {
1210 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1211 err = -ENODEV;
1212 goto out_chip_disable;
1213 }
1214
1215 err = register_candev(dev);
1216
1217 /* disable core and turn off clocks */
1218 out_chip_disable:
1219 flexcan_chip_disable(priv);
1220 out_disable_per:
1221 clk_disable_unprepare(priv->clk_per);
1222 out_disable_ipg:
1223 clk_disable_unprepare(priv->clk_ipg);
1224
1225 return err;
1226 }
1227
1228 static void unregister_flexcandev(struct net_device *dev)
1229 {
1230 unregister_candev(dev);
1231 }
1232
1233 static const struct of_device_id flexcan_of_match[] = {
1234 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1235 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1236 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1237 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1238 { /* sentinel */ },
1239 };
1240 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1241
1242 static const struct platform_device_id flexcan_id_table[] = {
1243 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1244 { /* sentinel */ },
1245 };
1246 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1247
1248 static int flexcan_probe(struct platform_device *pdev)
1249 {
1250 const struct of_device_id *of_id;
1251 const struct flexcan_devtype_data *devtype_data;
1252 struct net_device *dev;
1253 struct flexcan_priv *priv;
1254 struct regulator *reg_xceiver;
1255 struct resource *mem;
1256 struct clk *clk_ipg = NULL, *clk_per = NULL;
1257 struct flexcan_regs __iomem *regs;
1258 int err, irq;
1259 u32 clock_freq = 0;
1260
1261 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1262 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1263 return -EPROBE_DEFER;
1264 else if (IS_ERR(reg_xceiver))
1265 reg_xceiver = NULL;
1266
1267 if (pdev->dev.of_node)
1268 of_property_read_u32(pdev->dev.of_node,
1269 "clock-frequency", &clock_freq);
1270
1271 if (!clock_freq) {
1272 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1273 if (IS_ERR(clk_ipg)) {
1274 dev_err(&pdev->dev, "no ipg clock defined\n");
1275 return PTR_ERR(clk_ipg);
1276 }
1277
1278 clk_per = devm_clk_get(&pdev->dev, "per");
1279 if (IS_ERR(clk_per)) {
1280 dev_err(&pdev->dev, "no per clock defined\n");
1281 return PTR_ERR(clk_per);
1282 }
1283 clock_freq = clk_get_rate(clk_per);
1284 }
1285
1286 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1287 irq = platform_get_irq(pdev, 0);
1288 if (irq <= 0)
1289 return -ENODEV;
1290
1291 regs = devm_ioremap_resource(&pdev->dev, mem);
1292 if (IS_ERR(regs))
1293 return PTR_ERR(regs);
1294
1295 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1296 if (of_id) {
1297 devtype_data = of_id->data;
1298 } else if (platform_get_device_id(pdev)->driver_data) {
1299 devtype_data = (struct flexcan_devtype_data *)
1300 platform_get_device_id(pdev)->driver_data;
1301 } else {
1302 return -ENODEV;
1303 }
1304
1305 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1306 if (!dev)
1307 return -ENOMEM;
1308
1309 platform_set_drvdata(pdev, dev);
1310 SET_NETDEV_DEV(dev, &pdev->dev);
1311
1312 dev->netdev_ops = &flexcan_netdev_ops;
1313 dev->irq = irq;
1314 dev->flags |= IFF_ECHO;
1315
1316 priv = netdev_priv(dev);
1317 priv->can.clock.freq = clock_freq;
1318 priv->can.bittiming_const = &flexcan_bittiming_const;
1319 priv->can.do_set_mode = flexcan_set_mode;
1320 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1321 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1322 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1323 CAN_CTRLMODE_BERR_REPORTING;
1324 priv->regs = regs;
1325 priv->clk_ipg = clk_ipg;
1326 priv->clk_per = clk_per;
1327 priv->devtype_data = devtype_data;
1328 priv->reg_xceiver = reg_xceiver;
1329
1330 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1331 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_TIMESTAMP;
1332 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1333 } else {
1334 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
1335 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1336 }
1337 priv->tx_mb = &regs->mb[priv->tx_mb_idx];
1338
1339 priv->reg_imask1_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1340 priv->reg_imask2_default = 0;
1341
1342 priv->offload.mailbox_read = flexcan_mailbox_read;
1343
1344 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1345 u64 imask;
1346
1347 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1348 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1349
1350 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1351 priv->reg_imask1_default |= imask;
1352 priv->reg_imask2_default |= imask >> 32;
1353
1354 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1355 } else {
1356 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1357 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1358 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1359 }
1360 if (err)
1361 goto failed_offload;
1362
1363 err = register_flexcandev(dev);
1364 if (err) {
1365 dev_err(&pdev->dev, "registering netdev failed\n");
1366 goto failed_register;
1367 }
1368
1369 devm_can_led_init(dev);
1370
1371 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1372 priv->regs, dev->irq);
1373
1374 return 0;
1375
1376 failed_offload:
1377 failed_register:
1378 free_candev(dev);
1379 return err;
1380 }
1381
1382 static int flexcan_remove(struct platform_device *pdev)
1383 {
1384 struct net_device *dev = platform_get_drvdata(pdev);
1385 struct flexcan_priv *priv = netdev_priv(dev);
1386
1387 unregister_flexcandev(dev);
1388 can_rx_offload_del(&priv->offload);
1389 free_candev(dev);
1390
1391 return 0;
1392 }
1393
1394 static int __maybe_unused flexcan_suspend(struct device *device)
1395 {
1396 struct net_device *dev = dev_get_drvdata(device);
1397 struct flexcan_priv *priv = netdev_priv(dev);
1398 int err;
1399
1400 if (netif_running(dev)) {
1401 err = flexcan_chip_disable(priv);
1402 if (err)
1403 return err;
1404 netif_stop_queue(dev);
1405 netif_device_detach(dev);
1406 }
1407 priv->can.state = CAN_STATE_SLEEPING;
1408
1409 return 0;
1410 }
1411
1412 static int __maybe_unused flexcan_resume(struct device *device)
1413 {
1414 struct net_device *dev = dev_get_drvdata(device);
1415 struct flexcan_priv *priv = netdev_priv(dev);
1416 int err;
1417
1418 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1419 if (netif_running(dev)) {
1420 netif_device_attach(dev);
1421 netif_start_queue(dev);
1422 err = flexcan_chip_enable(priv);
1423 if (err)
1424 return err;
1425 }
1426 return 0;
1427 }
1428
1429 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1430
1431 static struct platform_driver flexcan_driver = {
1432 .driver = {
1433 .name = DRV_NAME,
1434 .pm = &flexcan_pm_ops,
1435 .of_match_table = flexcan_of_match,
1436 },
1437 .probe = flexcan_probe,
1438 .remove = flexcan_remove,
1439 .id_table = flexcan_id_table,
1440 };
1441
1442 module_platform_driver(flexcan_driver);
1443
1444 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1445 "Marc Kleine-Budde <kernel@pengutronix.de>");
1446 MODULE_LICENSE("GPL v2");
1447 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux with added FPC-III support