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mei: me: add cannon point device ids
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_os.c
blob46f2d0cf7c0d5db94576545db8e02971927879cb
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <linux/blk-mq-pci.h>
17 #include <scsi/scsi_tcq.h>
18 #include <scsi/scsicam.h>
19 #include <scsi/scsi_transport.h>
20 #include <scsi/scsi_transport_fc.h>
21
22 #include "qla_target.h"
23
24 /*
25 * Driver version
26 */
27 char qla2x00_version_str[40];
28
29 static int apidev_major;
30
31 /*
32 * SRB allocation cache
33 */
34 struct kmem_cache *srb_cachep;
35
36 /*
37 * CT6 CTX allocation cache
38 */
39 static struct kmem_cache *ctx_cachep;
40 /*
41 * error level for logging
42 */
43 int ql_errlev = ql_log_all;
44
45 static int ql2xenableclass2;
46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47 MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
51
52 int ql2xlogintimeout = 20;
53 module_param(ql2xlogintimeout, int, S_IRUGO);
54 MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
57 int qlport_down_retry;
58 module_param(qlport_down_retry, int, S_IRUGO);
59 MODULE_PARM_DESC(qlport_down_retry,
60 "Maximum number of command retries to a port that returns "
61 "a PORT-DOWN status.");
62
63 int ql2xplogiabsentdevice;
64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65 MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
67 "a Fabric scan. This is needed for several broken switches. "
68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
70 int ql2xloginretrycount = 0;
71 module_param(ql2xloginretrycount, int, S_IRUGO);
72 MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
75 int ql2xallocfwdump = 1;
76 module_param(ql2xallocfwdump, int, S_IRUGO);
77 MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
82 int ql2xextended_error_logging;
83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
85 MODULE_PARM_DESC(ql2xextended_error_logging,
86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
101 "\t\tDo LOGICAL OR of the value to enable more than one level");
102
103 int ql2xshiftctondsd = 6;
104 module_param(ql2xshiftctondsd, int, S_IRUGO);
105 MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
109 int ql2xfdmienable=1;
110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
112 MODULE_PARM_DESC(ql2xfdmienable,
113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
115
116 #define MAX_Q_DEPTH 64
117 static int ql2xmaxqdepth = MAX_Q_DEPTH;
118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119 MODULE_PARM_DESC(ql2xmaxqdepth,
120 "Maximum queue depth to set for each LUN. "
121 "Default is 64.");
122
123 #if (IS_ENABLED(CONFIG_NVME_FC))
124 int ql2xenabledif;
125 #else
126 int ql2xenabledif = 2;
127 #endif
128 module_param(ql2xenabledif, int, S_IRUGO);
129 MODULE_PARM_DESC(ql2xenabledif,
130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
135
136 #if (IS_ENABLED(CONFIG_NVME_FC))
137 int ql2xnvmeenable = 1;
138 #else
139 int ql2xnvmeenable;
140 #endif
141 module_param(ql2xnvmeenable, int, 0644);
142 MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
146 int ql2xenablehba_err_chk = 2;
147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148 MODULE_PARM_DESC(ql2xenablehba_err_chk,
149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
150 " Default is 2.\n"
151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
154
155 int ql2xiidmaenable=1;
156 module_param(ql2xiidmaenable, int, S_IRUGO);
157 MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
161 int ql2xmqsupport = 1;
162 module_param(ql2xmqsupport, int, S_IRUGO);
163 MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
167
168 int ql2xfwloadbin;
169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
171 MODULE_PARM_DESC(ql2xfwloadbin,
172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
178 int ql2xetsenable;
179 module_param(ql2xetsenable, int, S_IRUGO);
180 MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
184 int ql2xdbwr = 1;
185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
186 MODULE_PARM_DESC(ql2xdbwr,
187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
190
191 int ql2xtargetreset = 1;
192 module_param(ql2xtargetreset, int, S_IRUGO);
193 MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
197 int ql2xgffidenable;
198 module_param(ql2xgffidenable, int, S_IRUGO);
199 MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
202
203 int ql2xasynctmfenable = 1;
204 module_param(ql2xasynctmfenable, int, S_IRUGO);
205 MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
208
209 int ql2xdontresethba;
210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
211 MODULE_PARM_DESC(ql2xdontresethba,
212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
215
216 uint64_t ql2xmaxlun = MAX_LUNS;
217 module_param(ql2xmaxlun, ullong, S_IRUGO);
218 MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
222 int ql2xmdcapmask = 0x1F;
223 module_param(ql2xmdcapmask, int, S_IRUGO);
224 MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
227
228 int ql2xmdenable = 1;
229 module_param(ql2xmdenable, int, S_IRUGO);
230 MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
234
235 int ql2xexlogins = 0;
236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237 MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
241 int ql2xexchoffld = 1024;
242 module_param(ql2xexchoffld, uint, 0644);
243 MODULE_PARM_DESC(ql2xexchoffld,
244 "Number of target exchanges.");
245
246 int ql2xiniexchg = 1024;
247 module_param(ql2xiniexchg, uint, 0644);
248 MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
250
251 int ql2xfwholdabts = 0;
252 module_param(ql2xfwholdabts, int, S_IRUGO);
253 MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
258 int ql2xmvasynctoatio = 1;
259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260 MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
265 int ql2xautodetectsfp = 1;
266 module_param(ql2xautodetectsfp, int, 0444);
267 MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
271 int ql2xenablemsix = 1;
272 module_param(ql2xenablemsix, int, 0444);
273 MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
280 /*
281 * SCSI host template entry points
282 */
283 static int qla2xxx_slave_configure(struct scsi_device * device);
284 static int qla2xxx_slave_alloc(struct scsi_device *);
285 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
286 static void qla2xxx_scan_start(struct Scsi_Host *);
287 static void qla2xxx_slave_destroy(struct scsi_device *);
288 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
289 static int qla2xxx_eh_abort(struct scsi_cmnd *);
290 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
291 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
292 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
293 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
294
295 static void qla2x00_clear_drv_active(struct qla_hw_data *);
296 static void qla2x00_free_device(scsi_qla_host_t *);
297 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
298 static int qla2xxx_map_queues(struct Scsi_Host *shost);
299 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
300
301 struct scsi_host_template qla2xxx_driver_template = {
302 .module = THIS_MODULE,
303 .name = QLA2XXX_DRIVER_NAME,
304 .queuecommand = qla2xxx_queuecommand,
305
306 .eh_timed_out = fc_eh_timed_out,
307 .eh_abort_handler = qla2xxx_eh_abort,
308 .eh_device_reset_handler = qla2xxx_eh_device_reset,
309 .eh_target_reset_handler = qla2xxx_eh_target_reset,
310 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
311 .eh_host_reset_handler = qla2xxx_eh_host_reset,
312
313 .slave_configure = qla2xxx_slave_configure,
314
315 .slave_alloc = qla2xxx_slave_alloc,
316 .slave_destroy = qla2xxx_slave_destroy,
317 .scan_finished = qla2xxx_scan_finished,
318 .scan_start = qla2xxx_scan_start,
319 .change_queue_depth = scsi_change_queue_depth,
320 .map_queues = qla2xxx_map_queues,
321 .this_id = -1,
322 .cmd_per_lun = 3,
323 .use_clustering = ENABLE_CLUSTERING,
324 .sg_tablesize = SG_ALL,
325
326 .max_sectors = 0xFFFF,
327 .shost_attrs = qla2x00_host_attrs,
328
329 .supported_mode = MODE_INITIATOR,
330 .track_queue_depth = 1,
331 };
332
333 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
334 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
335
336 /* TODO Convert to inlines
337 *
338 * Timer routines
339 */
340
341 __inline__ void
342 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
343 {
344 timer_setup(&vha->timer, qla2x00_timer, 0);
345 vha->timer.expires = jiffies + interval * HZ;
346 add_timer(&vha->timer);
347 vha->timer_active = 1;
348 }
349
350 static inline void
351 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
352 {
353 /* Currently used for 82XX only. */
354 if (vha->device_flags & DFLG_DEV_FAILED) {
355 ql_dbg(ql_dbg_timer, vha, 0x600d,
356 "Device in a failed state, returning.\n");
357 return;
358 }
359
360 mod_timer(&vha->timer, jiffies + interval * HZ);
361 }
362
363 static __inline__ void
364 qla2x00_stop_timer(scsi_qla_host_t *vha)
365 {
366 del_timer_sync(&vha->timer);
367 vha->timer_active = 0;
368 }
369
370 static int qla2x00_do_dpc(void *data);
371
372 static void qla2x00_rst_aen(scsi_qla_host_t *);
373
374 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
375 struct req_que **, struct rsp_que **);
376 static void qla2x00_free_fw_dump(struct qla_hw_data *);
377 static void qla2x00_mem_free(struct qla_hw_data *);
378 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
379 struct qla_qpair *qpair);
380
381 /* -------------------------------------------------------------------------- */
382 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
383 struct rsp_que *rsp)
384 {
385 struct qla_hw_data *ha = vha->hw;
386 rsp->qpair = ha->base_qpair;
387 rsp->req = req;
388 ha->base_qpair->req = req;
389 ha->base_qpair->rsp = rsp;
390 ha->base_qpair->vha = vha;
391 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
392 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
393 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
394 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
395 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list);
396 ha->base_qpair->enable_class_2 = ql2xenableclass2;
397 /* init qpair to this cpu. Will adjust at run time. */
398 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
399 ha->base_qpair->pdev = ha->pdev;
400
401 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
402 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
403 }
404
405 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
406 struct rsp_que *rsp)
407 {
408 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
409 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
410 GFP_KERNEL);
411 if (!ha->req_q_map) {
412 ql_log(ql_log_fatal, vha, 0x003b,
413 "Unable to allocate memory for request queue ptrs.\n");
414 goto fail_req_map;
415 }
416
417 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
418 GFP_KERNEL);
419 if (!ha->rsp_q_map) {
420 ql_log(ql_log_fatal, vha, 0x003c,
421 "Unable to allocate memory for response queue ptrs.\n");
422 goto fail_rsp_map;
423 }
424
425 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
426 if (ha->base_qpair == NULL) {
427 ql_log(ql_log_warn, vha, 0x00e0,
428 "Failed to allocate base queue pair memory.\n");
429 goto fail_base_qpair;
430 }
431
432 qla_init_base_qpair(vha, req, rsp);
433
434 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
435 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
436 GFP_KERNEL);
437 if (!ha->queue_pair_map) {
438 ql_log(ql_log_fatal, vha, 0x0180,
439 "Unable to allocate memory for queue pair ptrs.\n");
440 goto fail_qpair_map;
441 }
442 }
443
444 /*
445 * Make sure we record at least the request and response queue zero in
446 * case we need to free them if part of the probe fails.
447 */
448 ha->rsp_q_map[0] = rsp;
449 ha->req_q_map[0] = req;
450 set_bit(0, ha->rsp_qid_map);
451 set_bit(0, ha->req_qid_map);
452 return 1;
453
454 fail_qpair_map:
455 kfree(ha->base_qpair);
456 ha->base_qpair = NULL;
457 fail_base_qpair:
458 kfree(ha->rsp_q_map);
459 ha->rsp_q_map = NULL;
460 fail_rsp_map:
461 kfree(ha->req_q_map);
462 ha->req_q_map = NULL;
463 fail_req_map:
464 return -ENOMEM;
465 }
466
467 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
468 {
469 if (IS_QLAFX00(ha)) {
470 if (req && req->ring_fx00)
471 dma_free_coherent(&ha->pdev->dev,
472 (req->length_fx00 + 1) * sizeof(request_t),
473 req->ring_fx00, req->dma_fx00);
474 } else if (req && req->ring)
475 dma_free_coherent(&ha->pdev->dev,
476 (req->length + 1) * sizeof(request_t),
477 req->ring, req->dma);
478
479 if (req)
480 kfree(req->outstanding_cmds);
481
482 kfree(req);
483 }
484
485 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
486 {
487 if (IS_QLAFX00(ha)) {
488 if (rsp && rsp->ring)
489 dma_free_coherent(&ha->pdev->dev,
490 (rsp->length_fx00 + 1) * sizeof(request_t),
491 rsp->ring_fx00, rsp->dma_fx00);
492 } else if (rsp && rsp->ring) {
493 dma_free_coherent(&ha->pdev->dev,
494 (rsp->length + 1) * sizeof(response_t),
495 rsp->ring, rsp->dma);
496 }
497 kfree(rsp);
498 }
499
500 static void qla2x00_free_queues(struct qla_hw_data *ha)
501 {
502 struct req_que *req;
503 struct rsp_que *rsp;
504 int cnt;
505 unsigned long flags;
506
507 if (ha->queue_pair_map) {
508 kfree(ha->queue_pair_map);
509 ha->queue_pair_map = NULL;
510 }
511 if (ha->base_qpair) {
512 kfree(ha->base_qpair);
513 ha->base_qpair = NULL;
514 }
515
516 spin_lock_irqsave(&ha->hardware_lock, flags);
517 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
518 if (!test_bit(cnt, ha->req_qid_map))
519 continue;
520
521 req = ha->req_q_map[cnt];
522 clear_bit(cnt, ha->req_qid_map);
523 ha->req_q_map[cnt] = NULL;
524
525 spin_unlock_irqrestore(&ha->hardware_lock, flags);
526 qla2x00_free_req_que(ha, req);
527 spin_lock_irqsave(&ha->hardware_lock, flags);
528 }
529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
530
531 kfree(ha->req_q_map);
532 ha->req_q_map = NULL;
533
534
535 spin_lock_irqsave(&ha->hardware_lock, flags);
536 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
537 if (!test_bit(cnt, ha->rsp_qid_map))
538 continue;
539
540 rsp = ha->rsp_q_map[cnt];
541 clear_bit(cnt, ha->rsp_qid_map);
542 ha->rsp_q_map[cnt] = NULL;
543 spin_unlock_irqrestore(&ha->hardware_lock, flags);
544 qla2x00_free_rsp_que(ha, rsp);
545 spin_lock_irqsave(&ha->hardware_lock, flags);
546 }
547 spin_unlock_irqrestore(&ha->hardware_lock, flags);
548
549 kfree(ha->rsp_q_map);
550 ha->rsp_q_map = NULL;
551 }
552
553 static char *
554 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
555 {
556 struct qla_hw_data *ha = vha->hw;
557 static char *pci_bus_modes[] = {
558 "33", "66", "100", "133",
559 };
560 uint16_t pci_bus;
561
562 strcpy(str, "PCI");
563 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
564 if (pci_bus) {
565 strcat(str, "-X (");
566 strcat(str, pci_bus_modes[pci_bus]);
567 } else {
568 pci_bus = (ha->pci_attr & BIT_8) >> 8;
569 strcat(str, " (");
570 strcat(str, pci_bus_modes[pci_bus]);
571 }
572 strcat(str, " MHz)");
573
574 return (str);
575 }
576
577 static char *
578 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
579 {
580 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
581 struct qla_hw_data *ha = vha->hw;
582 uint32_t pci_bus;
583
584 if (pci_is_pcie(ha->pdev)) {
585 char lwstr[6];
586 uint32_t lstat, lspeed, lwidth;
587
588 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
589 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
590 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
591
592 strcpy(str, "PCIe (");
593 switch (lspeed) {
594 case 1:
595 strcat(str, "2.5GT/s ");
596 break;
597 case 2:
598 strcat(str, "5.0GT/s ");
599 break;
600 case 3:
601 strcat(str, "8.0GT/s ");
602 break;
603 default:
604 strcat(str, "<unknown> ");
605 break;
606 }
607 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
608 strcat(str, lwstr);
609
610 return str;
611 }
612
613 strcpy(str, "PCI");
614 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
615 if (pci_bus == 0 || pci_bus == 8) {
616 strcat(str, " (");
617 strcat(str, pci_bus_modes[pci_bus >> 3]);
618 } else {
619 strcat(str, "-X ");
620 if (pci_bus & BIT_2)
621 strcat(str, "Mode 2");
622 else
623 strcat(str, "Mode 1");
624 strcat(str, " (");
625 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
626 }
627 strcat(str, " MHz)");
628
629 return str;
630 }
631
632 static char *
633 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
634 {
635 char un_str[10];
636 struct qla_hw_data *ha = vha->hw;
637
638 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
639 ha->fw_minor_version, ha->fw_subminor_version);
640
641 if (ha->fw_attributes & BIT_9) {
642 strcat(str, "FLX");
643 return (str);
644 }
645
646 switch (ha->fw_attributes & 0xFF) {
647 case 0x7:
648 strcat(str, "EF");
649 break;
650 case 0x17:
651 strcat(str, "TP");
652 break;
653 case 0x37:
654 strcat(str, "IP");
655 break;
656 case 0x77:
657 strcat(str, "VI");
658 break;
659 default:
660 sprintf(un_str, "(%x)", ha->fw_attributes);
661 strcat(str, un_str);
662 break;
663 }
664 if (ha->fw_attributes & 0x100)
665 strcat(str, "X");
666
667 return (str);
668 }
669
670 static char *
671 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
672 {
673 struct qla_hw_data *ha = vha->hw;
674
675 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
676 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
677 return str;
678 }
679
680 void
681 qla2x00_sp_free_dma(void *ptr)
682 {
683 srb_t *sp = ptr;
684 struct qla_hw_data *ha = sp->vha->hw;
685 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
686 void *ctx = GET_CMD_CTX_SP(sp);
687
688 if (sp->flags & SRB_DMA_VALID) {
689 scsi_dma_unmap(cmd);
690 sp->flags &= ~SRB_DMA_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
694 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
695 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
696 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
697 }
698
699 if (!ctx)
700 goto end;
701
702 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
703 /* List assured to be having elements */
704 qla2x00_clean_dsd_pool(ha, ctx);
705 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
706 }
707
708 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
709 struct crc_context *ctx0 = ctx;
710
711 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
712 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
713 }
714
715 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
716 struct ct6_dsd *ctx1 = ctx;
717
718 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
719 ctx1->fcp_cmnd_dma);
720 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
721 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
722 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
723 mempool_free(ctx1, ha->ctx_mempool);
724 }
725
726 end:
727 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
728 CMD_SP(cmd) = NULL;
729 qla2x00_rel_sp(sp);
730 }
731 }
732
733 void
734 qla2x00_sp_compl(void *ptr, int res)
735 {
736 srb_t *sp = ptr;
737 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
738
739 cmd->result = res;
740
741 if (atomic_read(&sp->ref_count) == 0) {
742 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
743 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
744 sp, GET_CMD_SP(sp));
745 if (ql2xextended_error_logging & ql_dbg_io)
746 WARN_ON(atomic_read(&sp->ref_count) == 0);
747 return;
748 }
749 if (!atomic_dec_and_test(&sp->ref_count))
750 return;
751
752 sp->free(sp);
753 cmd->scsi_done(cmd);
754 }
755
756 void
757 qla2xxx_qpair_sp_free_dma(void *ptr)
758 {
759 srb_t *sp = (srb_t *)ptr;
760 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
761 struct qla_hw_data *ha = sp->fcport->vha->hw;
762 void *ctx = GET_CMD_CTX_SP(sp);
763
764 if (sp->flags & SRB_DMA_VALID) {
765 scsi_dma_unmap(cmd);
766 sp->flags &= ~SRB_DMA_VALID;
767 }
768
769 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
770 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
771 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
772 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
773 }
774
775 if (!ctx)
776 goto end;
777
778 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
779 /* List assured to be having elements */
780 qla2x00_clean_dsd_pool(ha, ctx);
781 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
782 }
783
784 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
785 struct crc_context *ctx0 = ctx;
786
787 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
788 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
789 }
790
791 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
792 struct ct6_dsd *ctx1 = ctx;
793 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
794 ctx1->fcp_cmnd_dma);
795 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
796 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
797 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
798 mempool_free(ctx1, ha->ctx_mempool);
799 }
800 end:
801 CMD_SP(cmd) = NULL;
802 qla2xxx_rel_qpair_sp(sp->qpair, sp);
803 }
804
805 void
806 qla2xxx_qpair_sp_compl(void *ptr, int res)
807 {
808 srb_t *sp = ptr;
809 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
810
811 cmd->result = res;
812
813 if (atomic_read(&sp->ref_count) == 0) {
814 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
815 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
816 sp, GET_CMD_SP(sp));
817 if (ql2xextended_error_logging & ql_dbg_io)
818 WARN_ON(atomic_read(&sp->ref_count) == 0);
819 return;
820 }
821 if (!atomic_dec_and_test(&sp->ref_count))
822 return;
823
824 sp->free(sp);
825 cmd->scsi_done(cmd);
826 }
827
828 /* If we are SP1 here, we need to still take and release the host_lock as SP1
829 * does not have the changes necessary to avoid taking host->host_lock.
830 */
831 static int
832 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
833 {
834 scsi_qla_host_t *vha = shost_priv(host);
835 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
836 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
837 struct qla_hw_data *ha = vha->hw;
838 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
839 srb_t *sp;
840 int rval;
841 struct qla_qpair *qpair = NULL;
842 uint32_t tag;
843 uint16_t hwq;
844
845 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
846 cmd->result = DID_NO_CONNECT << 16;
847 goto qc24_fail_command;
848 }
849
850 if (ha->mqenable) {
851 if (shost_use_blk_mq(vha->host)) {
852 tag = blk_mq_unique_tag(cmd->request);
853 hwq = blk_mq_unique_tag_to_hwq(tag);
854 qpair = ha->queue_pair_map[hwq];
855 } else if (vha->vp_idx && vha->qpair) {
856 qpair = vha->qpair;
857 }
858
859 if (qpair)
860 return qla2xxx_mqueuecommand(host, cmd, qpair);
861 }
862
863 if (ha->flags.eeh_busy) {
864 if (ha->flags.pci_channel_io_perm_failure) {
865 ql_dbg(ql_dbg_aer, vha, 0x9010,
866 "PCI Channel IO permanent failure, exiting "
867 "cmd=%p.\n", cmd);
868 cmd->result = DID_NO_CONNECT << 16;
869 } else {
870 ql_dbg(ql_dbg_aer, vha, 0x9011,
871 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
872 cmd->result = DID_REQUEUE << 16;
873 }
874 goto qc24_fail_command;
875 }
876
877 rval = fc_remote_port_chkready(rport);
878 if (rval) {
879 cmd->result = rval;
880 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
881 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
882 cmd, rval);
883 goto qc24_fail_command;
884 }
885
886 if (!vha->flags.difdix_supported &&
887 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
888 ql_dbg(ql_dbg_io, vha, 0x3004,
889 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
890 cmd);
891 cmd->result = DID_NO_CONNECT << 16;
892 goto qc24_fail_command;
893 }
894
895 if (!fcport) {
896 cmd->result = DID_NO_CONNECT << 16;
897 goto qc24_fail_command;
898 }
899
900 if (atomic_read(&fcport->state) != FCS_ONLINE) {
901 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
902 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
903 ql_dbg(ql_dbg_io, vha, 0x3005,
904 "Returning DNC, fcport_state=%d loop_state=%d.\n",
905 atomic_read(&fcport->state),
906 atomic_read(&base_vha->loop_state));
907 cmd->result = DID_NO_CONNECT << 16;
908 goto qc24_fail_command;
909 }
910 goto qc24_target_busy;
911 }
912
913 /*
914 * Return target busy if we've received a non-zero retry_delay_timer
915 * in a FCP_RSP.
916 */
917 if (fcport->retry_delay_timestamp == 0) {
918 /* retry delay not set */
919 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
920 fcport->retry_delay_timestamp = 0;
921 else
922 goto qc24_target_busy;
923
924 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
925 if (!sp)
926 goto qc24_host_busy;
927
928 sp->u.scmd.cmd = cmd;
929 sp->type = SRB_SCSI_CMD;
930 atomic_set(&sp->ref_count, 1);
931 CMD_SP(cmd) = (void *)sp;
932 sp->free = qla2x00_sp_free_dma;
933 sp->done = qla2x00_sp_compl;
934
935 rval = ha->isp_ops->start_scsi(sp);
936 if (rval != QLA_SUCCESS) {
937 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
938 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
939 goto qc24_host_busy_free_sp;
940 }
941
942 return 0;
943
944 qc24_host_busy_free_sp:
945 sp->free(sp);
946
947 qc24_host_busy:
948 return SCSI_MLQUEUE_HOST_BUSY;
949
950 qc24_target_busy:
951 return SCSI_MLQUEUE_TARGET_BUSY;
952
953 qc24_fail_command:
954 cmd->scsi_done(cmd);
955
956 return 0;
957 }
958
959 /* For MQ supported I/O */
960 int
961 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
962 struct qla_qpair *qpair)
963 {
964 scsi_qla_host_t *vha = shost_priv(host);
965 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
966 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
967 struct qla_hw_data *ha = vha->hw;
968 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
969 srb_t *sp;
970 int rval;
971
972 rval = fc_remote_port_chkready(rport);
973 if (rval) {
974 cmd->result = rval;
975 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
976 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
977 cmd, rval);
978 goto qc24_fail_command;
979 }
980
981 if (!fcport) {
982 cmd->result = DID_NO_CONNECT << 16;
983 goto qc24_fail_command;
984 }
985
986 if (atomic_read(&fcport->state) != FCS_ONLINE) {
987 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
988 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
989 ql_dbg(ql_dbg_io, vha, 0x3077,
990 "Returning DNC, fcport_state=%d loop_state=%d.\n",
991 atomic_read(&fcport->state),
992 atomic_read(&base_vha->loop_state));
993 cmd->result = DID_NO_CONNECT << 16;
994 goto qc24_fail_command;
995 }
996 goto qc24_target_busy;
997 }
998
999 /*
1000 * Return target busy if we've received a non-zero retry_delay_timer
1001 * in a FCP_RSP.
1002 */
1003 if (fcport->retry_delay_timestamp == 0) {
1004 /* retry delay not set */
1005 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1006 fcport->retry_delay_timestamp = 0;
1007 else
1008 goto qc24_target_busy;
1009
1010 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1011 if (!sp)
1012 goto qc24_host_busy;
1013
1014 sp->u.scmd.cmd = cmd;
1015 sp->type = SRB_SCSI_CMD;
1016 atomic_set(&sp->ref_count, 1);
1017 CMD_SP(cmd) = (void *)sp;
1018 sp->free = qla2xxx_qpair_sp_free_dma;
1019 sp->done = qla2xxx_qpair_sp_compl;
1020 sp->qpair = qpair;
1021
1022 rval = ha->isp_ops->start_scsi_mq(sp);
1023 if (rval != QLA_SUCCESS) {
1024 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1025 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1026 if (rval == QLA_INTERFACE_ERROR)
1027 goto qc24_fail_command;
1028 goto qc24_host_busy_free_sp;
1029 }
1030
1031 return 0;
1032
1033 qc24_host_busy_free_sp:
1034 sp->free(sp);
1035
1036 qc24_host_busy:
1037 return SCSI_MLQUEUE_HOST_BUSY;
1038
1039 qc24_target_busy:
1040 return SCSI_MLQUEUE_TARGET_BUSY;
1041
1042 qc24_fail_command:
1043 cmd->scsi_done(cmd);
1044
1045 return 0;
1046 }
1047
1048 /*
1049 * qla2x00_eh_wait_on_command
1050 * Waits for the command to be returned by the Firmware for some
1051 * max time.
1052 *
1053 * Input:
1054 * cmd = Scsi Command to wait on.
1055 *
1056 * Return:
1057 * Not Found : 0
1058 * Found : 1
1059 */
1060 static int
1061 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1062 {
1063 #define ABORT_POLLING_PERIOD 1000
1064 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1065 unsigned long wait_iter = ABORT_WAIT_ITER;
1066 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1067 struct qla_hw_data *ha = vha->hw;
1068 int ret = QLA_SUCCESS;
1069
1070 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1071 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1072 "Return:eh_wait.\n");
1073 return ret;
1074 }
1075
1076 while (CMD_SP(cmd) && wait_iter--) {
1077 msleep(ABORT_POLLING_PERIOD);
1078 }
1079 if (CMD_SP(cmd))
1080 ret = QLA_FUNCTION_FAILED;
1081
1082 return ret;
1083 }
1084
1085 /*
1086 * qla2x00_wait_for_hba_online
1087 * Wait till the HBA is online after going through
1088 * <= MAX_RETRIES_OF_ISP_ABORT or
1089 * finally HBA is disabled ie marked offline
1090 *
1091 * Input:
1092 * ha - pointer to host adapter structure
1093 *
1094 * Note:
1095 * Does context switching-Release SPIN_LOCK
1096 * (if any) before calling this routine.
1097 *
1098 * Return:
1099 * Success (Adapter is online) : 0
1100 * Failed (Adapter is offline/disabled) : 1
1101 */
1102 int
1103 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1104 {
1105 int return_status;
1106 unsigned long wait_online;
1107 struct qla_hw_data *ha = vha->hw;
1108 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1109
1110 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1111 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1112 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1113 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1114 ha->dpc_active) && time_before(jiffies, wait_online)) {
1115
1116 msleep(1000);
1117 }
1118 if (base_vha->flags.online)
1119 return_status = QLA_SUCCESS;
1120 else
1121 return_status = QLA_FUNCTION_FAILED;
1122
1123 return (return_status);
1124 }
1125
1126 static inline int test_fcport_count(scsi_qla_host_t *vha)
1127 {
1128 struct qla_hw_data *ha = vha->hw;
1129 unsigned long flags;
1130 int res;
1131
1132 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1133 ql_dbg(ql_dbg_init, vha, 0x00ec,
1134 "tgt %p, fcport_count=%d\n",
1135 vha, vha->fcport_count);
1136 res = (vha->fcport_count == 0);
1137 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1138
1139 return res;
1140 }
1141
1142 /*
1143 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1144 * it has dependency on UNLOADING flag to stop device discovery
1145 */
1146 static void
1147 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1148 {
1149 qla2x00_mark_all_devices_lost(vha, 0);
1150
1151 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
1152 }
1153
1154 /*
1155 * qla2x00_wait_for_hba_ready
1156 * Wait till the HBA is ready before doing driver unload
1157 *
1158 * Input:
1159 * ha - pointer to host adapter structure
1160 *
1161 * Note:
1162 * Does context switching-Release SPIN_LOCK
1163 * (if any) before calling this routine.
1164 *
1165 */
1166 static void
1167 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1168 {
1169 struct qla_hw_data *ha = vha->hw;
1170 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1171
1172 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1173 ha->flags.mbox_busy) ||
1174 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1175 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1176 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1177 break;
1178 msleep(1000);
1179 }
1180 }
1181
1182 int
1183 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1184 {
1185 int return_status;
1186 unsigned long wait_reset;
1187 struct qla_hw_data *ha = vha->hw;
1188 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1189
1190 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1191 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1192 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1193 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1194 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1195
1196 msleep(1000);
1197
1198 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1199 ha->flags.chip_reset_done)
1200 break;
1201 }
1202 if (ha->flags.chip_reset_done)
1203 return_status = QLA_SUCCESS;
1204 else
1205 return_status = QLA_FUNCTION_FAILED;
1206
1207 return return_status;
1208 }
1209
1210 static void
1211 sp_get(struct srb *sp)
1212 {
1213 atomic_inc(&sp->ref_count);
1214 }
1215
1216 #define ISP_REG_DISCONNECT 0xffffffffU
1217 /**************************************************************************
1218 * qla2x00_isp_reg_stat
1219 *
1220 * Description:
1221 * Read the host status register of ISP before aborting the command.
1222 *
1223 * Input:
1224 * ha = pointer to host adapter structure.
1225 *
1226 *
1227 * Returns:
1228 * Either true or false.
1229 *
1230 * Note: Return true if there is register disconnect.
1231 **************************************************************************/
1232 static inline
1233 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1234 {
1235 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1236 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1237
1238 if (IS_P3P_TYPE(ha))
1239 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1240 else
1241 return ((RD_REG_DWORD(&reg->host_status)) ==
1242 ISP_REG_DISCONNECT);
1243 }
1244
1245 /**************************************************************************
1246 * qla2xxx_eh_abort
1247 *
1248 * Description:
1249 * The abort function will abort the specified command.
1250 *
1251 * Input:
1252 * cmd = Linux SCSI command packet to be aborted.
1253 *
1254 * Returns:
1255 * Either SUCCESS or FAILED.
1256 *
1257 * Note:
1258 * Only return FAILED if command not returned by firmware.
1259 **************************************************************************/
1260 static int
1261 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1262 {
1263 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1264 srb_t *sp;
1265 int ret;
1266 unsigned int id;
1267 uint64_t lun;
1268 unsigned long flags;
1269 int rval, wait = 0;
1270 struct qla_hw_data *ha = vha->hw;
1271
1272 if (qla2x00_isp_reg_stat(ha)) {
1273 ql_log(ql_log_info, vha, 0x8042,
1274 "PCI/Register disconnect, exiting.\n");
1275 return FAILED;
1276 }
1277 if (!CMD_SP(cmd))
1278 return SUCCESS;
1279
1280 ret = fc_block_scsi_eh(cmd);
1281 if (ret != 0)
1282 return ret;
1283 ret = SUCCESS;
1284
1285 id = cmd->device->id;
1286 lun = cmd->device->lun;
1287
1288 spin_lock_irqsave(&ha->hardware_lock, flags);
1289 sp = (srb_t *) CMD_SP(cmd);
1290 if (!sp) {
1291 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1292 return SUCCESS;
1293 }
1294
1295 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1296 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1297 vha->host_no, id, lun, sp, cmd, sp->handle);
1298
1299 /* Get a reference to the sp and drop the lock.*/
1300 sp_get(sp);
1301
1302 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1303 rval = ha->isp_ops->abort_command(sp);
1304 if (rval) {
1305 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
1306 ret = SUCCESS;
1307 else
1308 ret = FAILED;
1309
1310 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1311 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
1312 } else {
1313 ql_dbg(ql_dbg_taskm, vha, 0x8004,
1314 "Abort command mbx success cmd=%p.\n", cmd);
1315 wait = 1;
1316 }
1317
1318 spin_lock_irqsave(&ha->hardware_lock, flags);
1319 sp->done(sp, 0);
1320 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1321
1322 /* Did the command return during mailbox execution? */
1323 if (ret == FAILED && !CMD_SP(cmd))
1324 ret = SUCCESS;
1325
1326 /* Wait for the command to be returned. */
1327 if (wait) {
1328 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1329 ql_log(ql_log_warn, vha, 0x8006,
1330 "Abort handler timed out cmd=%p.\n", cmd);
1331 ret = FAILED;
1332 }
1333 }
1334
1335 ql_log(ql_log_info, vha, 0x801c,
1336 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1337 vha->host_no, id, lun, wait, ret);
1338
1339 return ret;
1340 }
1341
1342 int
1343 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1344 uint64_t l, enum nexus_wait_type type)
1345 {
1346 int cnt, match, status;
1347 unsigned long flags;
1348 struct qla_hw_data *ha = vha->hw;
1349 struct req_que *req;
1350 srb_t *sp;
1351 struct scsi_cmnd *cmd;
1352
1353 status = QLA_SUCCESS;
1354
1355 spin_lock_irqsave(&ha->hardware_lock, flags);
1356 req = vha->req;
1357 for (cnt = 1; status == QLA_SUCCESS &&
1358 cnt < req->num_outstanding_cmds; cnt++) {
1359 sp = req->outstanding_cmds[cnt];
1360 if (!sp)
1361 continue;
1362 if (sp->type != SRB_SCSI_CMD)
1363 continue;
1364 if (vha->vp_idx != sp->vha->vp_idx)
1365 continue;
1366 match = 0;
1367 cmd = GET_CMD_SP(sp);
1368 switch (type) {
1369 case WAIT_HOST:
1370 match = 1;
1371 break;
1372 case WAIT_TARGET:
1373 match = cmd->device->id == t;
1374 break;
1375 case WAIT_LUN:
1376 match = (cmd->device->id == t &&
1377 cmd->device->lun == l);
1378 break;
1379 }
1380 if (!match)
1381 continue;
1382
1383 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1384 status = qla2x00_eh_wait_on_command(cmd);
1385 spin_lock_irqsave(&ha->hardware_lock, flags);
1386 }
1387 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1388
1389 return status;
1390 }
1391
1392 static char *reset_errors[] = {
1393 "HBA not online",
1394 "HBA not ready",
1395 "Task management failed",
1396 "Waiting for command completions",
1397 };
1398
1399 static int
1400 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1401 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1402 {
1403 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1404 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1405 int err;
1406
1407 if (!fcport) {
1408 return FAILED;
1409 }
1410
1411 err = fc_block_scsi_eh(cmd);
1412 if (err != 0)
1413 return err;
1414
1415 ql_log(ql_log_info, vha, 0x8009,
1416 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1417 cmd->device->id, cmd->device->lun, cmd);
1418
1419 err = 0;
1420 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1421 ql_log(ql_log_warn, vha, 0x800a,
1422 "Wait for hba online failed for cmd=%p.\n", cmd);
1423 goto eh_reset_failed;
1424 }
1425 err = 2;
1426 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1427 != QLA_SUCCESS) {
1428 ql_log(ql_log_warn, vha, 0x800c,
1429 "do_reset failed for cmd=%p.\n", cmd);
1430 goto eh_reset_failed;
1431 }
1432 err = 3;
1433 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1434 cmd->device->lun, type) != QLA_SUCCESS) {
1435 ql_log(ql_log_warn, vha, 0x800d,
1436 "wait for pending cmds failed for cmd=%p.\n", cmd);
1437 goto eh_reset_failed;
1438 }
1439
1440 ql_log(ql_log_info, vha, 0x800e,
1441 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1442 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1443
1444 return SUCCESS;
1445
1446 eh_reset_failed:
1447 ql_log(ql_log_info, vha, 0x800f,
1448 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1449 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1450 cmd);
1451 return FAILED;
1452 }
1453
1454 static int
1455 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1456 {
1457 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1458 struct qla_hw_data *ha = vha->hw;
1459
1460 if (qla2x00_isp_reg_stat(ha)) {
1461 ql_log(ql_log_info, vha, 0x803e,
1462 "PCI/Register disconnect, exiting.\n");
1463 return FAILED;
1464 }
1465
1466 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1467 ha->isp_ops->lun_reset);
1468 }
1469
1470 static int
1471 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1472 {
1473 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1474 struct qla_hw_data *ha = vha->hw;
1475
1476 if (qla2x00_isp_reg_stat(ha)) {
1477 ql_log(ql_log_info, vha, 0x803f,
1478 "PCI/Register disconnect, exiting.\n");
1479 return FAILED;
1480 }
1481
1482 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1483 ha->isp_ops->target_reset);
1484 }
1485
1486 /**************************************************************************
1487 * qla2xxx_eh_bus_reset
1488 *
1489 * Description:
1490 * The bus reset function will reset the bus and abort any executing
1491 * commands.
1492 *
1493 * Input:
1494 * cmd = Linux SCSI command packet of the command that cause the
1495 * bus reset.
1496 *
1497 * Returns:
1498 * SUCCESS/FAILURE (defined as macro in scsi.h).
1499 *
1500 **************************************************************************/
1501 static int
1502 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1503 {
1504 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1505 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1506 int ret = FAILED;
1507 unsigned int id;
1508 uint64_t lun;
1509 struct qla_hw_data *ha = vha->hw;
1510
1511 if (qla2x00_isp_reg_stat(ha)) {
1512 ql_log(ql_log_info, vha, 0x8040,
1513 "PCI/Register disconnect, exiting.\n");
1514 return FAILED;
1515 }
1516
1517 id = cmd->device->id;
1518 lun = cmd->device->lun;
1519
1520 if (!fcport) {
1521 return ret;
1522 }
1523
1524 ret = fc_block_scsi_eh(cmd);
1525 if (ret != 0)
1526 return ret;
1527 ret = FAILED;
1528
1529 ql_log(ql_log_info, vha, 0x8012,
1530 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1531
1532 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1533 ql_log(ql_log_fatal, vha, 0x8013,
1534 "Wait for hba online failed board disabled.\n");
1535 goto eh_bus_reset_done;
1536 }
1537
1538 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1539 ret = SUCCESS;
1540
1541 if (ret == FAILED)
1542 goto eh_bus_reset_done;
1543
1544 /* Flush outstanding commands. */
1545 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1546 QLA_SUCCESS) {
1547 ql_log(ql_log_warn, vha, 0x8014,
1548 "Wait for pending commands failed.\n");
1549 ret = FAILED;
1550 }
1551
1552 eh_bus_reset_done:
1553 ql_log(ql_log_warn, vha, 0x802b,
1554 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1555 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1556
1557 return ret;
1558 }
1559
1560 /**************************************************************************
1561 * qla2xxx_eh_host_reset
1562 *
1563 * Description:
1564 * The reset function will reset the Adapter.
1565 *
1566 * Input:
1567 * cmd = Linux SCSI command packet of the command that cause the
1568 * adapter reset.
1569 *
1570 * Returns:
1571 * Either SUCCESS or FAILED.
1572 *
1573 * Note:
1574 **************************************************************************/
1575 static int
1576 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1577 {
1578 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1579 struct qla_hw_data *ha = vha->hw;
1580 int ret = FAILED;
1581 unsigned int id;
1582 uint64_t lun;
1583 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1584
1585 if (qla2x00_isp_reg_stat(ha)) {
1586 ql_log(ql_log_info, vha, 0x8041,
1587 "PCI/Register disconnect, exiting.\n");
1588 schedule_work(&ha->board_disable);
1589 return SUCCESS;
1590 }
1591
1592 id = cmd->device->id;
1593 lun = cmd->device->lun;
1594
1595 ql_log(ql_log_info, vha, 0x8018,
1596 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1597
1598 /*
1599 * No point in issuing another reset if one is active. Also do not
1600 * attempt a reset if we are updating flash.
1601 */
1602 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1603 goto eh_host_reset_lock;
1604
1605 if (vha != base_vha) {
1606 if (qla2x00_vp_abort_isp(vha))
1607 goto eh_host_reset_lock;
1608 } else {
1609 if (IS_P3P_TYPE(vha->hw)) {
1610 if (!qla82xx_fcoe_ctx_reset(vha)) {
1611 /* Ctx reset success */
1612 ret = SUCCESS;
1613 goto eh_host_reset_lock;
1614 }
1615 /* fall thru if ctx reset failed */
1616 }
1617 if (ha->wq)
1618 flush_workqueue(ha->wq);
1619
1620 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1621 if (ha->isp_ops->abort_isp(base_vha)) {
1622 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1623 /* failed. schedule dpc to try */
1624 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1625
1626 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1627 ql_log(ql_log_warn, vha, 0x802a,
1628 "wait for hba online failed.\n");
1629 goto eh_host_reset_lock;
1630 }
1631 }
1632 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1633 }
1634
1635 /* Waiting for command to be returned to OS.*/
1636 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1637 QLA_SUCCESS)
1638 ret = SUCCESS;
1639
1640 eh_host_reset_lock:
1641 ql_log(ql_log_info, vha, 0x8017,
1642 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1643 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1644
1645 return ret;
1646 }
1647
1648 /*
1649 * qla2x00_loop_reset
1650 * Issue loop reset.
1651 *
1652 * Input:
1653 * ha = adapter block pointer.
1654 *
1655 * Returns:
1656 * 0 = success
1657 */
1658 int
1659 qla2x00_loop_reset(scsi_qla_host_t *vha)
1660 {
1661 int ret;
1662 struct fc_port *fcport;
1663 struct qla_hw_data *ha = vha->hw;
1664
1665 if (IS_QLAFX00(ha)) {
1666 return qlafx00_loop_reset(vha);
1667 }
1668
1669 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1670 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1671 if (fcport->port_type != FCT_TARGET)
1672 continue;
1673
1674 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1675 if (ret != QLA_SUCCESS) {
1676 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1677 "Bus Reset failed: Reset=%d "
1678 "d_id=%x.\n", ret, fcport->d_id.b24);
1679 }
1680 }
1681 }
1682
1683
1684 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1685 atomic_set(&vha->loop_state, LOOP_DOWN);
1686 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1687 qla2x00_mark_all_devices_lost(vha, 0);
1688 ret = qla2x00_full_login_lip(vha);
1689 if (ret != QLA_SUCCESS) {
1690 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1691 "full_login_lip=%d.\n", ret);
1692 }
1693 }
1694
1695 if (ha->flags.enable_lip_reset) {
1696 ret = qla2x00_lip_reset(vha);
1697 if (ret != QLA_SUCCESS)
1698 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1699 "lip_reset failed (%d).\n", ret);
1700 }
1701
1702 /* Issue marker command only when we are going to start the I/O */
1703 vha->marker_needed = 1;
1704
1705 return QLA_SUCCESS;
1706 }
1707
1708 void
1709 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1710 {
1711 int que, cnt, status;
1712 unsigned long flags;
1713 srb_t *sp;
1714 struct qla_hw_data *ha = vha->hw;
1715 struct req_que *req;
1716 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1717 struct qla_tgt_cmd *cmd;
1718 uint8_t trace = 0;
1719
1720 spin_lock_irqsave(&ha->hardware_lock, flags);
1721 for (que = 0; que < ha->max_req_queues; que++) {
1722 req = ha->req_q_map[que];
1723 if (!req)
1724 continue;
1725 if (!req->outstanding_cmds)
1726 continue;
1727 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1728 sp = req->outstanding_cmds[cnt];
1729 if (sp) {
1730 req->outstanding_cmds[cnt] = NULL;
1731 if (sp->cmd_type == TYPE_SRB) {
1732 if (sp->type == SRB_NVME_CMD ||
1733 sp->type == SRB_NVME_LS) {
1734 sp_get(sp);
1735 spin_unlock_irqrestore(
1736 &ha->hardware_lock, flags);
1737 qla_nvme_abort(ha, sp);
1738 spin_lock_irqsave(
1739 &ha->hardware_lock, flags);
1740 } else if (GET_CMD_SP(sp) &&
1741 !ha->flags.eeh_busy &&
1742 (!test_bit(ABORT_ISP_ACTIVE,
1743 &vha->dpc_flags)) &&
1744 (sp->type == SRB_SCSI_CMD)) {
1745 /*
1746 * Don't abort commands in
1747 * adapter during EEH
1748 * recovery as it's not
1749 * accessible/responding.
1750 *
1751 * Get a reference to the sp
1752 * and drop the lock. The
1753 * reference ensures this
1754 * sp->done() call and not the
1755 * call in qla2xxx_eh_abort()
1756 * ends the SCSI command (with
1757 * result 'res').
1758 */
1759 sp_get(sp);
1760 spin_unlock_irqrestore(
1761 &ha->hardware_lock, flags);
1762 status = qla2xxx_eh_abort(
1763 GET_CMD_SP(sp));
1764 spin_lock_irqsave(
1765 &ha->hardware_lock, flags);
1766 /*
1767 * Get rid of extra reference
1768 * if immediate exit from
1769 * ql2xxx_eh_abort
1770 */
1771 if (status == FAILED &&
1772 (qla2x00_isp_reg_stat(ha)))
1773 atomic_dec(
1774 &sp->ref_count);
1775 }
1776 sp->done(sp, res);
1777 } else {
1778 if (!vha->hw->tgt.tgt_ops || !tgt ||
1779 qla_ini_mode_enabled(vha)) {
1780 if (!trace)
1781 ql_dbg(ql_dbg_tgt_mgt,
1782 vha, 0xf003,
1783 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1784 vha->dpc_flags);
1785 continue;
1786 }
1787 cmd = (struct qla_tgt_cmd *)sp;
1788 qlt_abort_cmd_on_host_reset(cmd->vha,
1789 cmd);
1790 }
1791 }
1792 }
1793 }
1794 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1795 }
1796
1797 static int
1798 qla2xxx_slave_alloc(struct scsi_device *sdev)
1799 {
1800 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1801
1802 if (!rport || fc_remote_port_chkready(rport))
1803 return -ENXIO;
1804
1805 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1806
1807 return 0;
1808 }
1809
1810 static int
1811 qla2xxx_slave_configure(struct scsi_device *sdev)
1812 {
1813 scsi_qla_host_t *vha = shost_priv(sdev->host);
1814 struct req_que *req = vha->req;
1815
1816 if (IS_T10_PI_CAPABLE(vha->hw))
1817 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1818
1819 scsi_change_queue_depth(sdev, req->max_q_depth);
1820 return 0;
1821 }
1822
1823 static void
1824 qla2xxx_slave_destroy(struct scsi_device *sdev)
1825 {
1826 sdev->hostdata = NULL;
1827 }
1828
1829 /**
1830 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1831 * @ha: HA context
1832 *
1833 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1834 * supported addressing method.
1835 */
1836 static void
1837 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1838 {
1839 /* Assume a 32bit DMA mask. */
1840 ha->flags.enable_64bit_addressing = 0;
1841
1842 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1843 /* Any upper-dword bits set? */
1844 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1845 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1846 /* Ok, a 64bit DMA mask is applicable. */
1847 ha->flags.enable_64bit_addressing = 1;
1848 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1849 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1850 return;
1851 }
1852 }
1853
1854 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1855 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1856 }
1857
1858 static void
1859 qla2x00_enable_intrs(struct qla_hw_data *ha)
1860 {
1861 unsigned long flags = 0;
1862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1863
1864 spin_lock_irqsave(&ha->hardware_lock, flags);
1865 ha->interrupts_on = 1;
1866 /* enable risc and host interrupts */
1867 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1868 RD_REG_WORD(&reg->ictrl);
1869 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1870
1871 }
1872
1873 static void
1874 qla2x00_disable_intrs(struct qla_hw_data *ha)
1875 {
1876 unsigned long flags = 0;
1877 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1878
1879 spin_lock_irqsave(&ha->hardware_lock, flags);
1880 ha->interrupts_on = 0;
1881 /* disable risc and host interrupts */
1882 WRT_REG_WORD(&reg->ictrl, 0);
1883 RD_REG_WORD(&reg->ictrl);
1884 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1885 }
1886
1887 static void
1888 qla24xx_enable_intrs(struct qla_hw_data *ha)
1889 {
1890 unsigned long flags = 0;
1891 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1892
1893 spin_lock_irqsave(&ha->hardware_lock, flags);
1894 ha->interrupts_on = 1;
1895 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1896 RD_REG_DWORD(&reg->ictrl);
1897 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1898 }
1899
1900 static void
1901 qla24xx_disable_intrs(struct qla_hw_data *ha)
1902 {
1903 unsigned long flags = 0;
1904 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1905
1906 if (IS_NOPOLLING_TYPE(ha))
1907 return;
1908 spin_lock_irqsave(&ha->hardware_lock, flags);
1909 ha->interrupts_on = 0;
1910 WRT_REG_DWORD(&reg->ictrl, 0);
1911 RD_REG_DWORD(&reg->ictrl);
1912 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1913 }
1914
1915 static int
1916 qla2x00_iospace_config(struct qla_hw_data *ha)
1917 {
1918 resource_size_t pio;
1919 uint16_t msix;
1920
1921 if (pci_request_selected_regions(ha->pdev, ha->bars,
1922 QLA2XXX_DRIVER_NAME)) {
1923 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1924 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1925 pci_name(ha->pdev));
1926 goto iospace_error_exit;
1927 }
1928 if (!(ha->bars & 1))
1929 goto skip_pio;
1930
1931 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1932 pio = pci_resource_start(ha->pdev, 0);
1933 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1934 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1935 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1936 "Invalid pci I/O region size (%s).\n",
1937 pci_name(ha->pdev));
1938 pio = 0;
1939 }
1940 } else {
1941 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1942 "Region #0 no a PIO resource (%s).\n",
1943 pci_name(ha->pdev));
1944 pio = 0;
1945 }
1946 ha->pio_address = pio;
1947 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1948 "PIO address=%llu.\n",
1949 (unsigned long long)ha->pio_address);
1950
1951 skip_pio:
1952 /* Use MMIO operations for all accesses. */
1953 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1954 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1955 "Region #1 not an MMIO resource (%s), aborting.\n",
1956 pci_name(ha->pdev));
1957 goto iospace_error_exit;
1958 }
1959 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1960 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1961 "Invalid PCI mem region size (%s), aborting.\n",
1962 pci_name(ha->pdev));
1963 goto iospace_error_exit;
1964 }
1965
1966 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1967 if (!ha->iobase) {
1968 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1969 "Cannot remap MMIO (%s), aborting.\n",
1970 pci_name(ha->pdev));
1971 goto iospace_error_exit;
1972 }
1973
1974 /* Determine queue resources */
1975 ha->max_req_queues = ha->max_rsp_queues = 1;
1976 ha->msix_count = QLA_BASE_VECTORS;
1977 if (!ql2xmqsupport || !ql2xnvmeenable ||
1978 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1979 goto mqiobase_exit;
1980
1981 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1982 pci_resource_len(ha->pdev, 3));
1983 if (ha->mqiobase) {
1984 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1985 "MQIO Base=%p.\n", ha->mqiobase);
1986 /* Read MSIX vector size of the board */
1987 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1988 ha->msix_count = msix + 1;
1989 /* Max queues are bounded by available msix vectors */
1990 /* MB interrupt uses 1 vector */
1991 ha->max_req_queues = ha->msix_count - 1;
1992 ha->max_rsp_queues = ha->max_req_queues;
1993 /* Queue pairs is the max value minus the base queue pair */
1994 ha->max_qpairs = ha->max_rsp_queues - 1;
1995 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1996 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1997
1998 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1999 "MSI-X vector count: %d.\n", ha->msix_count);
2000 } else
2001 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2002 "BAR 3 not enabled.\n");
2003
2004 mqiobase_exit:
2005 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2006 "MSIX Count: %d.\n", ha->msix_count);
2007 return (0);
2008
2009 iospace_error_exit:
2010 return (-ENOMEM);
2011 }
2012
2013
2014 static int
2015 qla83xx_iospace_config(struct qla_hw_data *ha)
2016 {
2017 uint16_t msix;
2018
2019 if (pci_request_selected_regions(ha->pdev, ha->bars,
2020 QLA2XXX_DRIVER_NAME)) {
2021 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2022 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2023 pci_name(ha->pdev));
2024
2025 goto iospace_error_exit;
2026 }
2027
2028 /* Use MMIO operations for all accesses. */
2029 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2030 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2031 "Invalid pci I/O region size (%s).\n",
2032 pci_name(ha->pdev));
2033 goto iospace_error_exit;
2034 }
2035 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2036 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2037 "Invalid PCI mem region size (%s), aborting\n",
2038 pci_name(ha->pdev));
2039 goto iospace_error_exit;
2040 }
2041
2042 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2043 if (!ha->iobase) {
2044 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2045 "Cannot remap MMIO (%s), aborting.\n",
2046 pci_name(ha->pdev));
2047 goto iospace_error_exit;
2048 }
2049
2050 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2051 /* 83XX 26XX always use MQ type access for queues
2052 * - mbar 2, a.k.a region 4 */
2053 ha->max_req_queues = ha->max_rsp_queues = 1;
2054 ha->msix_count = QLA_BASE_VECTORS;
2055 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2056 pci_resource_len(ha->pdev, 4));
2057
2058 if (!ha->mqiobase) {
2059 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2060 "BAR2/region4 not enabled\n");
2061 goto mqiobase_exit;
2062 }
2063
2064 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2065 pci_resource_len(ha->pdev, 2));
2066 if (ha->msixbase) {
2067 /* Read MSIX vector size of the board */
2068 pci_read_config_word(ha->pdev,
2069 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2070 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2071 /*
2072 * By default, driver uses at least two msix vectors
2073 * (default & rspq)
2074 */
2075 if (ql2xmqsupport || ql2xnvmeenable) {
2076 /* MB interrupt uses 1 vector */
2077 ha->max_req_queues = ha->msix_count - 1;
2078
2079 /* ATIOQ needs 1 vector. That's 1 less QPair */
2080 if (QLA_TGT_MODE_ENABLED())
2081 ha->max_req_queues--;
2082
2083 ha->max_rsp_queues = ha->max_req_queues;
2084
2085 /* Queue pairs is the max value minus
2086 * the base queue pair */
2087 ha->max_qpairs = ha->max_req_queues - 1;
2088 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2089 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2090 }
2091 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2092 "MSI-X vector count: %d.\n", ha->msix_count);
2093 } else
2094 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2095 "BAR 1 not enabled.\n");
2096
2097 mqiobase_exit:
2098 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2099 "MSIX Count: %d.\n", ha->msix_count);
2100 return 0;
2101
2102 iospace_error_exit:
2103 return -ENOMEM;
2104 }
2105
2106 static struct isp_operations qla2100_isp_ops = {
2107 .pci_config = qla2100_pci_config,
2108 .reset_chip = qla2x00_reset_chip,
2109 .chip_diag = qla2x00_chip_diag,
2110 .config_rings = qla2x00_config_rings,
2111 .reset_adapter = qla2x00_reset_adapter,
2112 .nvram_config = qla2x00_nvram_config,
2113 .update_fw_options = qla2x00_update_fw_options,
2114 .load_risc = qla2x00_load_risc,
2115 .pci_info_str = qla2x00_pci_info_str,
2116 .fw_version_str = qla2x00_fw_version_str,
2117 .intr_handler = qla2100_intr_handler,
2118 .enable_intrs = qla2x00_enable_intrs,
2119 .disable_intrs = qla2x00_disable_intrs,
2120 .abort_command = qla2x00_abort_command,
2121 .target_reset = qla2x00_abort_target,
2122 .lun_reset = qla2x00_lun_reset,
2123 .fabric_login = qla2x00_login_fabric,
2124 .fabric_logout = qla2x00_fabric_logout,
2125 .calc_req_entries = qla2x00_calc_iocbs_32,
2126 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2127 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2128 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2129 .read_nvram = qla2x00_read_nvram_data,
2130 .write_nvram = qla2x00_write_nvram_data,
2131 .fw_dump = qla2100_fw_dump,
2132 .beacon_on = NULL,
2133 .beacon_off = NULL,
2134 .beacon_blink = NULL,
2135 .read_optrom = qla2x00_read_optrom_data,
2136 .write_optrom = qla2x00_write_optrom_data,
2137 .get_flash_version = qla2x00_get_flash_version,
2138 .start_scsi = qla2x00_start_scsi,
2139 .start_scsi_mq = NULL,
2140 .abort_isp = qla2x00_abort_isp,
2141 .iospace_config = qla2x00_iospace_config,
2142 .initialize_adapter = qla2x00_initialize_adapter,
2143 };
2144
2145 static struct isp_operations qla2300_isp_ops = {
2146 .pci_config = qla2300_pci_config,
2147 .reset_chip = qla2x00_reset_chip,
2148 .chip_diag = qla2x00_chip_diag,
2149 .config_rings = qla2x00_config_rings,
2150 .reset_adapter = qla2x00_reset_adapter,
2151 .nvram_config = qla2x00_nvram_config,
2152 .update_fw_options = qla2x00_update_fw_options,
2153 .load_risc = qla2x00_load_risc,
2154 .pci_info_str = qla2x00_pci_info_str,
2155 .fw_version_str = qla2x00_fw_version_str,
2156 .intr_handler = qla2300_intr_handler,
2157 .enable_intrs = qla2x00_enable_intrs,
2158 .disable_intrs = qla2x00_disable_intrs,
2159 .abort_command = qla2x00_abort_command,
2160 .target_reset = qla2x00_abort_target,
2161 .lun_reset = qla2x00_lun_reset,
2162 .fabric_login = qla2x00_login_fabric,
2163 .fabric_logout = qla2x00_fabric_logout,
2164 .calc_req_entries = qla2x00_calc_iocbs_32,
2165 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2166 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2167 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2168 .read_nvram = qla2x00_read_nvram_data,
2169 .write_nvram = qla2x00_write_nvram_data,
2170 .fw_dump = qla2300_fw_dump,
2171 .beacon_on = qla2x00_beacon_on,
2172 .beacon_off = qla2x00_beacon_off,
2173 .beacon_blink = qla2x00_beacon_blink,
2174 .read_optrom = qla2x00_read_optrom_data,
2175 .write_optrom = qla2x00_write_optrom_data,
2176 .get_flash_version = qla2x00_get_flash_version,
2177 .start_scsi = qla2x00_start_scsi,
2178 .start_scsi_mq = NULL,
2179 .abort_isp = qla2x00_abort_isp,
2180 .iospace_config = qla2x00_iospace_config,
2181 .initialize_adapter = qla2x00_initialize_adapter,
2182 };
2183
2184 static struct isp_operations qla24xx_isp_ops = {
2185 .pci_config = qla24xx_pci_config,
2186 .reset_chip = qla24xx_reset_chip,
2187 .chip_diag = qla24xx_chip_diag,
2188 .config_rings = qla24xx_config_rings,
2189 .reset_adapter = qla24xx_reset_adapter,
2190 .nvram_config = qla24xx_nvram_config,
2191 .update_fw_options = qla24xx_update_fw_options,
2192 .load_risc = qla24xx_load_risc,
2193 .pci_info_str = qla24xx_pci_info_str,
2194 .fw_version_str = qla24xx_fw_version_str,
2195 .intr_handler = qla24xx_intr_handler,
2196 .enable_intrs = qla24xx_enable_intrs,
2197 .disable_intrs = qla24xx_disable_intrs,
2198 .abort_command = qla24xx_abort_command,
2199 .target_reset = qla24xx_abort_target,
2200 .lun_reset = qla24xx_lun_reset,
2201 .fabric_login = qla24xx_login_fabric,
2202 .fabric_logout = qla24xx_fabric_logout,
2203 .calc_req_entries = NULL,
2204 .build_iocbs = NULL,
2205 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2206 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2207 .read_nvram = qla24xx_read_nvram_data,
2208 .write_nvram = qla24xx_write_nvram_data,
2209 .fw_dump = qla24xx_fw_dump,
2210 .beacon_on = qla24xx_beacon_on,
2211 .beacon_off = qla24xx_beacon_off,
2212 .beacon_blink = qla24xx_beacon_blink,
2213 .read_optrom = qla24xx_read_optrom_data,
2214 .write_optrom = qla24xx_write_optrom_data,
2215 .get_flash_version = qla24xx_get_flash_version,
2216 .start_scsi = qla24xx_start_scsi,
2217 .start_scsi_mq = NULL,
2218 .abort_isp = qla2x00_abort_isp,
2219 .iospace_config = qla2x00_iospace_config,
2220 .initialize_adapter = qla2x00_initialize_adapter,
2221 };
2222
2223 static struct isp_operations qla25xx_isp_ops = {
2224 .pci_config = qla25xx_pci_config,
2225 .reset_chip = qla24xx_reset_chip,
2226 .chip_diag = qla24xx_chip_diag,
2227 .config_rings = qla24xx_config_rings,
2228 .reset_adapter = qla24xx_reset_adapter,
2229 .nvram_config = qla24xx_nvram_config,
2230 .update_fw_options = qla24xx_update_fw_options,
2231 .load_risc = qla24xx_load_risc,
2232 .pci_info_str = qla24xx_pci_info_str,
2233 .fw_version_str = qla24xx_fw_version_str,
2234 .intr_handler = qla24xx_intr_handler,
2235 .enable_intrs = qla24xx_enable_intrs,
2236 .disable_intrs = qla24xx_disable_intrs,
2237 .abort_command = qla24xx_abort_command,
2238 .target_reset = qla24xx_abort_target,
2239 .lun_reset = qla24xx_lun_reset,
2240 .fabric_login = qla24xx_login_fabric,
2241 .fabric_logout = qla24xx_fabric_logout,
2242 .calc_req_entries = NULL,
2243 .build_iocbs = NULL,
2244 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2245 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2246 .read_nvram = qla25xx_read_nvram_data,
2247 .write_nvram = qla25xx_write_nvram_data,
2248 .fw_dump = qla25xx_fw_dump,
2249 .beacon_on = qla24xx_beacon_on,
2250 .beacon_off = qla24xx_beacon_off,
2251 .beacon_blink = qla24xx_beacon_blink,
2252 .read_optrom = qla25xx_read_optrom_data,
2253 .write_optrom = qla24xx_write_optrom_data,
2254 .get_flash_version = qla24xx_get_flash_version,
2255 .start_scsi = qla24xx_dif_start_scsi,
2256 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2257 .abort_isp = qla2x00_abort_isp,
2258 .iospace_config = qla2x00_iospace_config,
2259 .initialize_adapter = qla2x00_initialize_adapter,
2260 };
2261
2262 static struct isp_operations qla81xx_isp_ops = {
2263 .pci_config = qla25xx_pci_config,
2264 .reset_chip = qla24xx_reset_chip,
2265 .chip_diag = qla24xx_chip_diag,
2266 .config_rings = qla24xx_config_rings,
2267 .reset_adapter = qla24xx_reset_adapter,
2268 .nvram_config = qla81xx_nvram_config,
2269 .update_fw_options = qla81xx_update_fw_options,
2270 .load_risc = qla81xx_load_risc,
2271 .pci_info_str = qla24xx_pci_info_str,
2272 .fw_version_str = qla24xx_fw_version_str,
2273 .intr_handler = qla24xx_intr_handler,
2274 .enable_intrs = qla24xx_enable_intrs,
2275 .disable_intrs = qla24xx_disable_intrs,
2276 .abort_command = qla24xx_abort_command,
2277 .target_reset = qla24xx_abort_target,
2278 .lun_reset = qla24xx_lun_reset,
2279 .fabric_login = qla24xx_login_fabric,
2280 .fabric_logout = qla24xx_fabric_logout,
2281 .calc_req_entries = NULL,
2282 .build_iocbs = NULL,
2283 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2284 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2285 .read_nvram = NULL,
2286 .write_nvram = NULL,
2287 .fw_dump = qla81xx_fw_dump,
2288 .beacon_on = qla24xx_beacon_on,
2289 .beacon_off = qla24xx_beacon_off,
2290 .beacon_blink = qla83xx_beacon_blink,
2291 .read_optrom = qla25xx_read_optrom_data,
2292 .write_optrom = qla24xx_write_optrom_data,
2293 .get_flash_version = qla24xx_get_flash_version,
2294 .start_scsi = qla24xx_dif_start_scsi,
2295 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2296 .abort_isp = qla2x00_abort_isp,
2297 .iospace_config = qla2x00_iospace_config,
2298 .initialize_adapter = qla2x00_initialize_adapter,
2299 };
2300
2301 static struct isp_operations qla82xx_isp_ops = {
2302 .pci_config = qla82xx_pci_config,
2303 .reset_chip = qla82xx_reset_chip,
2304 .chip_diag = qla24xx_chip_diag,
2305 .config_rings = qla82xx_config_rings,
2306 .reset_adapter = qla24xx_reset_adapter,
2307 .nvram_config = qla81xx_nvram_config,
2308 .update_fw_options = qla24xx_update_fw_options,
2309 .load_risc = qla82xx_load_risc,
2310 .pci_info_str = qla24xx_pci_info_str,
2311 .fw_version_str = qla24xx_fw_version_str,
2312 .intr_handler = qla82xx_intr_handler,
2313 .enable_intrs = qla82xx_enable_intrs,
2314 .disable_intrs = qla82xx_disable_intrs,
2315 .abort_command = qla24xx_abort_command,
2316 .target_reset = qla24xx_abort_target,
2317 .lun_reset = qla24xx_lun_reset,
2318 .fabric_login = qla24xx_login_fabric,
2319 .fabric_logout = qla24xx_fabric_logout,
2320 .calc_req_entries = NULL,
2321 .build_iocbs = NULL,
2322 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2323 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2324 .read_nvram = qla24xx_read_nvram_data,
2325 .write_nvram = qla24xx_write_nvram_data,
2326 .fw_dump = qla82xx_fw_dump,
2327 .beacon_on = qla82xx_beacon_on,
2328 .beacon_off = qla82xx_beacon_off,
2329 .beacon_blink = NULL,
2330 .read_optrom = qla82xx_read_optrom_data,
2331 .write_optrom = qla82xx_write_optrom_data,
2332 .get_flash_version = qla82xx_get_flash_version,
2333 .start_scsi = qla82xx_start_scsi,
2334 .start_scsi_mq = NULL,
2335 .abort_isp = qla82xx_abort_isp,
2336 .iospace_config = qla82xx_iospace_config,
2337 .initialize_adapter = qla2x00_initialize_adapter,
2338 };
2339
2340 static struct isp_operations qla8044_isp_ops = {
2341 .pci_config = qla82xx_pci_config,
2342 .reset_chip = qla82xx_reset_chip,
2343 .chip_diag = qla24xx_chip_diag,
2344 .config_rings = qla82xx_config_rings,
2345 .reset_adapter = qla24xx_reset_adapter,
2346 .nvram_config = qla81xx_nvram_config,
2347 .update_fw_options = qla24xx_update_fw_options,
2348 .load_risc = qla82xx_load_risc,
2349 .pci_info_str = qla24xx_pci_info_str,
2350 .fw_version_str = qla24xx_fw_version_str,
2351 .intr_handler = qla8044_intr_handler,
2352 .enable_intrs = qla82xx_enable_intrs,
2353 .disable_intrs = qla82xx_disable_intrs,
2354 .abort_command = qla24xx_abort_command,
2355 .target_reset = qla24xx_abort_target,
2356 .lun_reset = qla24xx_lun_reset,
2357 .fabric_login = qla24xx_login_fabric,
2358 .fabric_logout = qla24xx_fabric_logout,
2359 .calc_req_entries = NULL,
2360 .build_iocbs = NULL,
2361 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2362 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2363 .read_nvram = NULL,
2364 .write_nvram = NULL,
2365 .fw_dump = qla8044_fw_dump,
2366 .beacon_on = qla82xx_beacon_on,
2367 .beacon_off = qla82xx_beacon_off,
2368 .beacon_blink = NULL,
2369 .read_optrom = qla8044_read_optrom_data,
2370 .write_optrom = qla8044_write_optrom_data,
2371 .get_flash_version = qla82xx_get_flash_version,
2372 .start_scsi = qla82xx_start_scsi,
2373 .start_scsi_mq = NULL,
2374 .abort_isp = qla8044_abort_isp,
2375 .iospace_config = qla82xx_iospace_config,
2376 .initialize_adapter = qla2x00_initialize_adapter,
2377 };
2378
2379 static struct isp_operations qla83xx_isp_ops = {
2380 .pci_config = qla25xx_pci_config,
2381 .reset_chip = qla24xx_reset_chip,
2382 .chip_diag = qla24xx_chip_diag,
2383 .config_rings = qla24xx_config_rings,
2384 .reset_adapter = qla24xx_reset_adapter,
2385 .nvram_config = qla81xx_nvram_config,
2386 .update_fw_options = qla81xx_update_fw_options,
2387 .load_risc = qla81xx_load_risc,
2388 .pci_info_str = qla24xx_pci_info_str,
2389 .fw_version_str = qla24xx_fw_version_str,
2390 .intr_handler = qla24xx_intr_handler,
2391 .enable_intrs = qla24xx_enable_intrs,
2392 .disable_intrs = qla24xx_disable_intrs,
2393 .abort_command = qla24xx_abort_command,
2394 .target_reset = qla24xx_abort_target,
2395 .lun_reset = qla24xx_lun_reset,
2396 .fabric_login = qla24xx_login_fabric,
2397 .fabric_logout = qla24xx_fabric_logout,
2398 .calc_req_entries = NULL,
2399 .build_iocbs = NULL,
2400 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2401 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2402 .read_nvram = NULL,
2403 .write_nvram = NULL,
2404 .fw_dump = qla83xx_fw_dump,
2405 .beacon_on = qla24xx_beacon_on,
2406 .beacon_off = qla24xx_beacon_off,
2407 .beacon_blink = qla83xx_beacon_blink,
2408 .read_optrom = qla25xx_read_optrom_data,
2409 .write_optrom = qla24xx_write_optrom_data,
2410 .get_flash_version = qla24xx_get_flash_version,
2411 .start_scsi = qla24xx_dif_start_scsi,
2412 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2413 .abort_isp = qla2x00_abort_isp,
2414 .iospace_config = qla83xx_iospace_config,
2415 .initialize_adapter = qla2x00_initialize_adapter,
2416 };
2417
2418 static struct isp_operations qlafx00_isp_ops = {
2419 .pci_config = qlafx00_pci_config,
2420 .reset_chip = qlafx00_soft_reset,
2421 .chip_diag = qlafx00_chip_diag,
2422 .config_rings = qlafx00_config_rings,
2423 .reset_adapter = qlafx00_soft_reset,
2424 .nvram_config = NULL,
2425 .update_fw_options = NULL,
2426 .load_risc = NULL,
2427 .pci_info_str = qlafx00_pci_info_str,
2428 .fw_version_str = qlafx00_fw_version_str,
2429 .intr_handler = qlafx00_intr_handler,
2430 .enable_intrs = qlafx00_enable_intrs,
2431 .disable_intrs = qlafx00_disable_intrs,
2432 .abort_command = qla24xx_async_abort_command,
2433 .target_reset = qlafx00_abort_target,
2434 .lun_reset = qlafx00_lun_reset,
2435 .fabric_login = NULL,
2436 .fabric_logout = NULL,
2437 .calc_req_entries = NULL,
2438 .build_iocbs = NULL,
2439 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2440 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2441 .read_nvram = qla24xx_read_nvram_data,
2442 .write_nvram = qla24xx_write_nvram_data,
2443 .fw_dump = NULL,
2444 .beacon_on = qla24xx_beacon_on,
2445 .beacon_off = qla24xx_beacon_off,
2446 .beacon_blink = NULL,
2447 .read_optrom = qla24xx_read_optrom_data,
2448 .write_optrom = qla24xx_write_optrom_data,
2449 .get_flash_version = qla24xx_get_flash_version,
2450 .start_scsi = qlafx00_start_scsi,
2451 .start_scsi_mq = NULL,
2452 .abort_isp = qlafx00_abort_isp,
2453 .iospace_config = qlafx00_iospace_config,
2454 .initialize_adapter = qlafx00_initialize_adapter,
2455 };
2456
2457 static struct isp_operations qla27xx_isp_ops = {
2458 .pci_config = qla25xx_pci_config,
2459 .reset_chip = qla24xx_reset_chip,
2460 .chip_diag = qla24xx_chip_diag,
2461 .config_rings = qla24xx_config_rings,
2462 .reset_adapter = qla24xx_reset_adapter,
2463 .nvram_config = qla81xx_nvram_config,
2464 .update_fw_options = qla81xx_update_fw_options,
2465 .load_risc = qla81xx_load_risc,
2466 .pci_info_str = qla24xx_pci_info_str,
2467 .fw_version_str = qla24xx_fw_version_str,
2468 .intr_handler = qla24xx_intr_handler,
2469 .enable_intrs = qla24xx_enable_intrs,
2470 .disable_intrs = qla24xx_disable_intrs,
2471 .abort_command = qla24xx_abort_command,
2472 .target_reset = qla24xx_abort_target,
2473 .lun_reset = qla24xx_lun_reset,
2474 .fabric_login = qla24xx_login_fabric,
2475 .fabric_logout = qla24xx_fabric_logout,
2476 .calc_req_entries = NULL,
2477 .build_iocbs = NULL,
2478 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2479 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2480 .read_nvram = NULL,
2481 .write_nvram = NULL,
2482 .fw_dump = qla27xx_fwdump,
2483 .beacon_on = qla24xx_beacon_on,
2484 .beacon_off = qla24xx_beacon_off,
2485 .beacon_blink = qla83xx_beacon_blink,
2486 .read_optrom = qla25xx_read_optrom_data,
2487 .write_optrom = qla24xx_write_optrom_data,
2488 .get_flash_version = qla24xx_get_flash_version,
2489 .start_scsi = qla24xx_dif_start_scsi,
2490 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2491 .abort_isp = qla2x00_abort_isp,
2492 .iospace_config = qla83xx_iospace_config,
2493 .initialize_adapter = qla2x00_initialize_adapter,
2494 };
2495
2496 static inline void
2497 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2498 {
2499 ha->device_type = DT_EXTENDED_IDS;
2500 switch (ha->pdev->device) {
2501 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2502 ha->isp_type |= DT_ISP2100;
2503 ha->device_type &= ~DT_EXTENDED_IDS;
2504 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2505 break;
2506 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2507 ha->isp_type |= DT_ISP2200;
2508 ha->device_type &= ~DT_EXTENDED_IDS;
2509 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2510 break;
2511 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2512 ha->isp_type |= DT_ISP2300;
2513 ha->device_type |= DT_ZIO_SUPPORTED;
2514 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2515 break;
2516 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2517 ha->isp_type |= DT_ISP2312;
2518 ha->device_type |= DT_ZIO_SUPPORTED;
2519 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2520 break;
2521 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2522 ha->isp_type |= DT_ISP2322;
2523 ha->device_type |= DT_ZIO_SUPPORTED;
2524 if (ha->pdev->subsystem_vendor == 0x1028 &&
2525 ha->pdev->subsystem_device == 0x0170)
2526 ha->device_type |= DT_OEM_001;
2527 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2528 break;
2529 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2530 ha->isp_type |= DT_ISP6312;
2531 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2532 break;
2533 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2534 ha->isp_type |= DT_ISP6322;
2535 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2536 break;
2537 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2538 ha->isp_type |= DT_ISP2422;
2539 ha->device_type |= DT_ZIO_SUPPORTED;
2540 ha->device_type |= DT_FWI2;
2541 ha->device_type |= DT_IIDMA;
2542 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2543 break;
2544 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2545 ha->isp_type |= DT_ISP2432;
2546 ha->device_type |= DT_ZIO_SUPPORTED;
2547 ha->device_type |= DT_FWI2;
2548 ha->device_type |= DT_IIDMA;
2549 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2550 break;
2551 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2552 ha->isp_type |= DT_ISP8432;
2553 ha->device_type |= DT_ZIO_SUPPORTED;
2554 ha->device_type |= DT_FWI2;
2555 ha->device_type |= DT_IIDMA;
2556 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2557 break;
2558 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2559 ha->isp_type |= DT_ISP5422;
2560 ha->device_type |= DT_FWI2;
2561 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2562 break;
2563 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2564 ha->isp_type |= DT_ISP5432;
2565 ha->device_type |= DT_FWI2;
2566 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2567 break;
2568 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2569 ha->isp_type |= DT_ISP2532;
2570 ha->device_type |= DT_ZIO_SUPPORTED;
2571 ha->device_type |= DT_FWI2;
2572 ha->device_type |= DT_IIDMA;
2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2574 break;
2575 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2576 ha->isp_type |= DT_ISP8001;
2577 ha->device_type |= DT_ZIO_SUPPORTED;
2578 ha->device_type |= DT_FWI2;
2579 ha->device_type |= DT_IIDMA;
2580 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2581 break;
2582 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2583 ha->isp_type |= DT_ISP8021;
2584 ha->device_type |= DT_ZIO_SUPPORTED;
2585 ha->device_type |= DT_FWI2;
2586 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2587 /* Initialize 82XX ISP flags */
2588 qla82xx_init_flags(ha);
2589 break;
2590 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2591 ha->isp_type |= DT_ISP8044;
2592 ha->device_type |= DT_ZIO_SUPPORTED;
2593 ha->device_type |= DT_FWI2;
2594 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2595 /* Initialize 82XX ISP flags */
2596 qla82xx_init_flags(ha);
2597 break;
2598 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2599 ha->isp_type |= DT_ISP2031;
2600 ha->device_type |= DT_ZIO_SUPPORTED;
2601 ha->device_type |= DT_FWI2;
2602 ha->device_type |= DT_IIDMA;
2603 ha->device_type |= DT_T10_PI;
2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2605 break;
2606 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2607 ha->isp_type |= DT_ISP8031;
2608 ha->device_type |= DT_ZIO_SUPPORTED;
2609 ha->device_type |= DT_FWI2;
2610 ha->device_type |= DT_IIDMA;
2611 ha->device_type |= DT_T10_PI;
2612 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2613 break;
2614 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2615 ha->isp_type |= DT_ISPFX00;
2616 break;
2617 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2618 ha->isp_type |= DT_ISP2071;
2619 ha->device_type |= DT_ZIO_SUPPORTED;
2620 ha->device_type |= DT_FWI2;
2621 ha->device_type |= DT_IIDMA;
2622 ha->device_type |= DT_T10_PI;
2623 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2624 break;
2625 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2626 ha->isp_type |= DT_ISP2271;
2627 ha->device_type |= DT_ZIO_SUPPORTED;
2628 ha->device_type |= DT_FWI2;
2629 ha->device_type |= DT_IIDMA;
2630 ha->device_type |= DT_T10_PI;
2631 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2632 break;
2633 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2634 ha->isp_type |= DT_ISP2261;
2635 ha->device_type |= DT_ZIO_SUPPORTED;
2636 ha->device_type |= DT_FWI2;
2637 ha->device_type |= DT_IIDMA;
2638 ha->device_type |= DT_T10_PI;
2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2640 break;
2641 }
2642
2643 if (IS_QLA82XX(ha))
2644 ha->port_no = ha->portnum & 1;
2645 else {
2646 /* Get adapter physical port no from interrupt pin register. */
2647 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2648 if (IS_QLA27XX(ha))
2649 ha->port_no--;
2650 else
2651 ha->port_no = !(ha->port_no & 1);
2652 }
2653
2654 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2655 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2656 ha->device_type, ha->port_no, ha->fw_srisc_address);
2657 }
2658
2659 static void
2660 qla2xxx_scan_start(struct Scsi_Host *shost)
2661 {
2662 scsi_qla_host_t *vha = shost_priv(shost);
2663
2664 if (vha->hw->flags.running_gold_fw)
2665 return;
2666
2667 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2668 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2669 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2670 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2671 }
2672
2673 static int
2674 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2675 {
2676 scsi_qla_host_t *vha = shost_priv(shost);
2677
2678 if (test_bit(UNLOADING, &vha->dpc_flags))
2679 return 1;
2680 if (!vha->host)
2681 return 1;
2682 if (time > vha->hw->loop_reset_delay * HZ)
2683 return 1;
2684
2685 return atomic_read(&vha->loop_state) == LOOP_READY;
2686 }
2687
2688 static void qla2x00_iocb_work_fn(struct work_struct *work)
2689 {
2690 struct scsi_qla_host *vha = container_of(work,
2691 struct scsi_qla_host, iocb_work);
2692 int cnt = 0;
2693
2694 while (!list_empty(&vha->work_list)) {
2695 qla2x00_do_work(vha);
2696 cnt++;
2697 if (cnt > 10)
2698 break;
2699 }
2700 }
2701
2702 /*
2703 * PCI driver interface
2704 */
2705 static int
2706 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2707 {
2708 int ret = -ENODEV;
2709 struct Scsi_Host *host;
2710 scsi_qla_host_t *base_vha = NULL;
2711 struct qla_hw_data *ha;
2712 char pci_info[30];
2713 char fw_str[30], wq_name[30];
2714 struct scsi_host_template *sht;
2715 int bars, mem_only = 0;
2716 uint16_t req_length = 0, rsp_length = 0;
2717 struct req_que *req = NULL;
2718 struct rsp_que *rsp = NULL;
2719 int i;
2720
2721 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2722 sht = &qla2xxx_driver_template;
2723 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2724 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2725 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2726 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2727 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2728 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2729 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2730 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2731 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2732 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2733 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2734 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2735 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2736 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2737 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
2738 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2739 mem_only = 1;
2740 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2741 "Mem only adapter.\n");
2742 }
2743 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2744 "Bars=%d.\n", bars);
2745
2746 if (mem_only) {
2747 if (pci_enable_device_mem(pdev))
2748 return ret;
2749 } else {
2750 if (pci_enable_device(pdev))
2751 return ret;
2752 }
2753
2754 /* This may fail but that's ok */
2755 pci_enable_pcie_error_reporting(pdev);
2756
2757 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2758 if (!ha) {
2759 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2760 "Unable to allocate memory for ha.\n");
2761 goto disable_device;
2762 }
2763 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2764 "Memory allocated for ha=%p.\n", ha);
2765 ha->pdev = pdev;
2766 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2767 spin_lock_init(&ha->tgt.q_full_lock);
2768 spin_lock_init(&ha->tgt.sess_lock);
2769 spin_lock_init(&ha->tgt.atio_lock);
2770
2771 atomic_set(&ha->nvme_active_aen_cnt, 0);
2772
2773 /* Clear our data area */
2774 ha->bars = bars;
2775 ha->mem_only = mem_only;
2776 spin_lock_init(&ha->hardware_lock);
2777 spin_lock_init(&ha->vport_slock);
2778 mutex_init(&ha->selflogin_lock);
2779 mutex_init(&ha->optrom_mutex);
2780
2781 /* Set ISP-type information. */
2782 qla2x00_set_isp_flags(ha);
2783
2784 /* Set EEH reset type to fundamental if required by hba */
2785 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2786 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2787 pdev->needs_freset = 1;
2788
2789 ha->prev_topology = 0;
2790 ha->init_cb_size = sizeof(init_cb_t);
2791 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2792 ha->optrom_size = OPTROM_SIZE_2300;
2793
2794 /* Assign ISP specific operations. */
2795 if (IS_QLA2100(ha)) {
2796 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2797 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2798 req_length = REQUEST_ENTRY_CNT_2100;
2799 rsp_length = RESPONSE_ENTRY_CNT_2100;
2800 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2801 ha->gid_list_info_size = 4;
2802 ha->flash_conf_off = ~0;
2803 ha->flash_data_off = ~0;
2804 ha->nvram_conf_off = ~0;
2805 ha->nvram_data_off = ~0;
2806 ha->isp_ops = &qla2100_isp_ops;
2807 } else if (IS_QLA2200(ha)) {
2808 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2809 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2810 req_length = REQUEST_ENTRY_CNT_2200;
2811 rsp_length = RESPONSE_ENTRY_CNT_2100;
2812 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2813 ha->gid_list_info_size = 4;
2814 ha->flash_conf_off = ~0;
2815 ha->flash_data_off = ~0;
2816 ha->nvram_conf_off = ~0;
2817 ha->nvram_data_off = ~0;
2818 ha->isp_ops = &qla2100_isp_ops;
2819 } else if (IS_QLA23XX(ha)) {
2820 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2821 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2822 req_length = REQUEST_ENTRY_CNT_2200;
2823 rsp_length = RESPONSE_ENTRY_CNT_2300;
2824 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2825 ha->gid_list_info_size = 6;
2826 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2827 ha->optrom_size = OPTROM_SIZE_2322;
2828 ha->flash_conf_off = ~0;
2829 ha->flash_data_off = ~0;
2830 ha->nvram_conf_off = ~0;
2831 ha->nvram_data_off = ~0;
2832 ha->isp_ops = &qla2300_isp_ops;
2833 } else if (IS_QLA24XX_TYPE(ha)) {
2834 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2835 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2836 req_length = REQUEST_ENTRY_CNT_24XX;
2837 rsp_length = RESPONSE_ENTRY_CNT_2300;
2838 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2839 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2840 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2841 ha->gid_list_info_size = 8;
2842 ha->optrom_size = OPTROM_SIZE_24XX;
2843 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2844 ha->isp_ops = &qla24xx_isp_ops;
2845 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2846 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2847 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2848 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2849 } else if (IS_QLA25XX(ha)) {
2850 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2851 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2852 req_length = REQUEST_ENTRY_CNT_24XX;
2853 rsp_length = RESPONSE_ENTRY_CNT_2300;
2854 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2855 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2856 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2857 ha->gid_list_info_size = 8;
2858 ha->optrom_size = OPTROM_SIZE_25XX;
2859 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2860 ha->isp_ops = &qla25xx_isp_ops;
2861 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2862 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2863 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2864 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2865 } else if (IS_QLA81XX(ha)) {
2866 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2867 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2868 req_length = REQUEST_ENTRY_CNT_24XX;
2869 rsp_length = RESPONSE_ENTRY_CNT_2300;
2870 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2871 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2872 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2873 ha->gid_list_info_size = 8;
2874 ha->optrom_size = OPTROM_SIZE_81XX;
2875 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2876 ha->isp_ops = &qla81xx_isp_ops;
2877 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2878 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2879 ha->nvram_conf_off = ~0;
2880 ha->nvram_data_off = ~0;
2881 } else if (IS_QLA82XX(ha)) {
2882 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2883 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2884 req_length = REQUEST_ENTRY_CNT_82XX;
2885 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2886 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2887 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2888 ha->gid_list_info_size = 8;
2889 ha->optrom_size = OPTROM_SIZE_82XX;
2890 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2891 ha->isp_ops = &qla82xx_isp_ops;
2892 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2893 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2894 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2895 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2896 } else if (IS_QLA8044(ha)) {
2897 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2898 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2899 req_length = REQUEST_ENTRY_CNT_82XX;
2900 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2901 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2902 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2903 ha->gid_list_info_size = 8;
2904 ha->optrom_size = OPTROM_SIZE_83XX;
2905 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2906 ha->isp_ops = &qla8044_isp_ops;
2907 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2908 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2909 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2910 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2911 } else if (IS_QLA83XX(ha)) {
2912 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2913 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2914 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2915 req_length = REQUEST_ENTRY_CNT_83XX;
2916 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2917 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2918 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2919 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2920 ha->gid_list_info_size = 8;
2921 ha->optrom_size = OPTROM_SIZE_83XX;
2922 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2923 ha->isp_ops = &qla83xx_isp_ops;
2924 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2925 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2926 ha->nvram_conf_off = ~0;
2927 ha->nvram_data_off = ~0;
2928 } else if (IS_QLAFX00(ha)) {
2929 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2930 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2931 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2932 req_length = REQUEST_ENTRY_CNT_FX00;
2933 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2934 ha->isp_ops = &qlafx00_isp_ops;
2935 ha->port_down_retry_count = 30; /* default value */
2936 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2937 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2938 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2939 ha->mr.fw_hbt_en = 1;
2940 ha->mr.host_info_resend = false;
2941 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2942 } else if (IS_QLA27XX(ha)) {
2943 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2944 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2945 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2946 req_length = REQUEST_ENTRY_CNT_83XX;
2947 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2948 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2949 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2950 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2951 ha->gid_list_info_size = 8;
2952 ha->optrom_size = OPTROM_SIZE_83XX;
2953 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2954 ha->isp_ops = &qla27xx_isp_ops;
2955 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2956 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2957 ha->nvram_conf_off = ~0;
2958 ha->nvram_data_off = ~0;
2959 }
2960
2961 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2962 "mbx_count=%d, req_length=%d, "
2963 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2964 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2965 "max_fibre_devices=%d.\n",
2966 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2967 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2968 ha->nvram_npiv_size, ha->max_fibre_devices);
2969 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2970 "isp_ops=%p, flash_conf_off=%d, "
2971 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2972 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2973 ha->nvram_conf_off, ha->nvram_data_off);
2974
2975 /* Configure PCI I/O space */
2976 ret = ha->isp_ops->iospace_config(ha);
2977 if (ret)
2978 goto iospace_config_failed;
2979
2980 ql_log_pci(ql_log_info, pdev, 0x001d,
2981 "Found an ISP%04X irq %d iobase 0x%p.\n",
2982 pdev->device, pdev->irq, ha->iobase);
2983 mutex_init(&ha->vport_lock);
2984 mutex_init(&ha->mq_lock);
2985 init_completion(&ha->mbx_cmd_comp);
2986 complete(&ha->mbx_cmd_comp);
2987 init_completion(&ha->mbx_intr_comp);
2988 init_completion(&ha->dcbx_comp);
2989 init_completion(&ha->lb_portup_comp);
2990
2991 set_bit(0, (unsigned long *) ha->vp_idx_map);
2992
2993 qla2x00_config_dma_addressing(ha);
2994 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2995 "64 Bit addressing is %s.\n",
2996 ha->flags.enable_64bit_addressing ? "enable" :
2997 "disable");
2998 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2999 if (ret) {
3000 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3001 "Failed to allocate memory for adapter, aborting.\n");
3002
3003 goto probe_hw_failed;
3004 }
3005
3006 req->max_q_depth = MAX_Q_DEPTH;
3007 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3008 req->max_q_depth = ql2xmaxqdepth;
3009
3010
3011 base_vha = qla2x00_create_host(sht, ha);
3012 if (!base_vha) {
3013 ret = -ENOMEM;
3014 qla2x00_mem_free(ha);
3015 qla2x00_free_req_que(ha, req);
3016 qla2x00_free_rsp_que(ha, rsp);
3017 goto probe_hw_failed;
3018 }
3019
3020 pci_set_drvdata(pdev, base_vha);
3021 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3022
3023 host = base_vha->host;
3024 base_vha->req = req;
3025 if (IS_QLA2XXX_MIDTYPE(ha))
3026 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
3027 else
3028 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3029 base_vha->vp_idx;
3030
3031 /* Setup fcport template structure. */
3032 ha->mr.fcport.vha = base_vha;
3033 ha->mr.fcport.port_type = FCT_UNKNOWN;
3034 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3035 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3036 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3037 ha->mr.fcport.scan_state = 1;
3038
3039 /* Set the SG table size based on ISP type */
3040 if (!IS_FWI2_CAPABLE(ha)) {
3041 if (IS_QLA2100(ha))
3042 host->sg_tablesize = 32;
3043 } else {
3044 if (!IS_QLA82XX(ha))
3045 host->sg_tablesize = QLA_SG_ALL;
3046 }
3047 host->max_id = ha->max_fibre_devices;
3048 host->cmd_per_lun = 3;
3049 host->unique_id = host->host_no;
3050 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3051 host->max_cmd_len = 32;
3052 else
3053 host->max_cmd_len = MAX_CMDSZ;
3054 host->max_channel = MAX_BUSES - 1;
3055 /* Older HBAs support only 16-bit LUNs */
3056 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3057 ql2xmaxlun > 0xffff)
3058 host->max_lun = 0xffff;
3059 else
3060 host->max_lun = ql2xmaxlun;
3061 host->transportt = qla2xxx_transport_template;
3062 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3063
3064 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3065 "max_id=%d this_id=%d "
3066 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3067 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3068 host->this_id, host->cmd_per_lun, host->unique_id,
3069 host->max_cmd_len, host->max_channel, host->max_lun,
3070 host->transportt, sht->vendor_id);
3071
3072 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3073
3074 /* Set up the irqs */
3075 ret = qla2x00_request_irqs(ha, rsp);
3076 if (ret)
3077 goto probe_init_failed;
3078
3079 /* Alloc arrays of request and response ring ptrs */
3080 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3081 ql_log(ql_log_fatal, base_vha, 0x003d,
3082 "Failed to allocate memory for queue pointers..."
3083 "aborting.\n");
3084 goto probe_init_failed;
3085 }
3086
3087 if (ha->mqenable && shost_use_blk_mq(host)) {
3088 /* number of hardware queues supported by blk/scsi-mq*/
3089 host->nr_hw_queues = ha->max_qpairs;
3090
3091 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3092 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3093 } else {
3094 if (ql2xnvmeenable) {
3095 host->nr_hw_queues = ha->max_qpairs;
3096 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3097 "FC-NVMe support is enabled, HW queues=%d\n",
3098 host->nr_hw_queues);
3099 } else {
3100 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3101 "blk/scsi-mq disabled.\n");
3102 }
3103 }
3104
3105 qlt_probe_one_stage1(base_vha, ha);
3106
3107 pci_save_state(pdev);
3108
3109 /* Assign back pointers */
3110 rsp->req = req;
3111 req->rsp = rsp;
3112
3113 if (IS_QLAFX00(ha)) {
3114 ha->rsp_q_map[0] = rsp;
3115 ha->req_q_map[0] = req;
3116 set_bit(0, ha->req_qid_map);
3117 set_bit(0, ha->rsp_qid_map);
3118 }
3119
3120 /* FWI2-capable only. */
3121 req->req_q_in = &ha->iobase->isp24.req_q_in;
3122 req->req_q_out = &ha->iobase->isp24.req_q_out;
3123 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3124 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3125 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3126 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3127 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3128 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3129 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3130 }
3131
3132 if (IS_QLAFX00(ha)) {
3133 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3134 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3135 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3136 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3137 }
3138
3139 if (IS_P3P_TYPE(ha)) {
3140 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3141 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3142 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3143 }
3144
3145 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3146 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3147 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3148 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3149 "req->req_q_in=%p req->req_q_out=%p "
3150 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3151 req->req_q_in, req->req_q_out,
3152 rsp->rsp_q_in, rsp->rsp_q_out);
3153 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3154 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3155 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3156 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3157 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3158 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3159
3160 if (ha->isp_ops->initialize_adapter(base_vha)) {
3161 ql_log(ql_log_fatal, base_vha, 0x00d6,
3162 "Failed to initialize adapter - Adapter flags %x.\n",
3163 base_vha->device_flags);
3164
3165 if (IS_QLA82XX(ha)) {
3166 qla82xx_idc_lock(ha);
3167 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3168 QLA8XXX_DEV_FAILED);
3169 qla82xx_idc_unlock(ha);
3170 ql_log(ql_log_fatal, base_vha, 0x00d7,
3171 "HW State: FAILED.\n");
3172 } else if (IS_QLA8044(ha)) {
3173 qla8044_idc_lock(ha);
3174 qla8044_wr_direct(base_vha,
3175 QLA8044_CRB_DEV_STATE_INDEX,
3176 QLA8XXX_DEV_FAILED);
3177 qla8044_idc_unlock(ha);
3178 ql_log(ql_log_fatal, base_vha, 0x0150,
3179 "HW State: FAILED.\n");
3180 }
3181
3182 ret = -ENODEV;
3183 goto probe_failed;
3184 }
3185
3186 if (IS_QLAFX00(ha))
3187 host->can_queue = QLAFX00_MAX_CANQUEUE;
3188 else
3189 host->can_queue = req->num_outstanding_cmds - 10;
3190
3191 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3192 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3193 host->can_queue, base_vha->req,
3194 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3195
3196 if (ha->mqenable) {
3197 bool mq = false;
3198 bool startit = false;
3199 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3200
3201 if (QLA_TGT_MODE_ENABLED()) {
3202 mq = true;
3203 startit = false;
3204 }
3205
3206 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3207 shost_use_blk_mq(host)) {
3208 mq = true;
3209 startit = true;
3210 }
3211
3212 if (mq) {
3213 /* Create start of day qpairs for Block MQ */
3214 for (i = 0; i < ha->max_qpairs; i++)
3215 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3216 }
3217 }
3218
3219 if (ha->flags.running_gold_fw)
3220 goto skip_dpc;
3221
3222 /*
3223 * Startup the kernel thread for this host adapter
3224 */
3225 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3226 "%s_dpc", base_vha->host_str);
3227 if (IS_ERR(ha->dpc_thread)) {
3228 ql_log(ql_log_fatal, base_vha, 0x00ed,
3229 "Failed to start DPC thread.\n");
3230 ret = PTR_ERR(ha->dpc_thread);
3231 ha->dpc_thread = NULL;
3232 goto probe_failed;
3233 }
3234 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3235 "DPC thread started successfully.\n");
3236
3237 /*
3238 * If we're not coming up in initiator mode, we might sit for
3239 * a while without waking up the dpc thread, which leads to a
3240 * stuck process warning. So just kick the dpc once here and
3241 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3242 */
3243 qla2xxx_wake_dpc(base_vha);
3244
3245 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3246
3247 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3248 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3249 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3250 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3251
3252 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3253 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3254 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3255 INIT_WORK(&ha->idc_state_handler,
3256 qla83xx_idc_state_handler_work);
3257 INIT_WORK(&ha->nic_core_unrecoverable,
3258 qla83xx_nic_core_unrecoverable_work);
3259 }
3260
3261 skip_dpc:
3262 list_add_tail(&base_vha->list, &ha->vp_list);
3263 base_vha->host->irq = ha->pdev->irq;
3264
3265 /* Initialized the timer */
3266 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3267 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3268 "Started qla2x00_timer with "
3269 "interval=%d.\n", WATCH_INTERVAL);
3270 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3271 "Detected hba at address=%p.\n",
3272 ha);
3273
3274 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3275 if (ha->fw_attributes & BIT_4) {
3276 int prot = 0, guard;
3277 base_vha->flags.difdix_supported = 1;
3278 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3279 "Registering for DIF/DIX type 1 and 3 protection.\n");
3280 if (ql2xenabledif == 1)
3281 prot = SHOST_DIX_TYPE0_PROTECTION;
3282 scsi_host_set_prot(host,
3283 prot | SHOST_DIF_TYPE1_PROTECTION
3284 | SHOST_DIF_TYPE2_PROTECTION
3285 | SHOST_DIF_TYPE3_PROTECTION
3286 | SHOST_DIX_TYPE1_PROTECTION
3287 | SHOST_DIX_TYPE2_PROTECTION
3288 | SHOST_DIX_TYPE3_PROTECTION);
3289
3290 guard = SHOST_DIX_GUARD_CRC;
3291
3292 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3293 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3294 guard |= SHOST_DIX_GUARD_IP;
3295
3296 scsi_host_set_guard(host, guard);
3297 } else
3298 base_vha->flags.difdix_supported = 0;
3299 }
3300
3301 ha->isp_ops->enable_intrs(ha);
3302
3303 if (IS_QLAFX00(ha)) {
3304 ret = qlafx00_fx_disc(base_vha,
3305 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3306 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3307 QLA_SG_ALL : 128;
3308 }
3309
3310 ret = scsi_add_host(host, &pdev->dev);
3311 if (ret)
3312 goto probe_failed;
3313
3314 base_vha->flags.init_done = 1;
3315 base_vha->flags.online = 1;
3316 ha->prev_minidump_failed = 0;
3317
3318 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3319 "Init done and hba is online.\n");
3320
3321 if (qla_ini_mode_enabled(base_vha) ||
3322 qla_dual_mode_enabled(base_vha))
3323 scsi_scan_host(host);
3324 else
3325 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3326 "skipping scsi_scan_host() for non-initiator port\n");
3327
3328 qla2x00_alloc_sysfs_attr(base_vha);
3329
3330 if (IS_QLAFX00(ha)) {
3331 ret = qlafx00_fx_disc(base_vha,
3332 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3333
3334 /* Register system information */
3335 ret = qlafx00_fx_disc(base_vha,
3336 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3337 }
3338
3339 qla2x00_init_host_attr(base_vha);
3340
3341 qla2x00_dfs_setup(base_vha);
3342
3343 ql_log(ql_log_info, base_vha, 0x00fb,
3344 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3345 ql_log(ql_log_info, base_vha, 0x00fc,
3346 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3347 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3348 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3349 base_vha->host_no,
3350 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3351
3352 qlt_add_target(ha, base_vha);
3353
3354 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3355
3356 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3357 return -ENODEV;
3358
3359 if (ha->flags.detected_lr_sfp) {
3360 ql_log(ql_log_info, base_vha, 0xffff,
3361 "Reset chip to pick up LR SFP setting\n");
3362 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3363 qla2xxx_wake_dpc(base_vha);
3364 }
3365
3366 return 0;
3367
3368 probe_init_failed:
3369 qla2x00_free_req_que(ha, req);
3370 ha->req_q_map[0] = NULL;
3371 clear_bit(0, ha->req_qid_map);
3372 qla2x00_free_rsp_que(ha, rsp);
3373 ha->rsp_q_map[0] = NULL;
3374 clear_bit(0, ha->rsp_qid_map);
3375 ha->max_req_queues = ha->max_rsp_queues = 0;
3376
3377 probe_failed:
3378 if (base_vha->timer_active)
3379 qla2x00_stop_timer(base_vha);
3380 base_vha->flags.online = 0;
3381 if (ha->dpc_thread) {
3382 struct task_struct *t = ha->dpc_thread;
3383
3384 ha->dpc_thread = NULL;
3385 kthread_stop(t);
3386 }
3387
3388 qla2x00_free_device(base_vha);
3389
3390 scsi_host_put(base_vha->host);
3391
3392 probe_hw_failed:
3393 qla2x00_clear_drv_active(ha);
3394
3395 iospace_config_failed:
3396 if (IS_P3P_TYPE(ha)) {
3397 if (!ha->nx_pcibase)
3398 iounmap((device_reg_t *)ha->nx_pcibase);
3399 if (!ql2xdbwr)
3400 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3401 } else {
3402 if (ha->iobase)
3403 iounmap(ha->iobase);
3404 if (ha->cregbase)
3405 iounmap(ha->cregbase);
3406 }
3407 pci_release_selected_regions(ha->pdev, ha->bars);
3408 kfree(ha);
3409
3410 disable_device:
3411 pci_disable_device(pdev);
3412 return ret;
3413 }
3414
3415 static void
3416 qla2x00_shutdown(struct pci_dev *pdev)
3417 {
3418 scsi_qla_host_t *vha;
3419 struct qla_hw_data *ha;
3420
3421 vha = pci_get_drvdata(pdev);
3422 ha = vha->hw;
3423
3424 ql_log(ql_log_info, vha, 0xfffa,
3425 "Adapter shutdown\n");
3426
3427 /*
3428 * Prevent future board_disable and wait
3429 * until any pending board_disable has completed.
3430 */
3431 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3432 cancel_work_sync(&ha->board_disable);
3433
3434 if (!atomic_read(&pdev->enable_cnt))
3435 return;
3436
3437 /* Notify ISPFX00 firmware */
3438 if (IS_QLAFX00(ha))
3439 qlafx00_driver_shutdown(vha, 20);
3440
3441 /* Turn-off FCE trace */
3442 if (ha->flags.fce_enabled) {
3443 qla2x00_disable_fce_trace(vha, NULL, NULL);
3444 ha->flags.fce_enabled = 0;
3445 }
3446
3447 /* Turn-off EFT trace */
3448 if (ha->eft)
3449 qla2x00_disable_eft_trace(vha);
3450
3451 /* Stop currently executing firmware. */
3452 qla2x00_try_to_stop_firmware(vha);
3453
3454 /* Turn adapter off line */
3455 vha->flags.online = 0;
3456
3457 /* turn-off interrupts on the card */
3458 if (ha->interrupts_on) {
3459 vha->flags.init_done = 0;
3460 ha->isp_ops->disable_intrs(ha);
3461 }
3462
3463 qla2x00_free_irqs(vha);
3464
3465 qla2x00_free_fw_dump(ha);
3466
3467 pci_disable_device(pdev);
3468 ql_log(ql_log_info, vha, 0xfffe,
3469 "Adapter shutdown successfully.\n");
3470 }
3471
3472 /* Deletes all the virtual ports for a given ha */
3473 static void
3474 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3475 {
3476 scsi_qla_host_t *vha;
3477 unsigned long flags;
3478
3479 mutex_lock(&ha->vport_lock);
3480 while (ha->cur_vport_count) {
3481 spin_lock_irqsave(&ha->vport_slock, flags);
3482
3483 BUG_ON(base_vha->list.next == &ha->vp_list);
3484 /* This assumes first entry in ha->vp_list is always base vha */
3485 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3486 scsi_host_get(vha->host);
3487
3488 spin_unlock_irqrestore(&ha->vport_slock, flags);
3489 mutex_unlock(&ha->vport_lock);
3490
3491 fc_vport_terminate(vha->fc_vport);
3492 scsi_host_put(vha->host);
3493
3494 mutex_lock(&ha->vport_lock);
3495 }
3496 mutex_unlock(&ha->vport_lock);
3497 }
3498
3499 /* Stops all deferred work threads */
3500 static void
3501 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3502 {
3503 /* Cancel all work and destroy DPC workqueues */
3504 if (ha->dpc_lp_wq) {
3505 cancel_work_sync(&ha->idc_aen);
3506 destroy_workqueue(ha->dpc_lp_wq);
3507 ha->dpc_lp_wq = NULL;
3508 }
3509
3510 if (ha->dpc_hp_wq) {
3511 cancel_work_sync(&ha->nic_core_reset);
3512 cancel_work_sync(&ha->idc_state_handler);
3513 cancel_work_sync(&ha->nic_core_unrecoverable);
3514 destroy_workqueue(ha->dpc_hp_wq);
3515 ha->dpc_hp_wq = NULL;
3516 }
3517
3518 /* Kill the kernel thread for this host */
3519 if (ha->dpc_thread) {
3520 struct task_struct *t = ha->dpc_thread;
3521
3522 /*
3523 * qla2xxx_wake_dpc checks for ->dpc_thread
3524 * so we need to zero it out.
3525 */
3526 ha->dpc_thread = NULL;
3527 kthread_stop(t);
3528 }
3529 }
3530
3531 static void
3532 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3533 {
3534 if (IS_QLA82XX(ha)) {
3535
3536 iounmap((device_reg_t *)ha->nx_pcibase);
3537 if (!ql2xdbwr)
3538 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3539 } else {
3540 if (ha->iobase)
3541 iounmap(ha->iobase);
3542
3543 if (ha->cregbase)
3544 iounmap(ha->cregbase);
3545
3546 if (ha->mqiobase)
3547 iounmap(ha->mqiobase);
3548
3549 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3550 iounmap(ha->msixbase);
3551 }
3552 }
3553
3554 static void
3555 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3556 {
3557 if (IS_QLA8044(ha)) {
3558 qla8044_idc_lock(ha);
3559 qla8044_clear_drv_active(ha);
3560 qla8044_idc_unlock(ha);
3561 } else if (IS_QLA82XX(ha)) {
3562 qla82xx_idc_lock(ha);
3563 qla82xx_clear_drv_active(ha);
3564 qla82xx_idc_unlock(ha);
3565 }
3566 }
3567
3568 static void
3569 qla2x00_remove_one(struct pci_dev *pdev)
3570 {
3571 scsi_qla_host_t *base_vha;
3572 struct qla_hw_data *ha;
3573
3574 base_vha = pci_get_drvdata(pdev);
3575 ha = base_vha->hw;
3576
3577 /* Indicate device removal to prevent future board_disable and wait
3578 * until any pending board_disable has completed. */
3579 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3580 cancel_work_sync(&ha->board_disable);
3581
3582 /*
3583 * If the PCI device is disabled then there was a PCI-disconnect and
3584 * qla2x00_disable_board_on_pci_error has taken care of most of the
3585 * resources.
3586 */
3587 if (!atomic_read(&pdev->enable_cnt)) {
3588 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3589 base_vha->gnl.l, base_vha->gnl.ldma);
3590
3591 scsi_host_put(base_vha->host);
3592 kfree(ha);
3593 pci_set_drvdata(pdev, NULL);
3594 return;
3595 }
3596 qla2x00_wait_for_hba_ready(base_vha);
3597
3598 /*
3599 * if UNLOAD flag is already set, then continue unload,
3600 * where it was set first.
3601 */
3602 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3603 return;
3604
3605 set_bit(UNLOADING, &base_vha->dpc_flags);
3606
3607 qla_nvme_delete(base_vha);
3608
3609 dma_free_coherent(&ha->pdev->dev,
3610 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3611
3612 if (IS_QLAFX00(ha))
3613 qlafx00_driver_shutdown(base_vha, 20);
3614
3615 qla2x00_delete_all_vps(ha, base_vha);
3616
3617 if (IS_QLA8031(ha)) {
3618 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3619 "Clearing fcoe driver presence.\n");
3620 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3621 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3622 "Error while clearing DRV-Presence.\n");
3623 }
3624
3625 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3626
3627 qla2x00_dfs_remove(base_vha);
3628
3629 qla84xx_put_chip(base_vha);
3630
3631 /* Laser should be disabled only for ISP2031 */
3632 if (IS_QLA2031(ha))
3633 qla83xx_disable_laser(base_vha);
3634
3635 /* Disable timer */
3636 if (base_vha->timer_active)
3637 qla2x00_stop_timer(base_vha);
3638
3639 base_vha->flags.online = 0;
3640
3641 /* free DMA memory */
3642 if (ha->exlogin_buf)
3643 qla2x00_free_exlogin_buffer(ha);
3644
3645 /* free DMA memory */
3646 if (ha->exchoffld_buf)
3647 qla2x00_free_exchoffld_buffer(ha);
3648
3649 qla2x00_destroy_deferred_work(ha);
3650
3651 qlt_remove_target(ha, base_vha);
3652
3653 qla2x00_free_sysfs_attr(base_vha, true);
3654
3655 fc_remove_host(base_vha->host);
3656 qlt_remove_target_resources(ha);
3657
3658 scsi_remove_host(base_vha->host);
3659
3660 qla2x00_free_device(base_vha);
3661
3662 qla2x00_clear_drv_active(ha);
3663
3664 scsi_host_put(base_vha->host);
3665
3666 qla2x00_unmap_iobases(ha);
3667
3668 pci_release_selected_regions(ha->pdev, ha->bars);
3669 kfree(ha);
3670
3671 pci_disable_pcie_error_reporting(pdev);
3672
3673 pci_disable_device(pdev);
3674 }
3675
3676 static void
3677 qla2x00_free_device(scsi_qla_host_t *vha)
3678 {
3679 struct qla_hw_data *ha = vha->hw;
3680
3681 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3682
3683 /* Disable timer */
3684 if (vha->timer_active)
3685 qla2x00_stop_timer(vha);
3686
3687 qla25xx_delete_queues(vha);
3688
3689 if (ha->flags.fce_enabled)
3690 qla2x00_disable_fce_trace(vha, NULL, NULL);
3691
3692 if (ha->eft)
3693 qla2x00_disable_eft_trace(vha);
3694
3695 /* Stop currently executing firmware. */
3696 qla2x00_try_to_stop_firmware(vha);
3697
3698 vha->flags.online = 0;
3699
3700 /* turn-off interrupts on the card */
3701 if (ha->interrupts_on) {
3702 vha->flags.init_done = 0;
3703 ha->isp_ops->disable_intrs(ha);
3704 }
3705
3706 qla2x00_free_fcports(vha);
3707
3708 qla2x00_free_irqs(vha);
3709
3710 /* Flush the work queue and remove it */
3711 if (ha->wq) {
3712 flush_workqueue(ha->wq);
3713 destroy_workqueue(ha->wq);
3714 ha->wq = NULL;
3715 }
3716
3717
3718 qla2x00_mem_free(ha);
3719
3720 qla82xx_md_free(vha);
3721
3722 qla2x00_free_queues(ha);
3723 }
3724
3725 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3726 {
3727 fc_port_t *fcport, *tfcport;
3728
3729 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3730 list_del(&fcport->list);
3731 qla2x00_clear_loop_id(fcport);
3732 kfree(fcport);
3733 }
3734 }
3735
3736 static inline void
3737 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3738 int defer)
3739 {
3740 struct fc_rport *rport;
3741 scsi_qla_host_t *base_vha;
3742 unsigned long flags;
3743
3744 if (!fcport->rport)
3745 return;
3746
3747 rport = fcport->rport;
3748 if (defer) {
3749 base_vha = pci_get_drvdata(vha->hw->pdev);
3750 spin_lock_irqsave(vha->host->host_lock, flags);
3751 fcport->drport = rport;
3752 spin_unlock_irqrestore(vha->host->host_lock, flags);
3753 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3754 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3755 qla2xxx_wake_dpc(base_vha);
3756 } else {
3757 int now;
3758 if (rport) {
3759 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3760 "%s %8phN. rport %p roles %x\n",
3761 __func__, fcport->port_name, rport,
3762 rport->roles);
3763 fc_remote_port_delete(rport);
3764 }
3765 qlt_do_generation_tick(vha, &now);
3766 }
3767 }
3768
3769 /*
3770 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3771 *
3772 * Input: ha = adapter block pointer. fcport = port structure pointer.
3773 *
3774 * Return: None.
3775 *
3776 * Context:
3777 */
3778 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3779 int do_login, int defer)
3780 {
3781 if (IS_QLAFX00(vha->hw)) {
3782 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3783 qla2x00_schedule_rport_del(vha, fcport, defer);
3784 return;
3785 }
3786
3787 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3788 vha->vp_idx == fcport->vha->vp_idx) {
3789 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3790 qla2x00_schedule_rport_del(vha, fcport, defer);
3791 }
3792 /*
3793 * We may need to retry the login, so don't change the state of the
3794 * port but do the retries.
3795 */
3796 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3797 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3798
3799 if (!do_login)
3800 return;
3801
3802 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3803
3804 if (fcport->login_retry == 0) {
3805 fcport->login_retry = vha->hw->login_retry_count;
3806
3807 ql_dbg(ql_dbg_disc, vha, 0x20a3,
3808 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
3809 fcport->port_name, fcport->loop_id, fcport->login_retry);
3810 }
3811 }
3812
3813 /*
3814 * qla2x00_mark_all_devices_lost
3815 * Updates fcport state when device goes offline.
3816 *
3817 * Input:
3818 * ha = adapter block pointer.
3819 * fcport = port structure pointer.
3820 *
3821 * Return:
3822 * None.
3823 *
3824 * Context:
3825 */
3826 void
3827 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3828 {
3829 fc_port_t *fcport;
3830
3831 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3832 "Mark all dev lost\n");
3833
3834 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3835 fcport->scan_state = 0;
3836 qlt_schedule_sess_for_deletion_lock(fcport);
3837
3838 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3839 continue;
3840
3841 /*
3842 * No point in marking the device as lost, if the device is
3843 * already DEAD.
3844 */
3845 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3846 continue;
3847 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3848 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3849 if (defer)
3850 qla2x00_schedule_rport_del(vha, fcport, defer);
3851 else if (vha->vp_idx == fcport->vha->vp_idx)
3852 qla2x00_schedule_rport_del(vha, fcport, defer);
3853 }
3854 }
3855 }
3856
3857 /*
3858 * qla2x00_mem_alloc
3859 * Allocates adapter memory.
3860 *
3861 * Returns:
3862 * 0 = success.
3863 * !0 = failure.
3864 */
3865 static int
3866 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3867 struct req_que **req, struct rsp_que **rsp)
3868 {
3869 char name[16];
3870
3871 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3872 &ha->init_cb_dma, GFP_KERNEL);
3873 if (!ha->init_cb)
3874 goto fail;
3875
3876 if (qlt_mem_alloc(ha) < 0)
3877 goto fail_free_init_cb;
3878
3879 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3880 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3881 if (!ha->gid_list)
3882 goto fail_free_tgt_mem;
3883
3884 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3885 if (!ha->srb_mempool)
3886 goto fail_free_gid_list;
3887
3888 if (IS_P3P_TYPE(ha)) {
3889 /* Allocate cache for CT6 Ctx. */
3890 if (!ctx_cachep) {
3891 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3892 sizeof(struct ct6_dsd), 0,
3893 SLAB_HWCACHE_ALIGN, NULL);
3894 if (!ctx_cachep)
3895 goto fail_free_srb_mempool;
3896 }
3897 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3898 ctx_cachep);
3899 if (!ha->ctx_mempool)
3900 goto fail_free_srb_mempool;
3901 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3902 "ctx_cachep=%p ctx_mempool=%p.\n",
3903 ctx_cachep, ha->ctx_mempool);
3904 }
3905
3906 /* Get memory for cached NVRAM */
3907 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3908 if (!ha->nvram)
3909 goto fail_free_ctx_mempool;
3910
3911 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3912 ha->pdev->device);
3913 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3914 DMA_POOL_SIZE, 8, 0);
3915 if (!ha->s_dma_pool)
3916 goto fail_free_nvram;
3917
3918 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3919 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3920 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3921
3922 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3923 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3924 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3925 if (!ha->dl_dma_pool) {
3926 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3927 "Failed to allocate memory for dl_dma_pool.\n");
3928 goto fail_s_dma_pool;
3929 }
3930
3931 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3932 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3933 if (!ha->fcp_cmnd_dma_pool) {
3934 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3935 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3936 goto fail_dl_dma_pool;
3937 }
3938 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3939 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3940 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3941 }
3942
3943 /* Allocate memory for SNS commands */
3944 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3945 /* Get consistent memory allocated for SNS commands */
3946 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3947 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3948 if (!ha->sns_cmd)
3949 goto fail_dma_pool;
3950 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3951 "sns_cmd: %p.\n", ha->sns_cmd);
3952 } else {
3953 /* Get consistent memory allocated for MS IOCB */
3954 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3955 &ha->ms_iocb_dma);
3956 if (!ha->ms_iocb)
3957 goto fail_dma_pool;
3958 /* Get consistent memory allocated for CT SNS commands */
3959 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3960 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3961 if (!ha->ct_sns)
3962 goto fail_free_ms_iocb;
3963 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3964 "ms_iocb=%p ct_sns=%p.\n",
3965 ha->ms_iocb, ha->ct_sns);
3966 }
3967
3968 /* Allocate memory for request ring */
3969 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3970 if (!*req) {
3971 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3972 "Failed to allocate memory for req.\n");
3973 goto fail_req;
3974 }
3975 (*req)->length = req_len;
3976 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3977 ((*req)->length + 1) * sizeof(request_t),
3978 &(*req)->dma, GFP_KERNEL);
3979 if (!(*req)->ring) {
3980 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3981 "Failed to allocate memory for req_ring.\n");
3982 goto fail_req_ring;
3983 }
3984 /* Allocate memory for response ring */
3985 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3986 if (!*rsp) {
3987 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3988 "Failed to allocate memory for rsp.\n");
3989 goto fail_rsp;
3990 }
3991 (*rsp)->hw = ha;
3992 (*rsp)->length = rsp_len;
3993 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3994 ((*rsp)->length + 1) * sizeof(response_t),
3995 &(*rsp)->dma, GFP_KERNEL);
3996 if (!(*rsp)->ring) {
3997 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3998 "Failed to allocate memory for rsp_ring.\n");
3999 goto fail_rsp_ring;
4000 }
4001 (*req)->rsp = *rsp;
4002 (*rsp)->req = *req;
4003 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4004 "req=%p req->length=%d req->ring=%p rsp=%p "
4005 "rsp->length=%d rsp->ring=%p.\n",
4006 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4007 (*rsp)->ring);
4008 /* Allocate memory for NVRAM data for vports */
4009 if (ha->nvram_npiv_size) {
4010 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
4011 ha->nvram_npiv_size, GFP_KERNEL);
4012 if (!ha->npiv_info) {
4013 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4014 "Failed to allocate memory for npiv_info.\n");
4015 goto fail_npiv_info;
4016 }
4017 } else
4018 ha->npiv_info = NULL;
4019
4020 /* Get consistent memory allocated for EX-INIT-CB. */
4021 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
4022 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4023 &ha->ex_init_cb_dma);
4024 if (!ha->ex_init_cb)
4025 goto fail_ex_init_cb;
4026 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4027 "ex_init_cb=%p.\n", ha->ex_init_cb);
4028 }
4029
4030 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4031
4032 /* Get consistent memory allocated for Async Port-Database. */
4033 if (!IS_FWI2_CAPABLE(ha)) {
4034 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4035 &ha->async_pd_dma);
4036 if (!ha->async_pd)
4037 goto fail_async_pd;
4038 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4039 "async_pd=%p.\n", ha->async_pd);
4040 }
4041
4042 INIT_LIST_HEAD(&ha->vp_list);
4043
4044 /* Allocate memory for our loop_id bitmap */
4045 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4046 GFP_KERNEL);
4047 if (!ha->loop_id_map)
4048 goto fail_loop_id_map;
4049 else {
4050 qla2x00_set_reserved_loop_ids(ha);
4051 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4052 "loop_id_map=%p.\n", ha->loop_id_map);
4053 }
4054
4055 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4056 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4057 if (!ha->sfp_data) {
4058 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4059 "Unable to allocate memory for SFP read-data.\n");
4060 goto fail_sfp_data;
4061 }
4062
4063 return 0;
4064
4065 fail_sfp_data:
4066 kfree(ha->loop_id_map);
4067 fail_loop_id_map:
4068 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4069 fail_async_pd:
4070 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4071 fail_ex_init_cb:
4072 kfree(ha->npiv_info);
4073 fail_npiv_info:
4074 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4075 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4076 (*rsp)->ring = NULL;
4077 (*rsp)->dma = 0;
4078 fail_rsp_ring:
4079 kfree(*rsp);
4080 fail_rsp:
4081 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4082 sizeof(request_t), (*req)->ring, (*req)->dma);
4083 (*req)->ring = NULL;
4084 (*req)->dma = 0;
4085 fail_req_ring:
4086 kfree(*req);
4087 fail_req:
4088 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4089 ha->ct_sns, ha->ct_sns_dma);
4090 ha->ct_sns = NULL;
4091 ha->ct_sns_dma = 0;
4092 fail_free_ms_iocb:
4093 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4094 ha->ms_iocb = NULL;
4095 ha->ms_iocb_dma = 0;
4096
4097 if (ha->sns_cmd)
4098 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4099 ha->sns_cmd, ha->sns_cmd_dma);
4100 fail_dma_pool:
4101 if (IS_QLA82XX(ha) || ql2xenabledif) {
4102 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4103 ha->fcp_cmnd_dma_pool = NULL;
4104 }
4105 fail_dl_dma_pool:
4106 if (IS_QLA82XX(ha) || ql2xenabledif) {
4107 dma_pool_destroy(ha->dl_dma_pool);
4108 ha->dl_dma_pool = NULL;
4109 }
4110 fail_s_dma_pool:
4111 dma_pool_destroy(ha->s_dma_pool);
4112 ha->s_dma_pool = NULL;
4113 fail_free_nvram:
4114 kfree(ha->nvram);
4115 ha->nvram = NULL;
4116 fail_free_ctx_mempool:
4117 if (ha->ctx_mempool)
4118 mempool_destroy(ha->ctx_mempool);
4119 ha->ctx_mempool = NULL;
4120 fail_free_srb_mempool:
4121 if (ha->srb_mempool)
4122 mempool_destroy(ha->srb_mempool);
4123 ha->srb_mempool = NULL;
4124 fail_free_gid_list:
4125 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4126 ha->gid_list,
4127 ha->gid_list_dma);
4128 ha->gid_list = NULL;
4129 ha->gid_list_dma = 0;
4130 fail_free_tgt_mem:
4131 qlt_mem_free(ha);
4132 fail_free_init_cb:
4133 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4134 ha->init_cb_dma);
4135 ha->init_cb = NULL;
4136 ha->init_cb_dma = 0;
4137 fail:
4138 ql_log(ql_log_fatal, NULL, 0x0030,
4139 "Memory allocation failure.\n");
4140 return -ENOMEM;
4141 }
4142
4143 int
4144 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4145 {
4146 int rval;
4147 uint16_t size, max_cnt, temp;
4148 struct qla_hw_data *ha = vha->hw;
4149
4150 /* Return if we don't need to alloacate any extended logins */
4151 if (!ql2xexlogins)
4152 return QLA_SUCCESS;
4153
4154 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4155 return QLA_SUCCESS;
4156
4157 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4158 max_cnt = 0;
4159 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4160 if (rval != QLA_SUCCESS) {
4161 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4162 "Failed to get exlogin status.\n");
4163 return rval;
4164 }
4165
4166 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4167 temp *= size;
4168
4169 if (temp != ha->exlogin_size) {
4170 qla2x00_free_exlogin_buffer(ha);
4171 ha->exlogin_size = temp;
4172
4173 ql_log(ql_log_info, vha, 0xd024,
4174 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4175 max_cnt, size, temp);
4176
4177 ql_log(ql_log_info, vha, 0xd025,
4178 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4179
4180 /* Get consistent memory for extended logins */
4181 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4182 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4183 if (!ha->exlogin_buf) {
4184 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4185 "Failed to allocate memory for exlogin_buf_dma.\n");
4186 return -ENOMEM;
4187 }
4188 }
4189
4190 /* Now configure the dma buffer */
4191 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4192 if (rval) {
4193 ql_log(ql_log_fatal, vha, 0xd033,
4194 "Setup extended login buffer ****FAILED****.\n");
4195 qla2x00_free_exlogin_buffer(ha);
4196 }
4197
4198 return rval;
4199 }
4200
4201 /*
4202 * qla2x00_free_exlogin_buffer
4203 *
4204 * Input:
4205 * ha = adapter block pointer
4206 */
4207 void
4208 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4209 {
4210 if (ha->exlogin_buf) {
4211 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4212 ha->exlogin_buf, ha->exlogin_buf_dma);
4213 ha->exlogin_buf = NULL;
4214 ha->exlogin_size = 0;
4215 }
4216 }
4217
4218 static void
4219 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4220 {
4221 u32 temp;
4222 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4223
4224 if (qla_ini_mode_enabled(vha)) {
4225 if (ql2xiniexchg > max_cnt)
4226 ql2xiniexchg = max_cnt;
4227
4228 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4229 *ret_cnt = ql2xiniexchg;
4230 } else if (qla_tgt_mode_enabled(vha)) {
4231 if (ql2xexchoffld > max_cnt)
4232 ql2xexchoffld = max_cnt;
4233
4234 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4235 *ret_cnt = ql2xexchoffld;
4236 } else if (qla_dual_mode_enabled(vha)) {
4237 temp = ql2xiniexchg + ql2xexchoffld;
4238 if (temp > max_cnt) {
4239 ql2xiniexchg -= (temp - max_cnt)/2;
4240 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4241 temp = max_cnt;
4242 }
4243
4244 if (temp > FW_DEF_EXCHANGES_CNT)
4245 *ret_cnt = temp;
4246 }
4247 }
4248
4249 int
4250 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4251 {
4252 int rval;
4253 u16 size, max_cnt;
4254 u32 temp;
4255 struct qla_hw_data *ha = vha->hw;
4256
4257 if (!ha->flags.exchoffld_enabled)
4258 return QLA_SUCCESS;
4259
4260 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4261 return QLA_SUCCESS;
4262
4263 max_cnt = 0;
4264 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4265 if (rval != QLA_SUCCESS) {
4266 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4267 "Failed to get exlogin status.\n");
4268 return rval;
4269 }
4270
4271 qla2x00_number_of_exch(vha, &temp, max_cnt);
4272 temp *= size;
4273
4274 if (temp != ha->exchoffld_size) {
4275 qla2x00_free_exchoffld_buffer(ha);
4276 ha->exchoffld_size = temp;
4277
4278 ql_log(ql_log_info, vha, 0xd016,
4279 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4280 max_cnt, size, temp);
4281
4282 ql_log(ql_log_info, vha, 0xd017,
4283 "Exchange Buffers requested size = 0x%x\n",
4284 ha->exchoffld_size);
4285
4286 /* Get consistent memory for extended logins */
4287 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4288 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4289 if (!ha->exchoffld_buf) {
4290 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4291 "Failed to allocate memory for exchoffld_buf_dma.\n");
4292 return -ENOMEM;
4293 }
4294 }
4295
4296 /* Now configure the dma buffer */
4297 rval = qla_set_exchoffld_mem_cfg(vha);
4298 if (rval) {
4299 ql_log(ql_log_fatal, vha, 0xd02e,
4300 "Setup exchange offload buffer ****FAILED****.\n");
4301 qla2x00_free_exchoffld_buffer(ha);
4302 } else {
4303 /* re-adjust number of target exchange */
4304 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4305
4306 if (qla_ini_mode_enabled(vha))
4307 icb->exchange_count = 0;
4308 else
4309 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
4310 }
4311
4312 return rval;
4313 }
4314
4315 /*
4316 * qla2x00_free_exchoffld_buffer
4317 *
4318 * Input:
4319 * ha = adapter block pointer
4320 */
4321 void
4322 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4323 {
4324 if (ha->exchoffld_buf) {
4325 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4326 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4327 ha->exchoffld_buf = NULL;
4328 ha->exchoffld_size = 0;
4329 }
4330 }
4331
4332 /*
4333 * qla2x00_free_fw_dump
4334 * Frees fw dump stuff.
4335 *
4336 * Input:
4337 * ha = adapter block pointer
4338 */
4339 static void
4340 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4341 {
4342 if (ha->fce)
4343 dma_free_coherent(&ha->pdev->dev,
4344 FCE_SIZE, ha->fce, ha->fce_dma);
4345
4346 if (ha->eft)
4347 dma_free_coherent(&ha->pdev->dev,
4348 EFT_SIZE, ha->eft, ha->eft_dma);
4349
4350 if (ha->fw_dump)
4351 vfree(ha->fw_dump);
4352 if (ha->fw_dump_template)
4353 vfree(ha->fw_dump_template);
4354
4355 ha->fce = NULL;
4356 ha->fce_dma = 0;
4357 ha->eft = NULL;
4358 ha->eft_dma = 0;
4359 ha->fw_dumped = 0;
4360 ha->fw_dump_cap_flags = 0;
4361 ha->fw_dump_reading = 0;
4362 ha->fw_dump = NULL;
4363 ha->fw_dump_len = 0;
4364 ha->fw_dump_template = NULL;
4365 ha->fw_dump_template_len = 0;
4366 }
4367
4368 /*
4369 * qla2x00_mem_free
4370 * Frees all adapter allocated memory.
4371 *
4372 * Input:
4373 * ha = adapter block pointer.
4374 */
4375 static void
4376 qla2x00_mem_free(struct qla_hw_data *ha)
4377 {
4378 qla2x00_free_fw_dump(ha);
4379
4380 if (ha->mctp_dump)
4381 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4382 ha->mctp_dump_dma);
4383
4384 if (ha->srb_mempool)
4385 mempool_destroy(ha->srb_mempool);
4386
4387 if (ha->dcbx_tlv)
4388 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4389 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4390
4391 if (ha->xgmac_data)
4392 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4393 ha->xgmac_data, ha->xgmac_data_dma);
4394
4395 if (ha->sns_cmd)
4396 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4397 ha->sns_cmd, ha->sns_cmd_dma);
4398
4399 if (ha->ct_sns)
4400 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4401 ha->ct_sns, ha->ct_sns_dma);
4402
4403 if (ha->sfp_data)
4404 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4405 ha->sfp_data_dma);
4406
4407 if (ha->ms_iocb)
4408 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4409
4410 if (ha->ex_init_cb)
4411 dma_pool_free(ha->s_dma_pool,
4412 ha->ex_init_cb, ha->ex_init_cb_dma);
4413
4414 if (ha->async_pd)
4415 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4416
4417 if (ha->s_dma_pool)
4418 dma_pool_destroy(ha->s_dma_pool);
4419
4420 if (ha->gid_list)
4421 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4422 ha->gid_list, ha->gid_list_dma);
4423
4424 if (IS_QLA82XX(ha)) {
4425 if (!list_empty(&ha->gbl_dsd_list)) {
4426 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4427
4428 /* clean up allocated prev pool */
4429 list_for_each_entry_safe(dsd_ptr,
4430 tdsd_ptr, &ha->gbl_dsd_list, list) {
4431 dma_pool_free(ha->dl_dma_pool,
4432 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4433 list_del(&dsd_ptr->list);
4434 kfree(dsd_ptr);
4435 }
4436 }
4437 }
4438
4439 if (ha->dl_dma_pool)
4440 dma_pool_destroy(ha->dl_dma_pool);
4441
4442 if (ha->fcp_cmnd_dma_pool)
4443 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4444
4445 if (ha->ctx_mempool)
4446 mempool_destroy(ha->ctx_mempool);
4447
4448 qlt_mem_free(ha);
4449
4450 if (ha->init_cb)
4451 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4452 ha->init_cb, ha->init_cb_dma);
4453 vfree(ha->optrom_buffer);
4454 kfree(ha->nvram);
4455 kfree(ha->npiv_info);
4456 kfree(ha->swl);
4457 kfree(ha->loop_id_map);
4458
4459 ha->srb_mempool = NULL;
4460 ha->ctx_mempool = NULL;
4461 ha->sns_cmd = NULL;
4462 ha->sns_cmd_dma = 0;
4463 ha->ct_sns = NULL;
4464 ha->ct_sns_dma = 0;
4465 ha->ms_iocb = NULL;
4466 ha->ms_iocb_dma = 0;
4467 ha->init_cb = NULL;
4468 ha->init_cb_dma = 0;
4469 ha->ex_init_cb = NULL;
4470 ha->ex_init_cb_dma = 0;
4471 ha->async_pd = NULL;
4472 ha->async_pd_dma = 0;
4473
4474 ha->s_dma_pool = NULL;
4475 ha->dl_dma_pool = NULL;
4476 ha->fcp_cmnd_dma_pool = NULL;
4477
4478 ha->gid_list = NULL;
4479 ha->gid_list_dma = 0;
4480
4481 ha->tgt.atio_ring = NULL;
4482 ha->tgt.atio_dma = 0;
4483 ha->tgt.tgt_vp_map = NULL;
4484 }
4485
4486 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4487 struct qla_hw_data *ha)
4488 {
4489 struct Scsi_Host *host;
4490 struct scsi_qla_host *vha = NULL;
4491
4492 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4493 if (!host) {
4494 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4495 "Failed to allocate host from the scsi layer, aborting.\n");
4496 return NULL;
4497 }
4498
4499 /* Clear our data area */
4500 vha = shost_priv(host);
4501 memset(vha, 0, sizeof(scsi_qla_host_t));
4502
4503 vha->host = host;
4504 vha->host_no = host->host_no;
4505 vha->hw = ha;
4506
4507 INIT_LIST_HEAD(&vha->vp_fcports);
4508 INIT_LIST_HEAD(&vha->work_list);
4509 INIT_LIST_HEAD(&vha->list);
4510 INIT_LIST_HEAD(&vha->qla_cmd_list);
4511 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4512 INIT_LIST_HEAD(&vha->logo_list);
4513 INIT_LIST_HEAD(&vha->plogi_ack_list);
4514 INIT_LIST_HEAD(&vha->qp_list);
4515 INIT_LIST_HEAD(&vha->gnl.fcports);
4516 INIT_LIST_HEAD(&vha->nvme_rport_list);
4517
4518 spin_lock_init(&vha->work_lock);
4519 spin_lock_init(&vha->cmd_list_lock);
4520 init_waitqueue_head(&vha->fcport_waitQ);
4521 init_waitqueue_head(&vha->vref_waitq);
4522
4523 vha->gnl.size = sizeof(struct get_name_list_extended) *
4524 (ha->max_loop_id + 1);
4525 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4526 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4527 if (!vha->gnl.l) {
4528 ql_log(ql_log_fatal, vha, 0xd04a,
4529 "Alloc failed for name list.\n");
4530 scsi_remove_host(vha->host);
4531 return NULL;
4532 }
4533
4534 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
4535 ql_dbg(ql_dbg_init, vha, 0x0041,
4536 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4537 vha->host, vha->hw, vha,
4538 dev_name(&(ha->pdev->dev)));
4539
4540 return vha;
4541 }
4542
4543 struct qla_work_evt *
4544 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4545 {
4546 struct qla_work_evt *e;
4547 uint8_t bail;
4548
4549 QLA_VHA_MARK_BUSY(vha, bail);
4550 if (bail)
4551 return NULL;
4552
4553 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4554 if (!e) {
4555 QLA_VHA_MARK_NOT_BUSY(vha);
4556 return NULL;
4557 }
4558
4559 INIT_LIST_HEAD(&e->list);
4560 e->type = type;
4561 e->flags = QLA_EVT_FLAG_FREE;
4562 return e;
4563 }
4564
4565 int
4566 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4567 {
4568 unsigned long flags;
4569
4570 spin_lock_irqsave(&vha->work_lock, flags);
4571 list_add_tail(&e->list, &vha->work_list);
4572 spin_unlock_irqrestore(&vha->work_lock, flags);
4573
4574 if (QLA_EARLY_LINKUP(vha->hw))
4575 schedule_work(&vha->iocb_work);
4576 else
4577 qla2xxx_wake_dpc(vha);
4578
4579 return QLA_SUCCESS;
4580 }
4581
4582 int
4583 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4584 u32 data)
4585 {
4586 struct qla_work_evt *e;
4587
4588 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4589 if (!e)
4590 return QLA_FUNCTION_FAILED;
4591
4592 e->u.aen.code = code;
4593 e->u.aen.data = data;
4594 return qla2x00_post_work(vha, e);
4595 }
4596
4597 int
4598 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4599 {
4600 struct qla_work_evt *e;
4601
4602 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4603 if (!e)
4604 return QLA_FUNCTION_FAILED;
4605
4606 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4607 return qla2x00_post_work(vha, e);
4608 }
4609
4610 #define qla2x00_post_async_work(name, type) \
4611 int qla2x00_post_async_##name##_work( \
4612 struct scsi_qla_host *vha, \
4613 fc_port_t *fcport, uint16_t *data) \
4614 { \
4615 struct qla_work_evt *e; \
4616 \
4617 e = qla2x00_alloc_work(vha, type); \
4618 if (!e) \
4619 return QLA_FUNCTION_FAILED; \
4620 \
4621 e->u.logio.fcport = fcport; \
4622 if (data) { \
4623 e->u.logio.data[0] = data[0]; \
4624 e->u.logio.data[1] = data[1]; \
4625 } \
4626 return qla2x00_post_work(vha, e); \
4627 }
4628
4629 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4630 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4631 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
4632 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4633 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
4634
4635 int
4636 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4637 {
4638 struct qla_work_evt *e;
4639
4640 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4641 if (!e)
4642 return QLA_FUNCTION_FAILED;
4643
4644 e->u.uevent.code = code;
4645 return qla2x00_post_work(vha, e);
4646 }
4647
4648 static void
4649 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4650 {
4651 char event_string[40];
4652 char *envp[] = { event_string, NULL };
4653
4654 switch (code) {
4655 case QLA_UEVENT_CODE_FW_DUMP:
4656 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4657 vha->host_no);
4658 break;
4659 default:
4660 /* do nothing */
4661 break;
4662 }
4663 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4664 }
4665
4666 int
4667 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4668 uint32_t *data, int cnt)
4669 {
4670 struct qla_work_evt *e;
4671
4672 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4673 if (!e)
4674 return QLA_FUNCTION_FAILED;
4675
4676 e->u.aenfx.evtcode = evtcode;
4677 e->u.aenfx.count = cnt;
4678 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4679 return qla2x00_post_work(vha, e);
4680 }
4681
4682 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4683 {
4684 struct qla_work_evt *e;
4685
4686 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4687 if (!e)
4688 return QLA_FUNCTION_FAILED;
4689
4690 e->u.fcport.fcport = fcport;
4691 return qla2x00_post_work(vha, e);
4692 }
4693
4694 static
4695 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4696 {
4697 unsigned long flags;
4698 fc_port_t *fcport = NULL, *tfcp;
4699 struct qlt_plogi_ack_t *pla =
4700 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4701 uint8_t free_fcport = 0;
4702
4703 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4704 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4705 if (fcport) {
4706 fcport->d_id = e->u.new_sess.id;
4707 if (pla) {
4708 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4709 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4710 /* we took an extra ref_count to prevent PLOGI ACK when
4711 * fcport/sess has not been created.
4712 */
4713 pla->ref_count--;
4714 }
4715 } else {
4716 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4717 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4718 if (fcport) {
4719 fcport->d_id = e->u.new_sess.id;
4720 fcport->scan_state = QLA_FCPORT_FOUND;
4721 fcport->flags |= FCF_FABRIC_DEVICE;
4722 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4723
4724 memcpy(fcport->port_name, e->u.new_sess.port_name,
4725 WWN_SIZE);
4726 } else {
4727 ql_dbg(ql_dbg_disc, vha, 0xffff,
4728 "%s %8phC mem alloc fail.\n",
4729 __func__, e->u.new_sess.port_name);
4730
4731 if (pla)
4732 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4733 return;
4734 }
4735
4736 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4737 /* search again to make sure one else got ahead */
4738 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4739 e->u.new_sess.port_name, 1);
4740 if (tfcp) {
4741 /* should rarily happen */
4742 ql_dbg(ql_dbg_disc, vha, 0xffff,
4743 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4744 __func__, tfcp->port_name, tfcp->disc_state,
4745 tfcp->fw_login_state);
4746
4747 free_fcport = 1;
4748 } else {
4749 list_add_tail(&fcport->list, &vha->vp_fcports);
4750
4751 if (pla) {
4752 qlt_plogi_ack_link(vha, pla, fcport,
4753 QLT_PLOGI_LINK_SAME_WWN);
4754 pla->ref_count--;
4755 }
4756 }
4757 }
4758 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4759
4760 if (fcport) {
4761 if (pla)
4762 qlt_plogi_ack_unref(vha, pla);
4763 else
4764 qla24xx_async_gffid(vha, fcport);
4765 }
4766
4767 if (free_fcport) {
4768 qla2x00_free_fcport(fcport);
4769 if (pla)
4770 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4771 }
4772 }
4773
4774 void
4775 qla2x00_do_work(struct scsi_qla_host *vha)
4776 {
4777 struct qla_work_evt *e, *tmp;
4778 unsigned long flags;
4779 LIST_HEAD(work);
4780
4781 spin_lock_irqsave(&vha->work_lock, flags);
4782 list_splice_init(&vha->work_list, &work);
4783 spin_unlock_irqrestore(&vha->work_lock, flags);
4784
4785 list_for_each_entry_safe(e, tmp, &work, list) {
4786 list_del_init(&e->list);
4787
4788 switch (e->type) {
4789 case QLA_EVT_AEN:
4790 fc_host_post_event(vha->host, fc_get_event_number(),
4791 e->u.aen.code, e->u.aen.data);
4792 break;
4793 case QLA_EVT_IDC_ACK:
4794 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4795 break;
4796 case QLA_EVT_ASYNC_LOGIN:
4797 qla2x00_async_login(vha, e->u.logio.fcport,
4798 e->u.logio.data);
4799 break;
4800 case QLA_EVT_ASYNC_LOGOUT:
4801 qla2x00_async_logout(vha, e->u.logio.fcport);
4802 break;
4803 case QLA_EVT_ASYNC_LOGOUT_DONE:
4804 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4805 e->u.logio.data);
4806 break;
4807 case QLA_EVT_ASYNC_ADISC:
4808 qla2x00_async_adisc(vha, e->u.logio.fcport,
4809 e->u.logio.data);
4810 break;
4811 case QLA_EVT_ASYNC_ADISC_DONE:
4812 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4813 e->u.logio.data);
4814 break;
4815 case QLA_EVT_UEVENT:
4816 qla2x00_uevent_emit(vha, e->u.uevent.code);
4817 break;
4818 case QLA_EVT_AENFX:
4819 qlafx00_process_aen(vha, e);
4820 break;
4821 case QLA_EVT_GIDPN:
4822 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4823 break;
4824 case QLA_EVT_GPNID:
4825 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4826 break;
4827 case QLA_EVT_GPNID_DONE:
4828 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4829 break;
4830 case QLA_EVT_NEW_SESS:
4831 qla24xx_create_new_sess(vha, e);
4832 break;
4833 case QLA_EVT_GPDB:
4834 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4835 e->u.fcport.opt);
4836 break;
4837 case QLA_EVT_PRLI:
4838 qla24xx_async_prli(vha, e->u.fcport.fcport);
4839 break;
4840 case QLA_EVT_GPSC:
4841 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4842 break;
4843 case QLA_EVT_UPD_FCPORT:
4844 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4845 break;
4846 case QLA_EVT_GNL:
4847 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4848 break;
4849 case QLA_EVT_NACK:
4850 qla24xx_do_nack_work(vha, e);
4851 break;
4852 }
4853 if (e->flags & QLA_EVT_FLAG_FREE)
4854 kfree(e);
4855
4856 /* For each work completed decrement vha ref count */
4857 QLA_VHA_MARK_NOT_BUSY(vha);
4858 }
4859 }
4860
4861 /* Relogins all the fcports of a vport
4862 * Context: dpc thread
4863 */
4864 void qla2x00_relogin(struct scsi_qla_host *vha)
4865 {
4866 fc_port_t *fcport;
4867 int status;
4868 struct event_arg ea;
4869
4870 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4871 /*
4872 * If the port is not ONLINE then try to login
4873 * to it if we haven't run out of retries.
4874 */
4875 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4876 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4877 fcport->login_retry--;
4878 if (fcport->flags & FCF_FABRIC_DEVICE) {
4879 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
4880 "%s %8phC DS %d LS %d\n", __func__,
4881 fcport->port_name, fcport->disc_state,
4882 fcport->fw_login_state);
4883 memset(&ea, 0, sizeof(ea));
4884 ea.event = FCME_RELOGIN;
4885 ea.fcport = fcport;
4886 qla2x00_fcport_event_handler(vha, &ea);
4887 } else {
4888 status = qla2x00_local_device_login(vha,
4889 fcport);
4890 if (status == QLA_SUCCESS) {
4891 fcport->old_loop_id = fcport->loop_id;
4892 ql_dbg(ql_dbg_disc, vha, 0x2003,
4893 "Port login OK: logged in ID 0x%x.\n",
4894 fcport->loop_id);
4895 qla2x00_update_fcport(vha, fcport);
4896 } else if (status == 1) {
4897 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4898 /* retry the login again */
4899 ql_dbg(ql_dbg_disc, vha, 0x2007,
4900 "Retrying %d login again loop_id 0x%x.\n",
4901 fcport->login_retry,
4902 fcport->loop_id);
4903 } else {
4904 fcport->login_retry = 0;
4905 }
4906
4907 if (fcport->login_retry == 0 &&
4908 status != QLA_SUCCESS)
4909 qla2x00_clear_loop_id(fcport);
4910 }
4911 }
4912 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4913 break;
4914 }
4915 }
4916
4917 /* Schedule work on any of the dpc-workqueues */
4918 void
4919 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4920 {
4921 struct qla_hw_data *ha = base_vha->hw;
4922
4923 switch (work_code) {
4924 case MBA_IDC_AEN: /* 0x8200 */
4925 if (ha->dpc_lp_wq)
4926 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4927 break;
4928
4929 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4930 if (!ha->flags.nic_core_reset_hdlr_active) {
4931 if (ha->dpc_hp_wq)
4932 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4933 } else
4934 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4935 "NIC Core reset is already active. Skip "
4936 "scheduling it again.\n");
4937 break;
4938 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4939 if (ha->dpc_hp_wq)
4940 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4941 break;
4942 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4943 if (ha->dpc_hp_wq)
4944 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4945 break;
4946 default:
4947 ql_log(ql_log_warn, base_vha, 0xb05f,
4948 "Unknown work-code=0x%x.\n", work_code);
4949 }
4950
4951 return;
4952 }
4953
4954 /* Work: Perform NIC Core Unrecoverable state handling */
4955 void
4956 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4957 {
4958 struct qla_hw_data *ha =
4959 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4960 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4961 uint32_t dev_state = 0;
4962
4963 qla83xx_idc_lock(base_vha, 0);
4964 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4965 qla83xx_reset_ownership(base_vha);
4966 if (ha->flags.nic_core_reset_owner) {
4967 ha->flags.nic_core_reset_owner = 0;
4968 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4969 QLA8XXX_DEV_FAILED);
4970 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4971 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4972 }
4973 qla83xx_idc_unlock(base_vha, 0);
4974 }
4975
4976 /* Work: Execute IDC state handler */
4977 void
4978 qla83xx_idc_state_handler_work(struct work_struct *work)
4979 {
4980 struct qla_hw_data *ha =
4981 container_of(work, struct qla_hw_data, idc_state_handler);
4982 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4983 uint32_t dev_state = 0;
4984
4985 qla83xx_idc_lock(base_vha, 0);
4986 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4987 if (dev_state == QLA8XXX_DEV_FAILED ||
4988 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4989 qla83xx_idc_state_handler(base_vha);
4990 qla83xx_idc_unlock(base_vha, 0);
4991 }
4992
4993 static int
4994 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4995 {
4996 int rval = QLA_SUCCESS;
4997 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4998 uint32_t heart_beat_counter1, heart_beat_counter2;
4999
5000 do {
5001 if (time_after(jiffies, heart_beat_wait)) {
5002 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5003 "Nic Core f/w is not alive.\n");
5004 rval = QLA_FUNCTION_FAILED;
5005 break;
5006 }
5007
5008 qla83xx_idc_lock(base_vha, 0);
5009 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5010 &heart_beat_counter1);
5011 qla83xx_idc_unlock(base_vha, 0);
5012 msleep(100);
5013 qla83xx_idc_lock(base_vha, 0);
5014 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5015 &heart_beat_counter2);
5016 qla83xx_idc_unlock(base_vha, 0);
5017 } while (heart_beat_counter1 == heart_beat_counter2);
5018
5019 return rval;
5020 }
5021
5022 /* Work: Perform NIC Core Reset handling */
5023 void
5024 qla83xx_nic_core_reset_work(struct work_struct *work)
5025 {
5026 struct qla_hw_data *ha =
5027 container_of(work, struct qla_hw_data, nic_core_reset);
5028 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5029 uint32_t dev_state = 0;
5030
5031 if (IS_QLA2031(ha)) {
5032 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5033 ql_log(ql_log_warn, base_vha, 0xb081,
5034 "Failed to dump mctp\n");
5035 return;
5036 }
5037
5038 if (!ha->flags.nic_core_reset_hdlr_active) {
5039 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5040 qla83xx_idc_lock(base_vha, 0);
5041 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5042 &dev_state);
5043 qla83xx_idc_unlock(base_vha, 0);
5044 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5045 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5046 "Nic Core f/w is alive.\n");
5047 return;
5048 }
5049 }
5050
5051 ha->flags.nic_core_reset_hdlr_active = 1;
5052 if (qla83xx_nic_core_reset(base_vha)) {
5053 /* NIC Core reset failed. */
5054 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5055 "NIC Core reset failed.\n");
5056 }
5057 ha->flags.nic_core_reset_hdlr_active = 0;
5058 }
5059 }
5060
5061 /* Work: Handle 8200 IDC aens */
5062 void
5063 qla83xx_service_idc_aen(struct work_struct *work)
5064 {
5065 struct qla_hw_data *ha =
5066 container_of(work, struct qla_hw_data, idc_aen);
5067 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5068 uint32_t dev_state, idc_control;
5069
5070 qla83xx_idc_lock(base_vha, 0);
5071 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5072 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5073 qla83xx_idc_unlock(base_vha, 0);
5074 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5075 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5076 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5077 "Application requested NIC Core Reset.\n");
5078 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5079 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5080 QLA_SUCCESS) {
5081 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5082 "Other protocol driver requested NIC Core Reset.\n");
5083 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5084 }
5085 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5086 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5087 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5088 }
5089 }
5090
5091 static void
5092 qla83xx_wait_logic(void)
5093 {
5094 int i;
5095
5096 /* Yield CPU */
5097 if (!in_interrupt()) {
5098 /*
5099 * Wait about 200ms before retrying again.
5100 * This controls the number of retries for single
5101 * lock operation.
5102 */
5103 msleep(100);
5104 schedule();
5105 } else {
5106 for (i = 0; i < 20; i++)
5107 cpu_relax(); /* This a nop instr on i386 */
5108 }
5109 }
5110
5111 static int
5112 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5113 {
5114 int rval;
5115 uint32_t data;
5116 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5117 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5118 struct qla_hw_data *ha = base_vha->hw;
5119 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5120 "Trying force recovery of the IDC lock.\n");
5121
5122 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5123 if (rval)
5124 return rval;
5125
5126 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5127 return QLA_SUCCESS;
5128 } else {
5129 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5130 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5131 data);
5132 if (rval)
5133 return rval;
5134
5135 msleep(200);
5136
5137 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5138 &data);
5139 if (rval)
5140 return rval;
5141
5142 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5143 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5144 ~(idc_lck_rcvry_stage_mask));
5145 rval = qla83xx_wr_reg(base_vha,
5146 QLA83XX_IDC_LOCK_RECOVERY, data);
5147 if (rval)
5148 return rval;
5149
5150 /* Forcefully perform IDC UnLock */
5151 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5152 &data);
5153 if (rval)
5154 return rval;
5155 /* Clear lock-id by setting 0xff */
5156 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5157 0xff);
5158 if (rval)
5159 return rval;
5160 /* Clear lock-recovery by setting 0x0 */
5161 rval = qla83xx_wr_reg(base_vha,
5162 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5163 if (rval)
5164 return rval;
5165 } else
5166 return QLA_SUCCESS;
5167 }
5168
5169 return rval;
5170 }
5171
5172 static int
5173 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5174 {
5175 int rval = QLA_SUCCESS;
5176 uint32_t o_drv_lockid, n_drv_lockid;
5177 unsigned long lock_recovery_timeout;
5178
5179 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5180 retry_lockid:
5181 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5182 if (rval)
5183 goto exit;
5184
5185 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5186 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5187 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5188 return QLA_SUCCESS;
5189 else
5190 return QLA_FUNCTION_FAILED;
5191 }
5192
5193 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5194 if (rval)
5195 goto exit;
5196
5197 if (o_drv_lockid == n_drv_lockid) {
5198 qla83xx_wait_logic();
5199 goto retry_lockid;
5200 } else
5201 return QLA_SUCCESS;
5202
5203 exit:
5204 return rval;
5205 }
5206
5207 void
5208 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5209 {
5210 uint16_t options = (requester_id << 15) | BIT_6;
5211 uint32_t data;
5212 uint32_t lock_owner;
5213 struct qla_hw_data *ha = base_vha->hw;
5214
5215 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5216 retry_lock:
5217 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5218 == QLA_SUCCESS) {
5219 if (data) {
5220 /* Setting lock-id to our function-number */
5221 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5222 ha->portnum);
5223 } else {
5224 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5225 &lock_owner);
5226 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5227 "Failed to acquire IDC lock, acquired by %d, "
5228 "retrying...\n", lock_owner);
5229
5230 /* Retry/Perform IDC-Lock recovery */
5231 if (qla83xx_idc_lock_recovery(base_vha)
5232 == QLA_SUCCESS) {
5233 qla83xx_wait_logic();
5234 goto retry_lock;
5235 } else
5236 ql_log(ql_log_warn, base_vha, 0xb075,
5237 "IDC Lock recovery FAILED.\n");
5238 }
5239
5240 }
5241
5242 return;
5243
5244 /* XXX: IDC-lock implementation using access-control mbx */
5245 retry_lock2:
5246 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5247 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5248 "Failed to acquire IDC lock. retrying...\n");
5249 /* Retry/Perform IDC-Lock recovery */
5250 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5251 qla83xx_wait_logic();
5252 goto retry_lock2;
5253 } else
5254 ql_log(ql_log_warn, base_vha, 0xb076,
5255 "IDC Lock recovery FAILED.\n");
5256 }
5257
5258 return;
5259 }
5260
5261 void
5262 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5263 {
5264 #if 0
5265 uint16_t options = (requester_id << 15) | BIT_7;
5266 #endif
5267 uint16_t retry;
5268 uint32_t data;
5269 struct qla_hw_data *ha = base_vha->hw;
5270
5271 /* IDC-unlock implementation using driver-unlock/lock-id
5272 * remote registers
5273 */
5274 retry = 0;
5275 retry_unlock:
5276 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5277 == QLA_SUCCESS) {
5278 if (data == ha->portnum) {
5279 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5280 /* Clearing lock-id by setting 0xff */
5281 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5282 } else if (retry < 10) {
5283 /* SV: XXX: IDC unlock retrying needed here? */
5284
5285 /* Retry for IDC-unlock */
5286 qla83xx_wait_logic();
5287 retry++;
5288 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
5289 "Failed to release IDC lock, retrying=%d\n", retry);
5290 goto retry_unlock;
5291 }
5292 } else if (retry < 10) {
5293 /* Retry for IDC-unlock */
5294 qla83xx_wait_logic();
5295 retry++;
5296 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
5297 "Failed to read drv-lockid, retrying=%d\n", retry);
5298 goto retry_unlock;
5299 }
5300
5301 return;
5302
5303 #if 0
5304 /* XXX: IDC-unlock implementation using access-control mbx */
5305 retry = 0;
5306 retry_unlock2:
5307 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5308 if (retry < 10) {
5309 /* Retry for IDC-unlock */
5310 qla83xx_wait_logic();
5311 retry++;
5312 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
5313 "Failed to release IDC lock, retrying=%d\n", retry);
5314 goto retry_unlock2;
5315 }
5316 }
5317
5318 return;
5319 #endif
5320 }
5321
5322 int
5323 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5324 {
5325 int rval = QLA_SUCCESS;
5326 struct qla_hw_data *ha = vha->hw;
5327 uint32_t drv_presence;
5328
5329 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5330 if (rval == QLA_SUCCESS) {
5331 drv_presence |= (1 << ha->portnum);
5332 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5333 drv_presence);
5334 }
5335
5336 return rval;
5337 }
5338
5339 int
5340 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5341 {
5342 int rval = QLA_SUCCESS;
5343
5344 qla83xx_idc_lock(vha, 0);
5345 rval = __qla83xx_set_drv_presence(vha);
5346 qla83xx_idc_unlock(vha, 0);
5347
5348 return rval;
5349 }
5350
5351 int
5352 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5353 {
5354 int rval = QLA_SUCCESS;
5355 struct qla_hw_data *ha = vha->hw;
5356 uint32_t drv_presence;
5357
5358 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5359 if (rval == QLA_SUCCESS) {
5360 drv_presence &= ~(1 << ha->portnum);
5361 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5362 drv_presence);
5363 }
5364
5365 return rval;
5366 }
5367
5368 int
5369 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5370 {
5371 int rval = QLA_SUCCESS;
5372
5373 qla83xx_idc_lock(vha, 0);
5374 rval = __qla83xx_clear_drv_presence(vha);
5375 qla83xx_idc_unlock(vha, 0);
5376
5377 return rval;
5378 }
5379
5380 static void
5381 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5382 {
5383 struct qla_hw_data *ha = vha->hw;
5384 uint32_t drv_ack, drv_presence;
5385 unsigned long ack_timeout;
5386
5387 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5388 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5389 while (1) {
5390 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5391 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5392 if ((drv_ack & drv_presence) == drv_presence)
5393 break;
5394
5395 if (time_after_eq(jiffies, ack_timeout)) {
5396 ql_log(ql_log_warn, vha, 0xb067,
5397 "RESET ACK TIMEOUT! drv_presence=0x%x "
5398 "drv_ack=0x%x\n", drv_presence, drv_ack);
5399 /*
5400 * The function(s) which did not ack in time are forced
5401 * to withdraw any further participation in the IDC
5402 * reset.
5403 */
5404 if (drv_ack != drv_presence)
5405 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5406 drv_ack);
5407 break;
5408 }
5409
5410 qla83xx_idc_unlock(vha, 0);
5411 msleep(1000);
5412 qla83xx_idc_lock(vha, 0);
5413 }
5414
5415 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5416 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5417 }
5418
5419 static int
5420 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5421 {
5422 int rval = QLA_SUCCESS;
5423 uint32_t idc_control;
5424
5425 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5426 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5427
5428 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5429 __qla83xx_get_idc_control(vha, &idc_control);
5430 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5431 __qla83xx_set_idc_control(vha, 0);
5432
5433 qla83xx_idc_unlock(vha, 0);
5434 rval = qla83xx_restart_nic_firmware(vha);
5435 qla83xx_idc_lock(vha, 0);
5436
5437 if (rval != QLA_SUCCESS) {
5438 ql_log(ql_log_fatal, vha, 0xb06a,
5439 "Failed to restart NIC f/w.\n");
5440 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5441 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5442 } else {
5443 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5444 "Success in restarting nic f/w.\n");
5445 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5446 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5447 }
5448
5449 return rval;
5450 }
5451
5452 /* Assumes idc_lock always held on entry */
5453 int
5454 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5455 {
5456 struct qla_hw_data *ha = base_vha->hw;
5457 int rval = QLA_SUCCESS;
5458 unsigned long dev_init_timeout;
5459 uint32_t dev_state;
5460
5461 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5462 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5463
5464 while (1) {
5465
5466 if (time_after_eq(jiffies, dev_init_timeout)) {
5467 ql_log(ql_log_warn, base_vha, 0xb06e,
5468 "Initialization TIMEOUT!\n");
5469 /* Init timeout. Disable further NIC Core
5470 * communication.
5471 */
5472 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5473 QLA8XXX_DEV_FAILED);
5474 ql_log(ql_log_info, base_vha, 0xb06f,
5475 "HW State: FAILED.\n");
5476 }
5477
5478 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5479 switch (dev_state) {
5480 case QLA8XXX_DEV_READY:
5481 if (ha->flags.nic_core_reset_owner)
5482 qla83xx_idc_audit(base_vha,
5483 IDC_AUDIT_COMPLETION);
5484 ha->flags.nic_core_reset_owner = 0;
5485 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5486 "Reset_owner reset by 0x%x.\n",
5487 ha->portnum);
5488 goto exit;
5489 case QLA8XXX_DEV_COLD:
5490 if (ha->flags.nic_core_reset_owner)
5491 rval = qla83xx_device_bootstrap(base_vha);
5492 else {
5493 /* Wait for AEN to change device-state */
5494 qla83xx_idc_unlock(base_vha, 0);
5495 msleep(1000);
5496 qla83xx_idc_lock(base_vha, 0);
5497 }
5498 break;
5499 case QLA8XXX_DEV_INITIALIZING:
5500 /* Wait for AEN to change device-state */
5501 qla83xx_idc_unlock(base_vha, 0);
5502 msleep(1000);
5503 qla83xx_idc_lock(base_vha, 0);
5504 break;
5505 case QLA8XXX_DEV_NEED_RESET:
5506 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5507 qla83xx_need_reset_handler(base_vha);
5508 else {
5509 /* Wait for AEN to change device-state */
5510 qla83xx_idc_unlock(base_vha, 0);
5511 msleep(1000);
5512 qla83xx_idc_lock(base_vha, 0);
5513 }
5514 /* reset timeout value after need reset handler */
5515 dev_init_timeout = jiffies +
5516 (ha->fcoe_dev_init_timeout * HZ);
5517 break;
5518 case QLA8XXX_DEV_NEED_QUIESCENT:
5519 /* XXX: DEBUG for now */
5520 qla83xx_idc_unlock(base_vha, 0);
5521 msleep(1000);
5522 qla83xx_idc_lock(base_vha, 0);
5523 break;
5524 case QLA8XXX_DEV_QUIESCENT:
5525 /* XXX: DEBUG for now */
5526 if (ha->flags.quiesce_owner)
5527 goto exit;
5528
5529 qla83xx_idc_unlock(base_vha, 0);
5530 msleep(1000);
5531 qla83xx_idc_lock(base_vha, 0);
5532 dev_init_timeout = jiffies +
5533 (ha->fcoe_dev_init_timeout * HZ);
5534 break;
5535 case QLA8XXX_DEV_FAILED:
5536 if (ha->flags.nic_core_reset_owner)
5537 qla83xx_idc_audit(base_vha,
5538 IDC_AUDIT_COMPLETION);
5539 ha->flags.nic_core_reset_owner = 0;
5540 __qla83xx_clear_drv_presence(base_vha);
5541 qla83xx_idc_unlock(base_vha, 0);
5542 qla8xxx_dev_failed_handler(base_vha);
5543 rval = QLA_FUNCTION_FAILED;
5544 qla83xx_idc_lock(base_vha, 0);
5545 goto exit;
5546 case QLA8XXX_BAD_VALUE:
5547 qla83xx_idc_unlock(base_vha, 0);
5548 msleep(1000);
5549 qla83xx_idc_lock(base_vha, 0);
5550 break;
5551 default:
5552 ql_log(ql_log_warn, base_vha, 0xb071,
5553 "Unknown Device State: %x.\n", dev_state);
5554 qla83xx_idc_unlock(base_vha, 0);
5555 qla8xxx_dev_failed_handler(base_vha);
5556 rval = QLA_FUNCTION_FAILED;
5557 qla83xx_idc_lock(base_vha, 0);
5558 goto exit;
5559 }
5560 }
5561
5562 exit:
5563 return rval;
5564 }
5565
5566 void
5567 qla2x00_disable_board_on_pci_error(struct work_struct *work)
5568 {
5569 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5570 board_disable);
5571 struct pci_dev *pdev = ha->pdev;
5572 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5573
5574 /*
5575 * if UNLOAD flag is already set, then continue unload,
5576 * where it was set first.
5577 */
5578 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5579 return;
5580
5581 ql_log(ql_log_warn, base_vha, 0x015b,
5582 "Disabling adapter.\n");
5583
5584 if (!atomic_read(&pdev->enable_cnt)) {
5585 ql_log(ql_log_info, base_vha, 0xfffc,
5586 "PCI device disabled, no action req for PCI error=%lx\n",
5587 base_vha->pci_flags);
5588 return;
5589 }
5590
5591 qla2x00_wait_for_sess_deletion(base_vha);
5592
5593 set_bit(UNLOADING, &base_vha->dpc_flags);
5594
5595 qla2x00_delete_all_vps(ha, base_vha);
5596
5597 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5598
5599 qla2x00_dfs_remove(base_vha);
5600
5601 qla84xx_put_chip(base_vha);
5602
5603 if (base_vha->timer_active)
5604 qla2x00_stop_timer(base_vha);
5605
5606 base_vha->flags.online = 0;
5607
5608 qla2x00_destroy_deferred_work(ha);
5609
5610 /*
5611 * Do not try to stop beacon blink as it will issue a mailbox
5612 * command.
5613 */
5614 qla2x00_free_sysfs_attr(base_vha, false);
5615
5616 fc_remove_host(base_vha->host);
5617
5618 scsi_remove_host(base_vha->host);
5619
5620 base_vha->flags.init_done = 0;
5621 qla25xx_delete_queues(base_vha);
5622 qla2x00_free_fcports(base_vha);
5623 qla2x00_free_irqs(base_vha);
5624 qla2x00_mem_free(ha);
5625 qla82xx_md_free(base_vha);
5626 qla2x00_free_queues(ha);
5627
5628 qla2x00_unmap_iobases(ha);
5629
5630 pci_release_selected_regions(ha->pdev, ha->bars);
5631 pci_disable_pcie_error_reporting(pdev);
5632 pci_disable_device(pdev);
5633
5634 /*
5635 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5636 */
5637 }
5638
5639 /**************************************************************************
5640 * qla2x00_do_dpc
5641 * This kernel thread is a task that is schedule by the interrupt handler
5642 * to perform the background processing for interrupts.
5643 *
5644 * Notes:
5645 * This task always run in the context of a kernel thread. It
5646 * is kick-off by the driver's detect code and starts up
5647 * up one per adapter. It immediately goes to sleep and waits for
5648 * some fibre event. When either the interrupt handler or
5649 * the timer routine detects a event it will one of the task
5650 * bits then wake us up.
5651 **************************************************************************/
5652 static int
5653 qla2x00_do_dpc(void *data)
5654 {
5655 scsi_qla_host_t *base_vha;
5656 struct qla_hw_data *ha;
5657 uint32_t online;
5658 struct qla_qpair *qpair;
5659
5660 ha = (struct qla_hw_data *)data;
5661 base_vha = pci_get_drvdata(ha->pdev);
5662
5663 set_user_nice(current, MIN_NICE);
5664
5665 set_current_state(TASK_INTERRUPTIBLE);
5666 while (!kthread_should_stop()) {
5667 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5668 "DPC handler sleeping.\n");
5669
5670 schedule();
5671
5672 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5673 goto end_loop;
5674
5675 if (ha->flags.eeh_busy) {
5676 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5677 "eeh_busy=%d.\n", ha->flags.eeh_busy);
5678 goto end_loop;
5679 }
5680
5681 ha->dpc_active = 1;
5682
5683 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5684 "DPC handler waking up, dpc_flags=0x%lx.\n",
5685 base_vha->dpc_flags);
5686
5687 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5688 break;
5689
5690 qla2x00_do_work(base_vha);
5691
5692 if (IS_P3P_TYPE(ha)) {
5693 if (IS_QLA8044(ha)) {
5694 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5695 &base_vha->dpc_flags)) {
5696 qla8044_idc_lock(ha);
5697 qla8044_wr_direct(base_vha,
5698 QLA8044_CRB_DEV_STATE_INDEX,
5699 QLA8XXX_DEV_FAILED);
5700 qla8044_idc_unlock(ha);
5701 ql_log(ql_log_info, base_vha, 0x4004,
5702 "HW State: FAILED.\n");
5703 qla8044_device_state_handler(base_vha);
5704 continue;
5705 }
5706
5707 } else {
5708 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5709 &base_vha->dpc_flags)) {
5710 qla82xx_idc_lock(ha);
5711 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5712 QLA8XXX_DEV_FAILED);
5713 qla82xx_idc_unlock(ha);
5714 ql_log(ql_log_info, base_vha, 0x0151,
5715 "HW State: FAILED.\n");
5716 qla82xx_device_state_handler(base_vha);
5717 continue;
5718 }
5719 }
5720
5721 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5722 &base_vha->dpc_flags)) {
5723
5724 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5725 "FCoE context reset scheduled.\n");
5726 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5727 &base_vha->dpc_flags))) {
5728 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5729 /* FCoE-ctx reset failed.
5730 * Escalate to chip-reset
5731 */
5732 set_bit(ISP_ABORT_NEEDED,
5733 &base_vha->dpc_flags);
5734 }
5735 clear_bit(ABORT_ISP_ACTIVE,
5736 &base_vha->dpc_flags);
5737 }
5738
5739 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5740 "FCoE context reset end.\n");
5741 }
5742 } else if (IS_QLAFX00(ha)) {
5743 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5744 &base_vha->dpc_flags)) {
5745 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5746 "Firmware Reset Recovery\n");
5747 if (qlafx00_reset_initialize(base_vha)) {
5748 /* Failed. Abort isp later. */
5749 if (!test_bit(UNLOADING,
5750 &base_vha->dpc_flags)) {
5751 set_bit(ISP_UNRECOVERABLE,
5752 &base_vha->dpc_flags);
5753 ql_dbg(ql_dbg_dpc, base_vha,
5754 0x4021,
5755 "Reset Recovery Failed\n");
5756 }
5757 }
5758 }
5759
5760 if (test_and_clear_bit(FX00_TARGET_SCAN,
5761 &base_vha->dpc_flags)) {
5762 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5763 "ISPFx00 Target Scan scheduled\n");
5764 if (qlafx00_rescan_isp(base_vha)) {
5765 if (!test_bit(UNLOADING,
5766 &base_vha->dpc_flags))
5767 set_bit(ISP_UNRECOVERABLE,
5768 &base_vha->dpc_flags);
5769 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5770 "ISPFx00 Target Scan Failed\n");
5771 }
5772 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5773 "ISPFx00 Target Scan End\n");
5774 }
5775 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5776 &base_vha->dpc_flags)) {
5777 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5778 "ISPFx00 Host Info resend scheduled\n");
5779 qlafx00_fx_disc(base_vha,
5780 &base_vha->hw->mr.fcport,
5781 FXDISC_REG_HOST_INFO);
5782 }
5783 }
5784
5785 if (test_and_clear_bit(DETECT_SFP_CHANGE,
5786 &base_vha->dpc_flags) &&
5787 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
5788 qla24xx_detect_sfp(base_vha);
5789
5790 if (ha->flags.detected_lr_sfp !=
5791 ha->flags.using_lr_setting)
5792 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
5793 }
5794
5795 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5796 &base_vha->dpc_flags)) {
5797
5798 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5799 "ISP abort scheduled.\n");
5800 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5801 &base_vha->dpc_flags))) {
5802
5803 if (ha->isp_ops->abort_isp(base_vha)) {
5804 /* failed. retry later */
5805 set_bit(ISP_ABORT_NEEDED,
5806 &base_vha->dpc_flags);
5807 }
5808 clear_bit(ABORT_ISP_ACTIVE,
5809 &base_vha->dpc_flags);
5810 }
5811
5812 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5813 "ISP abort end.\n");
5814 }
5815
5816 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5817 &base_vha->dpc_flags)) {
5818 qla2x00_update_fcports(base_vha);
5819 }
5820
5821 if (IS_QLAFX00(ha))
5822 goto loop_resync_check;
5823
5824 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
5825 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5826 "Quiescence mode scheduled.\n");
5827 if (IS_P3P_TYPE(ha)) {
5828 if (IS_QLA82XX(ha))
5829 qla82xx_device_state_handler(base_vha);
5830 if (IS_QLA8044(ha))
5831 qla8044_device_state_handler(base_vha);
5832 clear_bit(ISP_QUIESCE_NEEDED,
5833 &base_vha->dpc_flags);
5834 if (!ha->flags.quiesce_owner) {
5835 qla2x00_perform_loop_resync(base_vha);
5836 if (IS_QLA82XX(ha)) {
5837 qla82xx_idc_lock(ha);
5838 qla82xx_clear_qsnt_ready(
5839 base_vha);
5840 qla82xx_idc_unlock(ha);
5841 } else if (IS_QLA8044(ha)) {
5842 qla8044_idc_lock(ha);
5843 qla8044_clear_qsnt_ready(
5844 base_vha);
5845 qla8044_idc_unlock(ha);
5846 }
5847 }
5848 } else {
5849 clear_bit(ISP_QUIESCE_NEEDED,
5850 &base_vha->dpc_flags);
5851 qla2x00_quiesce_io(base_vha);
5852 }
5853 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5854 "Quiescence mode end.\n");
5855 }
5856
5857 if (test_and_clear_bit(RESET_MARKER_NEEDED,
5858 &base_vha->dpc_flags) &&
5859 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5860
5861 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5862 "Reset marker scheduled.\n");
5863 qla2x00_rst_aen(base_vha);
5864 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5865 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5866 "Reset marker end.\n");
5867 }
5868
5869 /* Retry each device up to login retry count */
5870 if ((test_and_clear_bit(RELOGIN_NEEDED,
5871 &base_vha->dpc_flags)) &&
5872 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5873 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5874
5875 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5876 "Relogin scheduled.\n");
5877 qla2x00_relogin(base_vha);
5878 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5879 "Relogin end.\n");
5880 }
5881 loop_resync_check:
5882 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5883 &base_vha->dpc_flags)) {
5884
5885 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5886 "Loop resync scheduled.\n");
5887
5888 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5889 &base_vha->dpc_flags))) {
5890
5891 qla2x00_loop_resync(base_vha);
5892
5893 clear_bit(LOOP_RESYNC_ACTIVE,
5894 &base_vha->dpc_flags);
5895 }
5896
5897 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5898 "Loop resync end.\n");
5899 }
5900
5901 if (IS_QLAFX00(ha))
5902 goto intr_on_check;
5903
5904 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5905 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5906 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5907 qla2xxx_flash_npiv_conf(base_vha);
5908 }
5909
5910 intr_on_check:
5911 if (!ha->interrupts_on)
5912 ha->isp_ops->enable_intrs(ha);
5913
5914 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5915 &base_vha->dpc_flags)) {
5916 if (ha->beacon_blink_led == 1)
5917 ha->isp_ops->beacon_blink(base_vha);
5918 }
5919
5920 /* qpair online check */
5921 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5922 &base_vha->dpc_flags)) {
5923 if (ha->flags.eeh_busy ||
5924 ha->flags.pci_channel_io_perm_failure)
5925 online = 0;
5926 else
5927 online = 1;
5928
5929 mutex_lock(&ha->mq_lock);
5930 list_for_each_entry(qpair, &base_vha->qp_list,
5931 qp_list_elem)
5932 qpair->online = online;
5933 mutex_unlock(&ha->mq_lock);
5934 }
5935
5936 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
5937 ql_log(ql_log_info, base_vha, 0xffffff,
5938 "nvme: SET ZIO Activity exchange threshold to %d.\n",
5939 ha->nvme_last_rptd_aen);
5940 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
5941 ql_log(ql_log_info, base_vha, 0xffffff,
5942 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
5943 ha->nvme_last_rptd_aen);
5944 }
5945 }
5946
5947 if (!IS_QLAFX00(ha))
5948 qla2x00_do_dpc_all_vps(base_vha);
5949
5950 ha->dpc_active = 0;
5951 end_loop:
5952 set_current_state(TASK_INTERRUPTIBLE);
5953 } /* End of while(1) */
5954 __set_current_state(TASK_RUNNING);
5955
5956 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5957 "DPC handler exiting.\n");
5958
5959 /*
5960 * Make sure that nobody tries to wake us up again.
5961 */
5962 ha->dpc_active = 0;
5963
5964 /* Cleanup any residual CTX SRBs. */
5965 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5966
5967 return 0;
5968 }
5969
5970 void
5971 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5972 {
5973 struct qla_hw_data *ha = vha->hw;
5974 struct task_struct *t = ha->dpc_thread;
5975
5976 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5977 wake_up_process(t);
5978 }
5979
5980 /*
5981 * qla2x00_rst_aen
5982 * Processes asynchronous reset.
5983 *
5984 * Input:
5985 * ha = adapter block pointer.
5986 */
5987 static void
5988 qla2x00_rst_aen(scsi_qla_host_t *vha)
5989 {
5990 if (vha->flags.online && !vha->flags.reset_active &&
5991 !atomic_read(&vha->loop_down_timer) &&
5992 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5993 do {
5994 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5995
5996 /*
5997 * Issue marker command only when we are going to start
5998 * the I/O.
5999 */
6000 vha->marker_needed = 1;
6001 } while (!atomic_read(&vha->loop_down_timer) &&
6002 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
6003 }
6004 }
6005
6006 /**************************************************************************
6007 * qla2x00_timer
6008 *
6009 * Description:
6010 * One second timer
6011 *
6012 * Context: Interrupt
6013 ***************************************************************************/
6014 void
6015 qla2x00_timer(struct timer_list *t)
6016 {
6017 scsi_qla_host_t *vha = from_timer(vha, t, timer);
6018 unsigned long cpu_flags = 0;
6019 int start_dpc = 0;
6020 int index;
6021 srb_t *sp;
6022 uint16_t w;
6023 struct qla_hw_data *ha = vha->hw;
6024 struct req_que *req;
6025
6026 if (ha->flags.eeh_busy) {
6027 ql_dbg(ql_dbg_timer, vha, 0x6000,
6028 "EEH = %d, restarting timer.\n",
6029 ha->flags.eeh_busy);
6030 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6031 return;
6032 }
6033
6034 /*
6035 * Hardware read to raise pending EEH errors during mailbox waits. If
6036 * the read returns -1 then disable the board.
6037 */
6038 if (!pci_channel_offline(ha->pdev)) {
6039 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
6040 qla2x00_check_reg16_for_disconnect(vha, w);
6041 }
6042
6043 /* Make sure qla82xx_watchdog is run only for physical port */
6044 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
6045 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6046 start_dpc++;
6047 if (IS_QLA82XX(ha))
6048 qla82xx_watchdog(vha);
6049 else if (IS_QLA8044(ha))
6050 qla8044_watchdog(vha);
6051 }
6052
6053 if (!vha->vp_idx && IS_QLAFX00(ha))
6054 qlafx00_timer_routine(vha);
6055
6056 /* Loop down handler. */
6057 if (atomic_read(&vha->loop_down_timer) > 0 &&
6058 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6059 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
6060 && vha->flags.online) {
6061
6062 if (atomic_read(&vha->loop_down_timer) ==
6063 vha->loop_down_abort_time) {
6064
6065 ql_log(ql_log_info, vha, 0x6008,
6066 "Loop down - aborting the queues before time expires.\n");
6067
6068 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6069 atomic_set(&vha->loop_state, LOOP_DEAD);
6070
6071 /*
6072 * Schedule an ISP abort to return any FCP2-device
6073 * commands.
6074 */
6075 /* NPIV - scan physical port only */
6076 if (!vha->vp_idx) {
6077 spin_lock_irqsave(&ha->hardware_lock,
6078 cpu_flags);
6079 req = ha->req_q_map[0];
6080 for (index = 1;
6081 index < req->num_outstanding_cmds;
6082 index++) {
6083 fc_port_t *sfcp;
6084
6085 sp = req->outstanding_cmds[index];
6086 if (!sp)
6087 continue;
6088 if (sp->cmd_type != TYPE_SRB)
6089 continue;
6090 if (sp->type != SRB_SCSI_CMD)
6091 continue;
6092 sfcp = sp->fcport;
6093 if (!(sfcp->flags & FCF_FCP2_DEVICE))
6094 continue;
6095
6096 if (IS_QLA82XX(ha))
6097 set_bit(FCOE_CTX_RESET_NEEDED,
6098 &vha->dpc_flags);
6099 else
6100 set_bit(ISP_ABORT_NEEDED,
6101 &vha->dpc_flags);
6102 break;
6103 }
6104 spin_unlock_irqrestore(&ha->hardware_lock,
6105 cpu_flags);
6106 }
6107 start_dpc++;
6108 }
6109
6110 /* if the loop has been down for 4 minutes, reinit adapter */
6111 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
6112 if (!(vha->device_flags & DFLG_NO_CABLE)) {
6113 ql_log(ql_log_warn, vha, 0x6009,
6114 "Loop down - aborting ISP.\n");
6115
6116 if (IS_QLA82XX(ha))
6117 set_bit(FCOE_CTX_RESET_NEEDED,
6118 &vha->dpc_flags);
6119 else
6120 set_bit(ISP_ABORT_NEEDED,
6121 &vha->dpc_flags);
6122 }
6123 }
6124 ql_dbg(ql_dbg_timer, vha, 0x600a,
6125 "Loop down - seconds remaining %d.\n",
6126 atomic_read(&vha->loop_down_timer));
6127 }
6128 /* Check if beacon LED needs to be blinked for physical host only */
6129 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
6130 /* There is no beacon_blink function for ISP82xx */
6131 if (!IS_P3P_TYPE(ha)) {
6132 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6133 start_dpc++;
6134 }
6135 }
6136
6137 /* Process any deferred work. */
6138 if (!list_empty(&vha->work_list))
6139 start_dpc++;
6140
6141 /*
6142 * FC-NVME
6143 * see if the active AEN count has changed from what was last reported.
6144 */
6145 if (!vha->vp_idx &&
6146 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6147 ha->zio_mode == QLA_ZIO_MODE_6) {
6148 ql_log(ql_log_info, vha, 0x3002,
6149 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6150 ha->nvme_last_rptd_aen);
6151 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6152 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6153 start_dpc++;
6154 }
6155
6156 /* Schedule the DPC routine if needed */
6157 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6158 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6159 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
6160 start_dpc ||
6161 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6162 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
6163 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6164 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
6165 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
6166 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
6167 ql_dbg(ql_dbg_timer, vha, 0x600b,
6168 "isp_abort_needed=%d loop_resync_needed=%d "
6169 "fcport_update_needed=%d start_dpc=%d "
6170 "reset_marker_needed=%d",
6171 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6172 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6173 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6174 start_dpc,
6175 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6176 ql_dbg(ql_dbg_timer, vha, 0x600c,
6177 "beacon_blink_needed=%d isp_unrecoverable=%d "
6178 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
6179 "relogin_needed=%d.\n",
6180 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6181 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6182 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6183 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
6184 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
6185 qla2xxx_wake_dpc(vha);
6186 }
6187
6188 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6189 }
6190
6191 /* Firmware interface routines. */
6192
6193 #define FW_BLOBS 11
6194 #define FW_ISP21XX 0
6195 #define FW_ISP22XX 1
6196 #define FW_ISP2300 2
6197 #define FW_ISP2322 3
6198 #define FW_ISP24XX 4
6199 #define FW_ISP25XX 5
6200 #define FW_ISP81XX 6
6201 #define FW_ISP82XX 7
6202 #define FW_ISP2031 8
6203 #define FW_ISP8031 9
6204 #define FW_ISP27XX 10
6205
6206 #define FW_FILE_ISP21XX "ql2100_fw.bin"
6207 #define FW_FILE_ISP22XX "ql2200_fw.bin"
6208 #define FW_FILE_ISP2300 "ql2300_fw.bin"
6209 #define FW_FILE_ISP2322 "ql2322_fw.bin"
6210 #define FW_FILE_ISP24XX "ql2400_fw.bin"
6211 #define FW_FILE_ISP25XX "ql2500_fw.bin"
6212 #define FW_FILE_ISP81XX "ql8100_fw.bin"
6213 #define FW_FILE_ISP82XX "ql8200_fw.bin"
6214 #define FW_FILE_ISP2031 "ql2600_fw.bin"
6215 #define FW_FILE_ISP8031 "ql8300_fw.bin"
6216 #define FW_FILE_ISP27XX "ql2700_fw.bin"
6217
6218
6219 static DEFINE_MUTEX(qla_fw_lock);
6220
6221 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
6222 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6223 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6224 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6225 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6226 { .name = FW_FILE_ISP24XX, },
6227 { .name = FW_FILE_ISP25XX, },
6228 { .name = FW_FILE_ISP81XX, },
6229 { .name = FW_FILE_ISP82XX, },
6230 { .name = FW_FILE_ISP2031, },
6231 { .name = FW_FILE_ISP8031, },
6232 { .name = FW_FILE_ISP27XX, },
6233 };
6234
6235 struct fw_blob *
6236 qla2x00_request_firmware(scsi_qla_host_t *vha)
6237 {
6238 struct qla_hw_data *ha = vha->hw;
6239 struct fw_blob *blob;
6240
6241 if (IS_QLA2100(ha)) {
6242 blob = &qla_fw_blobs[FW_ISP21XX];
6243 } else if (IS_QLA2200(ha)) {
6244 blob = &qla_fw_blobs[FW_ISP22XX];
6245 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
6246 blob = &qla_fw_blobs[FW_ISP2300];
6247 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
6248 blob = &qla_fw_blobs[FW_ISP2322];
6249 } else if (IS_QLA24XX_TYPE(ha)) {
6250 blob = &qla_fw_blobs[FW_ISP24XX];
6251 } else if (IS_QLA25XX(ha)) {
6252 blob = &qla_fw_blobs[FW_ISP25XX];
6253 } else if (IS_QLA81XX(ha)) {
6254 blob = &qla_fw_blobs[FW_ISP81XX];
6255 } else if (IS_QLA82XX(ha)) {
6256 blob = &qla_fw_blobs[FW_ISP82XX];
6257 } else if (IS_QLA2031(ha)) {
6258 blob = &qla_fw_blobs[FW_ISP2031];
6259 } else if (IS_QLA8031(ha)) {
6260 blob = &qla_fw_blobs[FW_ISP8031];
6261 } else if (IS_QLA27XX(ha)) {
6262 blob = &qla_fw_blobs[FW_ISP27XX];
6263 } else {
6264 return NULL;
6265 }
6266
6267 mutex_lock(&qla_fw_lock);
6268 if (blob->fw)
6269 goto out;
6270
6271 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
6272 ql_log(ql_log_warn, vha, 0x0063,
6273 "Failed to load firmware image (%s).\n", blob->name);
6274 blob->fw = NULL;
6275 blob = NULL;
6276 goto out;
6277 }
6278
6279 out:
6280 mutex_unlock(&qla_fw_lock);
6281 return blob;
6282 }
6283
6284 static void
6285 qla2x00_release_firmware(void)
6286 {
6287 int idx;
6288
6289 mutex_lock(&qla_fw_lock);
6290 for (idx = 0; idx < FW_BLOBS; idx++)
6291 release_firmware(qla_fw_blobs[idx].fw);
6292 mutex_unlock(&qla_fw_lock);
6293 }
6294
6295 static pci_ers_result_t
6296 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6297 {
6298 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6299 struct qla_hw_data *ha = vha->hw;
6300
6301 ql_dbg(ql_dbg_aer, vha, 0x9000,
6302 "PCI error detected, state %x.\n", state);
6303
6304 if (!atomic_read(&pdev->enable_cnt)) {
6305 ql_log(ql_log_info, vha, 0xffff,
6306 "PCI device is disabled,state %x\n", state);
6307 return PCI_ERS_RESULT_NEED_RESET;
6308 }
6309
6310 switch (state) {
6311 case pci_channel_io_normal:
6312 ha->flags.eeh_busy = 0;
6313 if (ql2xmqsupport || ql2xnvmeenable) {
6314 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6315 qla2xxx_wake_dpc(vha);
6316 }
6317 return PCI_ERS_RESULT_CAN_RECOVER;
6318 case pci_channel_io_frozen:
6319 ha->flags.eeh_busy = 1;
6320 /* For ISP82XX complete any pending mailbox cmd */
6321 if (IS_QLA82XX(ha)) {
6322 ha->flags.isp82xx_fw_hung = 1;
6323 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6324 qla82xx_clear_pending_mbx(vha);
6325 }
6326 qla2x00_free_irqs(vha);
6327 pci_disable_device(pdev);
6328 /* Return back all IOs */
6329 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6330 if (ql2xmqsupport || ql2xnvmeenable) {
6331 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6332 qla2xxx_wake_dpc(vha);
6333 }
6334 return PCI_ERS_RESULT_NEED_RESET;
6335 case pci_channel_io_perm_failure:
6336 ha->flags.pci_channel_io_perm_failure = 1;
6337 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
6338 if (ql2xmqsupport || ql2xnvmeenable) {
6339 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6340 qla2xxx_wake_dpc(vha);
6341 }
6342 return PCI_ERS_RESULT_DISCONNECT;
6343 }
6344 return PCI_ERS_RESULT_NEED_RESET;
6345 }
6346
6347 static pci_ers_result_t
6348 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6349 {
6350 int risc_paused = 0;
6351 uint32_t stat;
6352 unsigned long flags;
6353 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6354 struct qla_hw_data *ha = base_vha->hw;
6355 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6356 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6357
6358 if (IS_QLA82XX(ha))
6359 return PCI_ERS_RESULT_RECOVERED;
6360
6361 spin_lock_irqsave(&ha->hardware_lock, flags);
6362 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6363 stat = RD_REG_DWORD(&reg->hccr);
6364 if (stat & HCCR_RISC_PAUSE)
6365 risc_paused = 1;
6366 } else if (IS_QLA23XX(ha)) {
6367 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6368 if (stat & HSR_RISC_PAUSED)
6369 risc_paused = 1;
6370 } else if (IS_FWI2_CAPABLE(ha)) {
6371 stat = RD_REG_DWORD(&reg24->host_status);
6372 if (stat & HSRX_RISC_PAUSED)
6373 risc_paused = 1;
6374 }
6375 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6376
6377 if (risc_paused) {
6378 ql_log(ql_log_info, base_vha, 0x9003,
6379 "RISC paused -- mmio_enabled, Dumping firmware.\n");
6380 ha->isp_ops->fw_dump(base_vha, 0);
6381
6382 return PCI_ERS_RESULT_NEED_RESET;
6383 } else
6384 return PCI_ERS_RESULT_RECOVERED;
6385 }
6386
6387 static uint32_t
6388 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
6389 {
6390 uint32_t rval = QLA_FUNCTION_FAILED;
6391 uint32_t drv_active = 0;
6392 struct qla_hw_data *ha = base_vha->hw;
6393 int fn;
6394 struct pci_dev *other_pdev = NULL;
6395
6396 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6397 "Entered %s.\n", __func__);
6398
6399 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6400
6401 if (base_vha->flags.online) {
6402 /* Abort all outstanding commands,
6403 * so as to be requeued later */
6404 qla2x00_abort_isp_cleanup(base_vha);
6405 }
6406
6407
6408 fn = PCI_FUNC(ha->pdev->devfn);
6409 while (fn > 0) {
6410 fn--;
6411 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6412 "Finding pci device at function = 0x%x.\n", fn);
6413 other_pdev =
6414 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6415 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6416 fn));
6417
6418 if (!other_pdev)
6419 continue;
6420 if (atomic_read(&other_pdev->enable_cnt)) {
6421 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6422 "Found PCI func available and enable at 0x%x.\n",
6423 fn);
6424 pci_dev_put(other_pdev);
6425 break;
6426 }
6427 pci_dev_put(other_pdev);
6428 }
6429
6430 if (!fn) {
6431 /* Reset owner */
6432 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6433 "This devfn is reset owner = 0x%x.\n",
6434 ha->pdev->devfn);
6435 qla82xx_idc_lock(ha);
6436
6437 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6438 QLA8XXX_DEV_INITIALIZING);
6439
6440 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6441 QLA82XX_IDC_VERSION);
6442
6443 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
6444 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6445 "drv_active = 0x%x.\n", drv_active);
6446
6447 qla82xx_idc_unlock(ha);
6448 /* Reset if device is not already reset
6449 * drv_active would be 0 if a reset has already been done
6450 */
6451 if (drv_active)
6452 rval = qla82xx_start_firmware(base_vha);
6453 else
6454 rval = QLA_SUCCESS;
6455 qla82xx_idc_lock(ha);
6456
6457 if (rval != QLA_SUCCESS) {
6458 ql_log(ql_log_info, base_vha, 0x900b,
6459 "HW State: FAILED.\n");
6460 qla82xx_clear_drv_active(ha);
6461 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6462 QLA8XXX_DEV_FAILED);
6463 } else {
6464 ql_log(ql_log_info, base_vha, 0x900c,
6465 "HW State: READY.\n");
6466 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6467 QLA8XXX_DEV_READY);
6468 qla82xx_idc_unlock(ha);
6469 ha->flags.isp82xx_fw_hung = 0;
6470 rval = qla82xx_restart_isp(base_vha);
6471 qla82xx_idc_lock(ha);
6472 /* Clear driver state register */
6473 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6474 qla82xx_set_drv_active(base_vha);
6475 }
6476 qla82xx_idc_unlock(ha);
6477 } else {
6478 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6479 "This devfn is not reset owner = 0x%x.\n",
6480 ha->pdev->devfn);
6481 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
6482 QLA8XXX_DEV_READY)) {
6483 ha->flags.isp82xx_fw_hung = 0;
6484 rval = qla82xx_restart_isp(base_vha);
6485 qla82xx_idc_lock(ha);
6486 qla82xx_set_drv_active(base_vha);
6487 qla82xx_idc_unlock(ha);
6488 }
6489 }
6490 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6491
6492 return rval;
6493 }
6494
6495 static pci_ers_result_t
6496 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6497 {
6498 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
6499 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6500 struct qla_hw_data *ha = base_vha->hw;
6501 struct rsp_que *rsp;
6502 int rc, retries = 10;
6503
6504 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6505 "Slot Reset.\n");
6506
6507 /* Workaround: qla2xxx driver which access hardware earlier
6508 * needs error state to be pci_channel_io_online.
6509 * Otherwise mailbox command timesout.
6510 */
6511 pdev->error_state = pci_channel_io_normal;
6512
6513 pci_restore_state(pdev);
6514
6515 /* pci_restore_state() clears the saved_state flag of the device
6516 * save restored state which resets saved_state flag
6517 */
6518 pci_save_state(pdev);
6519
6520 if (ha->mem_only)
6521 rc = pci_enable_device_mem(pdev);
6522 else
6523 rc = pci_enable_device(pdev);
6524
6525 if (rc) {
6526 ql_log(ql_log_warn, base_vha, 0x9005,
6527 "Can't re-enable PCI device after reset.\n");
6528 goto exit_slot_reset;
6529 }
6530
6531 rsp = ha->rsp_q_map[0];
6532 if (qla2x00_request_irqs(ha, rsp))
6533 goto exit_slot_reset;
6534
6535 if (ha->isp_ops->pci_config(base_vha))
6536 goto exit_slot_reset;
6537
6538 if (IS_QLA82XX(ha)) {
6539 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6540 ret = PCI_ERS_RESULT_RECOVERED;
6541 goto exit_slot_reset;
6542 } else
6543 goto exit_slot_reset;
6544 }
6545
6546 while (ha->flags.mbox_busy && retries--)
6547 msleep(1000);
6548
6549 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6550 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
6551 ret = PCI_ERS_RESULT_RECOVERED;
6552 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6553
6554
6555 exit_slot_reset:
6556 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6557 "slot_reset return %x.\n", ret);
6558
6559 return ret;
6560 }
6561
6562 static void
6563 qla2xxx_pci_resume(struct pci_dev *pdev)
6564 {
6565 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6566 struct qla_hw_data *ha = base_vha->hw;
6567 int ret;
6568
6569 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6570 "pci_resume.\n");
6571
6572 ret = qla2x00_wait_for_hba_online(base_vha);
6573 if (ret != QLA_SUCCESS) {
6574 ql_log(ql_log_fatal, base_vha, 0x9002,
6575 "The device failed to resume I/O from slot/link_reset.\n");
6576 }
6577
6578 pci_cleanup_aer_uncorrect_error_status(pdev);
6579
6580 ha->flags.eeh_busy = 0;
6581 }
6582
6583 static void
6584 qla83xx_disable_laser(scsi_qla_host_t *vha)
6585 {
6586 uint32_t reg, data, fn;
6587 struct qla_hw_data *ha = vha->hw;
6588 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6589
6590 /* pci func #/port # */
6591 ql_dbg(ql_dbg_init, vha, 0x004b,
6592 "Disabling Laser for hba: %p\n", vha);
6593
6594 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6595 (BIT_15|BIT_14|BIT_13|BIT_12));
6596
6597 fn = (fn >> 12);
6598
6599 if (fn & 1)
6600 reg = PORT_1_2031;
6601 else
6602 reg = PORT_0_2031;
6603
6604 data = LASER_OFF_2031;
6605
6606 qla83xx_wr_reg(vha, reg, data);
6607 }
6608
6609 static int qla2xxx_map_queues(struct Scsi_Host *shost)
6610 {
6611 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6612
6613 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6614 }
6615
6616 static const struct pci_error_handlers qla2xxx_err_handler = {
6617 .error_detected = qla2xxx_pci_error_detected,
6618 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6619 .slot_reset = qla2xxx_pci_slot_reset,
6620 .resume = qla2xxx_pci_resume,
6621 };
6622
6623 static struct pci_device_id qla2xxx_pci_tbl[] = {
6624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6629 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
6633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
6634 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6635 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
6636 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6637 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
6638 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
6639 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
6640 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
6641 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
6642 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
6643 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
6644 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
6645 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
6646 { 0 },
6647 };
6648 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6649
6650 static struct pci_driver qla2xxx_pci_driver = {
6651 .name = QLA2XXX_DRIVER_NAME,
6652 .driver = {
6653 .owner = THIS_MODULE,
6654 },
6655 .id_table = qla2xxx_pci_tbl,
6656 .probe = qla2x00_probe_one,
6657 .remove = qla2x00_remove_one,
6658 .shutdown = qla2x00_shutdown,
6659 .err_handler = &qla2xxx_err_handler,
6660 };
6661
6662 static const struct file_operations apidev_fops = {
6663 .owner = THIS_MODULE,
6664 .llseek = noop_llseek,
6665 };
6666
6667 /**
6668 * qla2x00_module_init - Module initialization.
6669 **/
6670 static int __init
6671 qla2x00_module_init(void)
6672 {
6673 int ret = 0;
6674
6675 /* Allocate cache for SRBs. */
6676 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
6677 SLAB_HWCACHE_ALIGN, NULL);
6678 if (srb_cachep == NULL) {
6679 ql_log(ql_log_fatal, NULL, 0x0001,
6680 "Unable to allocate SRB cache...Failing load!.\n");
6681 return -ENOMEM;
6682 }
6683
6684 /* Initialize target kmem_cache and mem_pools */
6685 ret = qlt_init();
6686 if (ret < 0) {
6687 kmem_cache_destroy(srb_cachep);
6688 return ret;
6689 } else if (ret > 0) {
6690 /*
6691 * If initiator mode is explictly disabled by qlt_init(),
6692 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6693 * performing scsi_scan_target() during LOOP UP event.
6694 */
6695 qla2xxx_transport_functions.disable_target_scan = 1;
6696 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6697 }
6698
6699 /* Derive version string. */
6700 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
6701 if (ql2xextended_error_logging)
6702 strcat(qla2x00_version_str, "-debug");
6703 if (ql2xextended_error_logging == 1)
6704 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
6705
6706 qla2xxx_transport_template =
6707 fc_attach_transport(&qla2xxx_transport_functions);
6708 if (!qla2xxx_transport_template) {
6709 kmem_cache_destroy(srb_cachep);
6710 ql_log(ql_log_fatal, NULL, 0x0002,
6711 "fc_attach_transport failed...Failing load!.\n");
6712 qlt_exit();
6713 return -ENODEV;
6714 }
6715
6716 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6717 if (apidev_major < 0) {
6718 ql_log(ql_log_fatal, NULL, 0x0003,
6719 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6720 }
6721
6722 qla2xxx_transport_vport_template =
6723 fc_attach_transport(&qla2xxx_transport_vport_functions);
6724 if (!qla2xxx_transport_vport_template) {
6725 kmem_cache_destroy(srb_cachep);
6726 qlt_exit();
6727 fc_release_transport(qla2xxx_transport_template);
6728 ql_log(ql_log_fatal, NULL, 0x0004,
6729 "fc_attach_transport vport failed...Failing load!.\n");
6730 return -ENODEV;
6731 }
6732 ql_log(ql_log_info, NULL, 0x0005,
6733 "QLogic Fibre Channel HBA Driver: %s.\n",
6734 qla2x00_version_str);
6735 ret = pci_register_driver(&qla2xxx_pci_driver);
6736 if (ret) {
6737 kmem_cache_destroy(srb_cachep);
6738 qlt_exit();
6739 fc_release_transport(qla2xxx_transport_template);
6740 fc_release_transport(qla2xxx_transport_vport_template);
6741 ql_log(ql_log_fatal, NULL, 0x0006,
6742 "pci_register_driver failed...ret=%d Failing load!.\n",
6743 ret);
6744 }
6745 return ret;
6746 }
6747
6748 /**
6749 * qla2x00_module_exit - Module cleanup.
6750 **/
6751 static void __exit
6752 qla2x00_module_exit(void)
6753 {
6754 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
6755 pci_unregister_driver(&qla2xxx_pci_driver);
6756 qla2x00_release_firmware();
6757 kmem_cache_destroy(srb_cachep);
6758 qlt_exit();
6759 if (ctx_cachep)
6760 kmem_cache_destroy(ctx_cachep);
6761 fc_release_transport(qla2xxx_transport_template);
6762 fc_release_transport(qla2xxx_transport_vport_template);
6763 }
6764
6765 module_init(qla2x00_module_init);
6766 module_exit(qla2x00_module_exit);
6767
6768 MODULE_AUTHOR("QLogic Corporation");
6769 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6770 MODULE_LICENSE("GPL");
6771 MODULE_VERSION(QLA2XXX_VERSION);
6772 MODULE_FIRMWARE(FW_FILE_ISP21XX);
6773 MODULE_FIRMWARE(FW_FILE_ISP22XX);
6774 MODULE_FIRMWARE(FW_FILE_ISP2300);
6775 MODULE_FIRMWARE(FW_FILE_ISP2322);
6776 MODULE_FIRMWARE(FW_FILE_ISP24XX);
6777 MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux with added FPC-III support