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mei: me: add cannon point device ids
[linux/fpc-iii.git] / drivers / spi / spi-s3c64xx.c
blobde7df20f8712dd74dc074e763555891f076b820f
1 /*
2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/clk.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dmaengine.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/spi/spi.h>
26 #include <linux/gpio.h>
27 #include <linux/of.h>
28 #include <linux/of_gpio.h>
29
30 #include <linux/platform_data/spi-s3c64xx.h>
31
32 #define MAX_SPI_PORTS 6
33 #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
34 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
35 #define AUTOSUSPEND_TIMEOUT 2000
36
37 /* Registers and bit-fields */
38
39 #define S3C64XX_SPI_CH_CFG 0x00
40 #define S3C64XX_SPI_CLK_CFG 0x04
41 #define S3C64XX_SPI_MODE_CFG 0x08
42 #define S3C64XX_SPI_SLAVE_SEL 0x0C
43 #define S3C64XX_SPI_INT_EN 0x10
44 #define S3C64XX_SPI_STATUS 0x14
45 #define S3C64XX_SPI_TX_DATA 0x18
46 #define S3C64XX_SPI_RX_DATA 0x1C
47 #define S3C64XX_SPI_PACKET_CNT 0x20
48 #define S3C64XX_SPI_PENDING_CLR 0x24
49 #define S3C64XX_SPI_SWAP_CFG 0x28
50 #define S3C64XX_SPI_FB_CLK 0x2C
51
52 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
53 #define S3C64XX_SPI_CH_SW_RST (1<<5)
54 #define S3C64XX_SPI_CH_SLAVE (1<<4)
55 #define S3C64XX_SPI_CPOL_L (1<<3)
56 #define S3C64XX_SPI_CPHA_B (1<<2)
57 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
58 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
59
60 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
61 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
62 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
63 #define S3C64XX_SPI_PSR_MASK 0xff
64
65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
73 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
74 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
75 #define S3C64XX_SPI_MODE_4BURST (1<<0)
76
77 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
78 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4)
80
81 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
88
89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
95
96 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
97
98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
103
104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
112
113 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
114
115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
117 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
120 FIFO_LVL_MASK(i))
121
122 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
123 #define S3C64XX_SPI_TRAILCNT_OFF 19
124
125 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
126
127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
129
130 #define RXBUSY (1<<2)
131 #define TXBUSY (1<<3)
132
133 struct s3c64xx_spi_dma_data {
134 struct dma_chan *ch;
135 enum dma_transfer_direction direction;
136 };
137
138 /**
139 * struct s3c64xx_spi_info - SPI Controller hardware info
140 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
141 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
142 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
143 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
144 * @clk_from_cmu: True, if the controller does not include a clock mux and
145 * prescaler unit.
146 *
147 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
148 * differ in some aspects such as the size of the fifo and spi bus clock
149 * setup. Such differences are specified to the driver using this structure
150 * which is provided as driver data to the driver.
151 */
152 struct s3c64xx_spi_port_config {
153 int fifo_lvl_mask[MAX_SPI_PORTS];
154 int rx_lvl_offset;
155 int tx_st_done;
156 int quirks;
157 bool high_speed;
158 bool clk_from_cmu;
159 bool clk_ioclk;
160 };
161
162 /**
163 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164 * @clk: Pointer to the spi clock.
165 * @src_clk: Pointer to the clock used to generate SPI signals.
166 * @ioclk: Pointer to the i/o clock between master and slave
167 * @master: Pointer to the SPI Protocol master.
168 * @cntrlr_info: Platform specific data for the controller this driver manages.
169 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
170 * @lock: Controller specific lock.
171 * @state: Set of FLAGS to indicate status.
172 * @rx_dmach: Controller's DMA channel for Rx.
173 * @tx_dmach: Controller's DMA channel for Tx.
174 * @sfr_start: BUS address of SPI controller regs.
175 * @regs: Pointer to ioremap'ed controller registers.
176 * @irq: interrupt
177 * @xfer_completion: To indicate completion of xfer task.
178 * @cur_mode: Stores the active configuration of the controller.
179 * @cur_bpw: Stores the active bits per word settings.
180 * @cur_speed: Stores the active xfer clock speed.
181 */
182 struct s3c64xx_spi_driver_data {
183 void __iomem *regs;
184 struct clk *clk;
185 struct clk *src_clk;
186 struct clk *ioclk;
187 struct platform_device *pdev;
188 struct spi_master *master;
189 struct s3c64xx_spi_info *cntrlr_info;
190 struct spi_device *tgl_spi;
191 spinlock_t lock;
192 unsigned long sfr_start;
193 struct completion xfer_completion;
194 unsigned state;
195 unsigned cur_mode, cur_bpw;
196 unsigned cur_speed;
197 struct s3c64xx_spi_dma_data rx_dma;
198 struct s3c64xx_spi_dma_data tx_dma;
199 struct s3c64xx_spi_port_config *port_conf;
200 unsigned int port_id;
201 };
202
203 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
204 {
205 void __iomem *regs = sdd->regs;
206 unsigned long loops;
207 u32 val;
208
209 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
210
211 val = readl(regs + S3C64XX_SPI_CH_CFG);
212 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
213 writel(val, regs + S3C64XX_SPI_CH_CFG);
214
215 val = readl(regs + S3C64XX_SPI_CH_CFG);
216 val |= S3C64XX_SPI_CH_SW_RST;
217 val &= ~S3C64XX_SPI_CH_HS_EN;
218 writel(val, regs + S3C64XX_SPI_CH_CFG);
219
220 /* Flush TxFIFO*/
221 loops = msecs_to_loops(1);
222 do {
223 val = readl(regs + S3C64XX_SPI_STATUS);
224 } while (TX_FIFO_LVL(val, sdd) && loops--);
225
226 if (loops == 0)
227 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
228
229 /* Flush RxFIFO*/
230 loops = msecs_to_loops(1);
231 do {
232 val = readl(regs + S3C64XX_SPI_STATUS);
233 if (RX_FIFO_LVL(val, sdd))
234 readl(regs + S3C64XX_SPI_RX_DATA);
235 else
236 break;
237 } while (loops--);
238
239 if (loops == 0)
240 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
241
242 val = readl(regs + S3C64XX_SPI_CH_CFG);
243 val &= ~S3C64XX_SPI_CH_SW_RST;
244 writel(val, regs + S3C64XX_SPI_CH_CFG);
245
246 val = readl(regs + S3C64XX_SPI_MODE_CFG);
247 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
248 writel(val, regs + S3C64XX_SPI_MODE_CFG);
249 }
250
251 static void s3c64xx_spi_dmacb(void *data)
252 {
253 struct s3c64xx_spi_driver_data *sdd;
254 struct s3c64xx_spi_dma_data *dma = data;
255 unsigned long flags;
256
257 if (dma->direction == DMA_DEV_TO_MEM)
258 sdd = container_of(data,
259 struct s3c64xx_spi_driver_data, rx_dma);
260 else
261 sdd = container_of(data,
262 struct s3c64xx_spi_driver_data, tx_dma);
263
264 spin_lock_irqsave(&sdd->lock, flags);
265
266 if (dma->direction == DMA_DEV_TO_MEM) {
267 sdd->state &= ~RXBUSY;
268 if (!(sdd->state & TXBUSY))
269 complete(&sdd->xfer_completion);
270 } else {
271 sdd->state &= ~TXBUSY;
272 if (!(sdd->state & RXBUSY))
273 complete(&sdd->xfer_completion);
274 }
275
276 spin_unlock_irqrestore(&sdd->lock, flags);
277 }
278
279 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
280 struct sg_table *sgt)
281 {
282 struct s3c64xx_spi_driver_data *sdd;
283 struct dma_slave_config config;
284 struct dma_async_tx_descriptor *desc;
285
286 memset(&config, 0, sizeof(config));
287
288 if (dma->direction == DMA_DEV_TO_MEM) {
289 sdd = container_of((void *)dma,
290 struct s3c64xx_spi_driver_data, rx_dma);
291 config.direction = dma->direction;
292 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
293 config.src_addr_width = sdd->cur_bpw / 8;
294 config.src_maxburst = 1;
295 dmaengine_slave_config(dma->ch, &config);
296 } else {
297 sdd = container_of((void *)dma,
298 struct s3c64xx_spi_driver_data, tx_dma);
299 config.direction = dma->direction;
300 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
301 config.dst_addr_width = sdd->cur_bpw / 8;
302 config.dst_maxburst = 1;
303 dmaengine_slave_config(dma->ch, &config);
304 }
305
306 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
307 dma->direction, DMA_PREP_INTERRUPT);
308
309 desc->callback = s3c64xx_spi_dmacb;
310 desc->callback_param = dma;
311
312 dmaengine_submit(desc);
313 dma_async_issue_pending(dma->ch);
314 }
315
316 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
317 {
318 struct s3c64xx_spi_driver_data *sdd =
319 spi_master_get_devdata(spi->master);
320
321 if (sdd->cntrlr_info->no_cs)
322 return;
323
324 if (enable) {
325 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
326 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
327 } else {
328 u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
329
330 ssel |= (S3C64XX_SPI_SLAVE_AUTO |
331 S3C64XX_SPI_SLAVE_NSC_CNT_2);
332 writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
333 }
334 } else {
335 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
336 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
337 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
338 }
339 }
340
341 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
342 {
343 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
344
345 if (is_polling(sdd))
346 return 0;
347
348 spi->dma_rx = sdd->rx_dma.ch;
349 spi->dma_tx = sdd->tx_dma.ch;
350
351 return 0;
352 }
353
354 static bool s3c64xx_spi_can_dma(struct spi_master *master,
355 struct spi_device *spi,
356 struct spi_transfer *xfer)
357 {
358 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
359
360 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
361 }
362
363 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
364 struct spi_device *spi,
365 struct spi_transfer *xfer, int dma_mode)
366 {
367 void __iomem *regs = sdd->regs;
368 u32 modecfg, chcfg;
369
370 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
371 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
372
373 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
374 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
375
376 if (dma_mode) {
377 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
378 } else {
379 /* Always shift in data in FIFO, even if xfer is Tx only,
380 * this helps setting PCKT_CNT value for generating clocks
381 * as exactly needed.
382 */
383 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
384 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
385 | S3C64XX_SPI_PACKET_CNT_EN,
386 regs + S3C64XX_SPI_PACKET_CNT);
387 }
388
389 if (xfer->tx_buf != NULL) {
390 sdd->state |= TXBUSY;
391 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
392 if (dma_mode) {
393 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
394 prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
395 } else {
396 switch (sdd->cur_bpw) {
397 case 32:
398 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
399 xfer->tx_buf, xfer->len / 4);
400 break;
401 case 16:
402 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
403 xfer->tx_buf, xfer->len / 2);
404 break;
405 default:
406 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
407 xfer->tx_buf, xfer->len);
408 break;
409 }
410 }
411 }
412
413 if (xfer->rx_buf != NULL) {
414 sdd->state |= RXBUSY;
415
416 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
417 && !(sdd->cur_mode & SPI_CPHA))
418 chcfg |= S3C64XX_SPI_CH_HS_EN;
419
420 if (dma_mode) {
421 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
422 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
423 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
424 | S3C64XX_SPI_PACKET_CNT_EN,
425 regs + S3C64XX_SPI_PACKET_CNT);
426 prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
427 }
428 }
429
430 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
431 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
432 }
433
434 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
435 int timeout_ms)
436 {
437 void __iomem *regs = sdd->regs;
438 unsigned long val = 1;
439 u32 status;
440
441 /* max fifo depth available */
442 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
443
444 if (timeout_ms)
445 val = msecs_to_loops(timeout_ms);
446
447 do {
448 status = readl(regs + S3C64XX_SPI_STATUS);
449 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
450
451 /* return the actual received data length */
452 return RX_FIFO_LVL(status, sdd);
453 }
454
455 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
456 struct spi_transfer *xfer)
457 {
458 void __iomem *regs = sdd->regs;
459 unsigned long val;
460 u32 status;
461 int ms;
462
463 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
464 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
465 ms += 10; /* some tolerance */
466
467 val = msecs_to_jiffies(ms) + 10;
468 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
469
470 /*
471 * If the previous xfer was completed within timeout, then
472 * proceed further else return -EIO.
473 * DmaTx returns after simply writing data in the FIFO,
474 * w/o waiting for real transmission on the bus to finish.
475 * DmaRx returns only after Dma read data from FIFO which
476 * needs bus transmission to finish, so we don't worry if
477 * Xfer involved Rx(with or without Tx).
478 */
479 if (val && !xfer->rx_buf) {
480 val = msecs_to_loops(10);
481 status = readl(regs + S3C64XX_SPI_STATUS);
482 while ((TX_FIFO_LVL(status, sdd)
483 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
484 && --val) {
485 cpu_relax();
486 status = readl(regs + S3C64XX_SPI_STATUS);
487 }
488
489 }
490
491 /* If timed out while checking rx/tx status return error */
492 if (!val)
493 return -EIO;
494
495 return 0;
496 }
497
498 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
499 struct spi_transfer *xfer)
500 {
501 void __iomem *regs = sdd->regs;
502 unsigned long val;
503 u32 status;
504 int loops;
505 u32 cpy_len;
506 u8 *buf;
507 int ms;
508
509 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
510 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
511 ms += 10; /* some tolerance */
512
513 val = msecs_to_loops(ms);
514 do {
515 status = readl(regs + S3C64XX_SPI_STATUS);
516 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
517
518
519 /* If it was only Tx */
520 if (!xfer->rx_buf) {
521 sdd->state &= ~TXBUSY;
522 return 0;
523 }
524
525 /*
526 * If the receive length is bigger than the controller fifo
527 * size, calculate the loops and read the fifo as many times.
528 * loops = length / max fifo size (calculated by using the
529 * fifo mask).
530 * For any size less than the fifo size the below code is
531 * executed atleast once.
532 */
533 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
534 buf = xfer->rx_buf;
535 do {
536 /* wait for data to be received in the fifo */
537 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
538 (loops ? ms : 0));
539
540 switch (sdd->cur_bpw) {
541 case 32:
542 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
543 buf, cpy_len / 4);
544 break;
545 case 16:
546 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
547 buf, cpy_len / 2);
548 break;
549 default:
550 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
551 buf, cpy_len);
552 break;
553 }
554
555 buf = buf + cpy_len;
556 } while (loops--);
557 sdd->state &= ~RXBUSY;
558
559 return 0;
560 }
561
562 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
563 {
564 void __iomem *regs = sdd->regs;
565 u32 val;
566
567 /* Disable Clock */
568 if (!sdd->port_conf->clk_from_cmu) {
569 val = readl(regs + S3C64XX_SPI_CLK_CFG);
570 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
571 writel(val, regs + S3C64XX_SPI_CLK_CFG);
572 }
573
574 /* Set Polarity and Phase */
575 val = readl(regs + S3C64XX_SPI_CH_CFG);
576 val &= ~(S3C64XX_SPI_CH_SLAVE |
577 S3C64XX_SPI_CPOL_L |
578 S3C64XX_SPI_CPHA_B);
579
580 if (sdd->cur_mode & SPI_CPOL)
581 val |= S3C64XX_SPI_CPOL_L;
582
583 if (sdd->cur_mode & SPI_CPHA)
584 val |= S3C64XX_SPI_CPHA_B;
585
586 writel(val, regs + S3C64XX_SPI_CH_CFG);
587
588 /* Set Channel & DMA Mode */
589 val = readl(regs + S3C64XX_SPI_MODE_CFG);
590 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
591 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
592
593 switch (sdd->cur_bpw) {
594 case 32:
595 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
596 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
597 break;
598 case 16:
599 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
600 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
601 break;
602 default:
603 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
604 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
605 break;
606 }
607
608 writel(val, regs + S3C64XX_SPI_MODE_CFG);
609
610 if (sdd->port_conf->clk_from_cmu) {
611 /* The src_clk clock is divided internally by 2 */
612 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
613 } else {
614 /* Configure Clock */
615 val = readl(regs + S3C64XX_SPI_CLK_CFG);
616 val &= ~S3C64XX_SPI_PSR_MASK;
617 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
618 & S3C64XX_SPI_PSR_MASK);
619 writel(val, regs + S3C64XX_SPI_CLK_CFG);
620
621 /* Enable Clock */
622 val = readl(regs + S3C64XX_SPI_CLK_CFG);
623 val |= S3C64XX_SPI_ENCLK_ENABLE;
624 writel(val, regs + S3C64XX_SPI_CLK_CFG);
625 }
626 }
627
628 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
629
630 static int s3c64xx_spi_prepare_message(struct spi_master *master,
631 struct spi_message *msg)
632 {
633 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
634 struct spi_device *spi = msg->spi;
635 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
636
637 /* Configure feedback delay */
638 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
639
640 return 0;
641 }
642
643 static int s3c64xx_spi_transfer_one(struct spi_master *master,
644 struct spi_device *spi,
645 struct spi_transfer *xfer)
646 {
647 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
648 int status;
649 u32 speed;
650 u8 bpw;
651 unsigned long flags;
652 int use_dma;
653
654 reinit_completion(&sdd->xfer_completion);
655
656 /* Only BPW and Speed may change across transfers */
657 bpw = xfer->bits_per_word;
658 speed = xfer->speed_hz;
659
660 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
661 sdd->cur_bpw = bpw;
662 sdd->cur_speed = speed;
663 sdd->cur_mode = spi->mode;
664 s3c64xx_spi_config(sdd);
665 }
666
667 /* Polling method for xfers not bigger than FIFO capacity */
668 use_dma = 0;
669 if (!is_polling(sdd) &&
670 (sdd->rx_dma.ch && sdd->tx_dma.ch &&
671 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
672 use_dma = 1;
673
674 spin_lock_irqsave(&sdd->lock, flags);
675
676 /* Pending only which is to be done */
677 sdd->state &= ~RXBUSY;
678 sdd->state &= ~TXBUSY;
679
680 enable_datapath(sdd, spi, xfer, use_dma);
681
682 /* Start the signals */
683 s3c64xx_spi_set_cs(spi, true);
684
685 spin_unlock_irqrestore(&sdd->lock, flags);
686
687 if (use_dma)
688 status = wait_for_dma(sdd, xfer);
689 else
690 status = wait_for_pio(sdd, xfer);
691
692 if (status) {
693 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
694 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
695 (sdd->state & RXBUSY) ? 'f' : 'p',
696 (sdd->state & TXBUSY) ? 'f' : 'p',
697 xfer->len);
698
699 if (use_dma) {
700 if (xfer->tx_buf != NULL
701 && (sdd->state & TXBUSY))
702 dmaengine_terminate_all(sdd->tx_dma.ch);
703 if (xfer->rx_buf != NULL
704 && (sdd->state & RXBUSY))
705 dmaengine_terminate_all(sdd->rx_dma.ch);
706 }
707 } else {
708 flush_fifo(sdd);
709 }
710
711 return status;
712 }
713
714 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
715 struct spi_device *spi)
716 {
717 struct s3c64xx_spi_csinfo *cs;
718 struct device_node *slave_np, *data_np = NULL;
719 u32 fb_delay = 0;
720
721 slave_np = spi->dev.of_node;
722 if (!slave_np) {
723 dev_err(&spi->dev, "device node not found\n");
724 return ERR_PTR(-EINVAL);
725 }
726
727 data_np = of_get_child_by_name(slave_np, "controller-data");
728 if (!data_np) {
729 dev_err(&spi->dev, "child node 'controller-data' not found\n");
730 return ERR_PTR(-EINVAL);
731 }
732
733 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
734 if (!cs) {
735 of_node_put(data_np);
736 return ERR_PTR(-ENOMEM);
737 }
738
739 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
740 cs->fb_delay = fb_delay;
741 of_node_put(data_np);
742 return cs;
743 }
744
745 /*
746 * Here we only check the validity of requested configuration
747 * and save the configuration in a local data-structure.
748 * The controller is actually configured only just before we
749 * get a message to transfer.
750 */
751 static int s3c64xx_spi_setup(struct spi_device *spi)
752 {
753 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
754 struct s3c64xx_spi_driver_data *sdd;
755 int err;
756
757 sdd = spi_master_get_devdata(spi->master);
758 if (spi->dev.of_node) {
759 cs = s3c64xx_get_slave_ctrldata(spi);
760 spi->controller_data = cs;
761 } else if (cs) {
762 /* On non-DT platforms the SPI core will set spi->cs_gpio
763 * to -ENOENT. The GPIO pin used to drive the chip select
764 * is defined by using platform data so spi->cs_gpio value
765 * has to be override to have the proper GPIO pin number.
766 */
767 spi->cs_gpio = cs->line;
768 }
769
770 if (IS_ERR_OR_NULL(cs)) {
771 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
772 return -ENODEV;
773 }
774
775 if (!spi_get_ctldata(spi)) {
776 if (gpio_is_valid(spi->cs_gpio)) {
777 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
778 dev_name(&spi->dev));
779 if (err) {
780 dev_err(&spi->dev,
781 "Failed to get /CS gpio [%d]: %d\n",
782 spi->cs_gpio, err);
783 goto err_gpio_req;
784 }
785 }
786
787 spi_set_ctldata(spi, cs);
788 }
789
790 pm_runtime_get_sync(&sdd->pdev->dev);
791
792 /* Check if we can provide the requested rate */
793 if (!sdd->port_conf->clk_from_cmu) {
794 u32 psr, speed;
795
796 /* Max possible */
797 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
798
799 if (spi->max_speed_hz > speed)
800 spi->max_speed_hz = speed;
801
802 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
803 psr &= S3C64XX_SPI_PSR_MASK;
804 if (psr == S3C64XX_SPI_PSR_MASK)
805 psr--;
806
807 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
808 if (spi->max_speed_hz < speed) {
809 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
810 psr++;
811 } else {
812 err = -EINVAL;
813 goto setup_exit;
814 }
815 }
816
817 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
818 if (spi->max_speed_hz >= speed) {
819 spi->max_speed_hz = speed;
820 } else {
821 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
822 spi->max_speed_hz);
823 err = -EINVAL;
824 goto setup_exit;
825 }
826 }
827
828 pm_runtime_mark_last_busy(&sdd->pdev->dev);
829 pm_runtime_put_autosuspend(&sdd->pdev->dev);
830 s3c64xx_spi_set_cs(spi, false);
831
832 return 0;
833
834 setup_exit:
835 pm_runtime_mark_last_busy(&sdd->pdev->dev);
836 pm_runtime_put_autosuspend(&sdd->pdev->dev);
837 /* setup() returns with device de-selected */
838 s3c64xx_spi_set_cs(spi, false);
839
840 if (gpio_is_valid(spi->cs_gpio))
841 gpio_free(spi->cs_gpio);
842 spi_set_ctldata(spi, NULL);
843
844 err_gpio_req:
845 if (spi->dev.of_node)
846 kfree(cs);
847
848 return err;
849 }
850
851 static void s3c64xx_spi_cleanup(struct spi_device *spi)
852 {
853 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
854
855 if (gpio_is_valid(spi->cs_gpio)) {
856 gpio_free(spi->cs_gpio);
857 if (spi->dev.of_node)
858 kfree(cs);
859 else {
860 /* On non-DT platforms, the SPI core sets
861 * spi->cs_gpio to -ENOENT and .setup()
862 * overrides it with the GPIO pin value
863 * passed using platform data.
864 */
865 spi->cs_gpio = -ENOENT;
866 }
867 }
868
869 spi_set_ctldata(spi, NULL);
870 }
871
872 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
873 {
874 struct s3c64xx_spi_driver_data *sdd = data;
875 struct spi_master *spi = sdd->master;
876 unsigned int val, clr = 0;
877
878 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
879
880 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
881 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
882 dev_err(&spi->dev, "RX overrun\n");
883 }
884 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
885 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
886 dev_err(&spi->dev, "RX underrun\n");
887 }
888 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
889 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
890 dev_err(&spi->dev, "TX overrun\n");
891 }
892 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
893 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
894 dev_err(&spi->dev, "TX underrun\n");
895 }
896
897 /* Clear the pending irq by setting and then clearing it */
898 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
899 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
900
901 return IRQ_HANDLED;
902 }
903
904 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
905 {
906 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
907 void __iomem *regs = sdd->regs;
908 unsigned int val;
909
910 sdd->cur_speed = 0;
911
912 if (sci->no_cs)
913 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
914 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
915 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
916
917 /* Disable Interrupts - we use Polling if not DMA mode */
918 writel(0, regs + S3C64XX_SPI_INT_EN);
919
920 if (!sdd->port_conf->clk_from_cmu)
921 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
922 regs + S3C64XX_SPI_CLK_CFG);
923 writel(0, regs + S3C64XX_SPI_MODE_CFG);
924 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
925
926 /* Clear any irq pending bits, should set and clear the bits */
927 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
928 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
929 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
930 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
931 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
932 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
933
934 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
935
936 val = readl(regs + S3C64XX_SPI_MODE_CFG);
937 val &= ~S3C64XX_SPI_MODE_4BURST;
938 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
939 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
940 writel(val, regs + S3C64XX_SPI_MODE_CFG);
941
942 flush_fifo(sdd);
943 }
944
945 #ifdef CONFIG_OF
946 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
947 {
948 struct s3c64xx_spi_info *sci;
949 u32 temp;
950
951 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
952 if (!sci)
953 return ERR_PTR(-ENOMEM);
954
955 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
956 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
957 sci->src_clk_nr = 0;
958 } else {
959 sci->src_clk_nr = temp;
960 }
961
962 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
963 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
964 sci->num_cs = 1;
965 } else {
966 sci->num_cs = temp;
967 }
968
969 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
970
971 return sci;
972 }
973 #else
974 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
975 {
976 return dev_get_platdata(dev);
977 }
978 #endif
979
980 static const struct of_device_id s3c64xx_spi_dt_match[];
981
982 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
983 struct platform_device *pdev)
984 {
985 #ifdef CONFIG_OF
986 if (pdev->dev.of_node) {
987 const struct of_device_id *match;
988 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
989 return (struct s3c64xx_spi_port_config *)match->data;
990 }
991 #endif
992 return (struct s3c64xx_spi_port_config *)
993 platform_get_device_id(pdev)->driver_data;
994 }
995
996 static int s3c64xx_spi_probe(struct platform_device *pdev)
997 {
998 struct resource *mem_res;
999 struct s3c64xx_spi_driver_data *sdd;
1000 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1001 struct spi_master *master;
1002 int ret, irq;
1003 char clk_name[16];
1004
1005 if (!sci && pdev->dev.of_node) {
1006 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1007 if (IS_ERR(sci))
1008 return PTR_ERR(sci);
1009 }
1010
1011 if (!sci) {
1012 dev_err(&pdev->dev, "platform_data missing!\n");
1013 return -ENODEV;
1014 }
1015
1016 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1017 if (mem_res == NULL) {
1018 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1019 return -ENXIO;
1020 }
1021
1022 irq = platform_get_irq(pdev, 0);
1023 if (irq < 0) {
1024 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1025 return irq;
1026 }
1027
1028 master = spi_alloc_master(&pdev->dev,
1029 sizeof(struct s3c64xx_spi_driver_data));
1030 if (master == NULL) {
1031 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1032 return -ENOMEM;
1033 }
1034
1035 platform_set_drvdata(pdev, master);
1036
1037 sdd = spi_master_get_devdata(master);
1038 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1039 sdd->master = master;
1040 sdd->cntrlr_info = sci;
1041 sdd->pdev = pdev;
1042 sdd->sfr_start = mem_res->start;
1043 if (pdev->dev.of_node) {
1044 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1045 if (ret < 0) {
1046 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1047 ret);
1048 goto err_deref_master;
1049 }
1050 sdd->port_id = ret;
1051 } else {
1052 sdd->port_id = pdev->id;
1053 }
1054
1055 sdd->cur_bpw = 8;
1056
1057 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1058 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1059
1060 master->dev.of_node = pdev->dev.of_node;
1061 master->bus_num = sdd->port_id;
1062 master->setup = s3c64xx_spi_setup;
1063 master->cleanup = s3c64xx_spi_cleanup;
1064 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1065 master->prepare_message = s3c64xx_spi_prepare_message;
1066 master->transfer_one = s3c64xx_spi_transfer_one;
1067 master->num_chipselect = sci->num_cs;
1068 master->dma_alignment = 8;
1069 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1070 SPI_BPW_MASK(8);
1071 /* the spi->mode bits understood by this driver: */
1072 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1073 master->auto_runtime_pm = true;
1074 if (!is_polling(sdd))
1075 master->can_dma = s3c64xx_spi_can_dma;
1076
1077 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1078 if (IS_ERR(sdd->regs)) {
1079 ret = PTR_ERR(sdd->regs);
1080 goto err_deref_master;
1081 }
1082
1083 if (sci->cfg_gpio && sci->cfg_gpio()) {
1084 dev_err(&pdev->dev, "Unable to config gpio\n");
1085 ret = -EBUSY;
1086 goto err_deref_master;
1087 }
1088
1089 /* Setup clocks */
1090 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1091 if (IS_ERR(sdd->clk)) {
1092 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1093 ret = PTR_ERR(sdd->clk);
1094 goto err_deref_master;
1095 }
1096
1097 ret = clk_prepare_enable(sdd->clk);
1098 if (ret) {
1099 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1100 goto err_deref_master;
1101 }
1102
1103 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1104 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1105 if (IS_ERR(sdd->src_clk)) {
1106 dev_err(&pdev->dev,
1107 "Unable to acquire clock '%s'\n", clk_name);
1108 ret = PTR_ERR(sdd->src_clk);
1109 goto err_disable_clk;
1110 }
1111
1112 ret = clk_prepare_enable(sdd->src_clk);
1113 if (ret) {
1114 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1115 goto err_disable_clk;
1116 }
1117
1118 if (sdd->port_conf->clk_ioclk) {
1119 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1120 if (IS_ERR(sdd->ioclk)) {
1121 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1122 ret = PTR_ERR(sdd->ioclk);
1123 goto err_disable_src_clk;
1124 }
1125
1126 ret = clk_prepare_enable(sdd->ioclk);
1127 if (ret) {
1128 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1129 goto err_disable_src_clk;
1130 }
1131 }
1132
1133 if (!is_polling(sdd)) {
1134 /* Acquire DMA channels */
1135 sdd->rx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1136 "rx");
1137 if (IS_ERR(sdd->rx_dma.ch)) {
1138 dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1139 ret = PTR_ERR(sdd->rx_dma.ch);
1140 goto err_disable_io_clk;
1141 }
1142 sdd->tx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1143 "tx");
1144 if (IS_ERR(sdd->tx_dma.ch)) {
1145 dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1146 ret = PTR_ERR(sdd->tx_dma.ch);
1147 goto err_release_rx_dma;
1148 }
1149 }
1150
1151 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1152 pm_runtime_use_autosuspend(&pdev->dev);
1153 pm_runtime_set_active(&pdev->dev);
1154 pm_runtime_enable(&pdev->dev);
1155 pm_runtime_get_sync(&pdev->dev);
1156
1157 /* Setup Deufult Mode */
1158 s3c64xx_spi_hwinit(sdd, sdd->port_id);
1159
1160 spin_lock_init(&sdd->lock);
1161 init_completion(&sdd->xfer_completion);
1162
1163 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1164 "spi-s3c64xx", sdd);
1165 if (ret != 0) {
1166 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1167 irq, ret);
1168 goto err_pm_put;
1169 }
1170
1171 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1172 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1173 sdd->regs + S3C64XX_SPI_INT_EN);
1174
1175 ret = devm_spi_register_master(&pdev->dev, master);
1176 if (ret != 0) {
1177 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1178 goto err_pm_put;
1179 }
1180
1181 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1182 sdd->port_id, master->num_chipselect);
1183 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1184 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1185
1186 pm_runtime_mark_last_busy(&pdev->dev);
1187 pm_runtime_put_autosuspend(&pdev->dev);
1188
1189 return 0;
1190
1191 err_pm_put:
1192 pm_runtime_put_noidle(&pdev->dev);
1193 pm_runtime_disable(&pdev->dev);
1194 pm_runtime_set_suspended(&pdev->dev);
1195
1196 if (!is_polling(sdd))
1197 dma_release_channel(sdd->tx_dma.ch);
1198 err_release_rx_dma:
1199 if (!is_polling(sdd))
1200 dma_release_channel(sdd->rx_dma.ch);
1201 err_disable_io_clk:
1202 clk_disable_unprepare(sdd->ioclk);
1203 err_disable_src_clk:
1204 clk_disable_unprepare(sdd->src_clk);
1205 err_disable_clk:
1206 clk_disable_unprepare(sdd->clk);
1207 err_deref_master:
1208 spi_master_put(master);
1209
1210 return ret;
1211 }
1212
1213 static int s3c64xx_spi_remove(struct platform_device *pdev)
1214 {
1215 struct spi_master *master = platform_get_drvdata(pdev);
1216 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1217
1218 pm_runtime_get_sync(&pdev->dev);
1219
1220 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1221
1222 if (!is_polling(sdd)) {
1223 dma_release_channel(sdd->rx_dma.ch);
1224 dma_release_channel(sdd->tx_dma.ch);
1225 }
1226
1227 clk_disable_unprepare(sdd->ioclk);
1228
1229 clk_disable_unprepare(sdd->src_clk);
1230
1231 clk_disable_unprepare(sdd->clk);
1232
1233 pm_runtime_put_noidle(&pdev->dev);
1234 pm_runtime_disable(&pdev->dev);
1235 pm_runtime_set_suspended(&pdev->dev);
1236
1237 return 0;
1238 }
1239
1240 #ifdef CONFIG_PM_SLEEP
1241 static int s3c64xx_spi_suspend(struct device *dev)
1242 {
1243 struct spi_master *master = dev_get_drvdata(dev);
1244 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1245
1246 int ret = spi_master_suspend(master);
1247 if (ret)
1248 return ret;
1249
1250 ret = pm_runtime_force_suspend(dev);
1251 if (ret < 0)
1252 return ret;
1253
1254 sdd->cur_speed = 0; /* Output Clock is stopped */
1255
1256 return 0;
1257 }
1258
1259 static int s3c64xx_spi_resume(struct device *dev)
1260 {
1261 struct spi_master *master = dev_get_drvdata(dev);
1262 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1263 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1264 int ret;
1265
1266 if (sci->cfg_gpio)
1267 sci->cfg_gpio();
1268
1269 ret = pm_runtime_force_resume(dev);
1270 if (ret < 0)
1271 return ret;
1272
1273 s3c64xx_spi_hwinit(sdd, sdd->port_id);
1274
1275 return spi_master_resume(master);
1276 }
1277 #endif /* CONFIG_PM_SLEEP */
1278
1279 #ifdef CONFIG_PM
1280 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1281 {
1282 struct spi_master *master = dev_get_drvdata(dev);
1283 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1284
1285 clk_disable_unprepare(sdd->clk);
1286 clk_disable_unprepare(sdd->src_clk);
1287 clk_disable_unprepare(sdd->ioclk);
1288
1289 return 0;
1290 }
1291
1292 static int s3c64xx_spi_runtime_resume(struct device *dev)
1293 {
1294 struct spi_master *master = dev_get_drvdata(dev);
1295 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1296 int ret;
1297
1298 if (sdd->port_conf->clk_ioclk) {
1299 ret = clk_prepare_enable(sdd->ioclk);
1300 if (ret != 0)
1301 return ret;
1302 }
1303
1304 ret = clk_prepare_enable(sdd->src_clk);
1305 if (ret != 0)
1306 goto err_disable_ioclk;
1307
1308 ret = clk_prepare_enable(sdd->clk);
1309 if (ret != 0)
1310 goto err_disable_src_clk;
1311
1312 return 0;
1313
1314 err_disable_src_clk:
1315 clk_disable_unprepare(sdd->src_clk);
1316 err_disable_ioclk:
1317 clk_disable_unprepare(sdd->ioclk);
1318
1319 return ret;
1320 }
1321 #endif /* CONFIG_PM */
1322
1323 static const struct dev_pm_ops s3c64xx_spi_pm = {
1324 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1325 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1326 s3c64xx_spi_runtime_resume, NULL)
1327 };
1328
1329 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1330 .fifo_lvl_mask = { 0x7f },
1331 .rx_lvl_offset = 13,
1332 .tx_st_done = 21,
1333 .high_speed = true,
1334 };
1335
1336 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1337 .fifo_lvl_mask = { 0x7f, 0x7F },
1338 .rx_lvl_offset = 13,
1339 .tx_st_done = 21,
1340 };
1341
1342 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1343 .fifo_lvl_mask = { 0x1ff, 0x7F },
1344 .rx_lvl_offset = 15,
1345 .tx_st_done = 25,
1346 .high_speed = true,
1347 };
1348
1349 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1350 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1351 .rx_lvl_offset = 15,
1352 .tx_st_done = 25,
1353 .high_speed = true,
1354 .clk_from_cmu = true,
1355 };
1356
1357 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1358 .fifo_lvl_mask = { 0x1ff },
1359 .rx_lvl_offset = 15,
1360 .tx_st_done = 25,
1361 .high_speed = true,
1362 .clk_from_cmu = true,
1363 .quirks = S3C64XX_SPI_QUIRK_POLL,
1364 };
1365
1366 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1367 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1368 .rx_lvl_offset = 15,
1369 .tx_st_done = 25,
1370 .high_speed = true,
1371 .clk_from_cmu = true,
1372 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1373 };
1374
1375 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1376 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1377 .rx_lvl_offset = 15,
1378 .tx_st_done = 25,
1379 .high_speed = true,
1380 .clk_from_cmu = true,
1381 .clk_ioclk = true,
1382 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1383 };
1384
1385 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1386 {
1387 .name = "s3c2443-spi",
1388 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1389 }, {
1390 .name = "s3c6410-spi",
1391 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1392 },
1393 { },
1394 };
1395
1396 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1397 { .compatible = "samsung,s3c2443-spi",
1398 .data = (void *)&s3c2443_spi_port_config,
1399 },
1400 { .compatible = "samsung,s3c6410-spi",
1401 .data = (void *)&s3c6410_spi_port_config,
1402 },
1403 { .compatible = "samsung,s5pv210-spi",
1404 .data = (void *)&s5pv210_spi_port_config,
1405 },
1406 { .compatible = "samsung,exynos4210-spi",
1407 .data = (void *)&exynos4_spi_port_config,
1408 },
1409 { .compatible = "samsung,exynos5440-spi",
1410 .data = (void *)&exynos5440_spi_port_config,
1411 },
1412 { .compatible = "samsung,exynos7-spi",
1413 .data = (void *)&exynos7_spi_port_config,
1414 },
1415 { .compatible = "samsung,exynos5433-spi",
1416 .data = (void *)&exynos5433_spi_port_config,
1417 },
1418 { },
1419 };
1420 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1421
1422 static struct platform_driver s3c64xx_spi_driver = {
1423 .driver = {
1424 .name = "s3c64xx-spi",
1425 .pm = &s3c64xx_spi_pm,
1426 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1427 },
1428 .probe = s3c64xx_spi_probe,
1429 .remove = s3c64xx_spi_remove,
1430 .id_table = s3c64xx_spi_driver_ids,
1431 };
1432 MODULE_ALIAS("platform:s3c64xx-spi");
1433
1434 module_platform_driver(s3c64xx_spi_driver);
1435
1436 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1437 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1438 MODULE_LICENSE("GPL");
Linux with added FPC-III support