arch/m68k/include/asm/m5407sim.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      m5407sim.h -- ColdFire 5407 System Integration Module support.
   5  *
   6  *      (C) Copyright 2000,  Lineo (www.lineo.com)
   7  *      (C) Copyright 1999,  Moreton Bay Ventures Pty Ltd.
   8  *
   9  *      Modified by David W. Miller for the MCF5307 Eval Board.
  10  */
  11
  12 /****************************************************************************/
  13 #ifndef m5407sim_h
  14 #define m5407sim_h
  15 /****************************************************************************/
  16
  17 #define CPU_NAME                "COLDFIRE(m5407)"
  18 #define CPU_INSTR_PER_JIFFY     3
  19 #define MCF_BUSCLK              (MCF_CLK / 2)
  20
  21 #include <asm/m54xxacr.h>
  22
  23 /*
  24  *      Define the 5407 SIM register set addresses.
  25  */
  26 #define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
  27 #define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
  28 #define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
  29 #define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
  30 #define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
  31 #define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
  32 #define MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
  33 #define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
  34 #define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
  35 #define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
  36 #define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
  37 #define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
  38 #define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
  39 #define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
  40 #define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
  41 #define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
  42 #define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
  43 #define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
  44 #define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
  45 #define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
  46 #define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
  47 #define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
  48 #define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
  49
  50 #define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
  51 #define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
  52 #define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
  53 #define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
  54 #define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
  55 #define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
  56
  57 #define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
  58 #define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
  59 #define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
  60 #define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
  61 #define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
  62 #define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
  63 #define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
  64 #define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
  65 #define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
  66 #define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
  67 #define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
  68 #define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
  69 #define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
  70 #define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
  71 #define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
  72 #define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
  73 #define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
  74 #define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
  75
  76 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
  77 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
  78 #define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM 0 Mask */
  79 #define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM 1 Addr/Ctrl */
  80 #define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM 1 Mask */
  81
  82 /*
  83  *      Timer module.
  84  */
  85 #define MCFTIMER_BASE1          (MCF_MBAR + 0x140)      /* Base of TIMER1 */
  86 #define MCFTIMER_BASE2          (MCF_MBAR + 0x180)      /* Base of TIMER2 */
  87
  88 #define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
  89 #define MCFUART_BASE2           0x200           /* Base address of UART2 */
  90
  91 #define MCFSIM_PADDR            (MCF_MBAR + 0x244)
  92 #define MCFSIM_PADAT            (MCF_MBAR + 0x248)
  93
  94 /*
  95  *      DMA unit base addresses.
  96  */
  97 #define MCFDMA_BASE0            (MCF_MBAR + 0x300)      /* Base address DMA 0 */
  98 #define MCFDMA_BASE1            (MCF_MBAR + 0x340)      /* Base address DMA 1 */
  99 #define MCFDMA_BASE2            (MCF_MBAR + 0x380)      /* Base address DMA 2 */
 100 #define MCFDMA_BASE3            (MCF_MBAR + 0x3C0)      /* Base address DMA 3 */
 101
 102 /*
 103  * Generic GPIO support
 104  */
 105 #define MCFGPIO_PIN_MAX                 16
 106 #define MCFGPIO_IRQ_MAX                 -1
 107 #define MCFGPIO_IRQ_VECBASE             -1
 108
 109 /*
 110  *      Some symbol defines for the above...
 111  */
 112 #define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
 113 #define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
 114 #define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
 115 #define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
 116 #define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
 117 #define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
 118 #define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
 119 #define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
 120 #define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
 121
 122 /*
 123  *      Some symbol defines for the Parallel Port Pin Assignment Register
 124  */
 125 #define MCFSIM_PAR_DREQ0        0x40            /* Set to select DREQ0 input */
 126                                                 /* Clear to select par I/O */
 127 #define MCFSIM_PAR_DREQ1        0x20            /* Select DREQ1 input */
 128                                                 /* Clear to select par I/O */
 129
 130 /*
 131  *       Defines for the IRQPAR Register
 132  */
 133 #define IRQ5_LEVEL4     0x80
 134 #define IRQ3_LEVEL6     0x40
 135 #define IRQ1_LEVEL2     0x20
 136
 137 /*
 138  *      Define system peripheral IRQ usage.
 139  */
 140 #define MCF_IRQ_TIMER           30              /* Timer0, Level 6 */
 141 #define MCF_IRQ_PROFILER        31              /* Timer1, Level 7 */
 142
 143 /****************************************************************************/
 144 #endif  /* m5407sim_h */