arch/m68k/include/asm/m54xxacr.h

   1 /*
   2  * Bit definitions for the MCF54xx ACR and CACR registers.
   3  */
   4
   5 #ifndef m54xxacr_h
   6 #define m54xxacr_h
   7
   8 /*
   9  *      Define the Cache register flags.
  10  */
  11 #define CACR_DEC        0x80000000      /* Enable data cache */
  12 #define CACR_DWP        0x40000000      /* Data write protection */
  13 #define CACR_DESB       0x20000000      /* Enable data store buffer */
  14 #define CACR_DDPI       0x10000000      /* Disable invalidation by CPUSHL */
  15 #define CACR_DHCLK      0x08000000      /* Half data cache lock mode */
  16 #define CACR_DDCM_WT    0x00000000      /* Write through cache*/
  17 #define CACR_DDCM_CP    0x02000000      /* Copyback cache */
  18 #define CACR_DDCM_P     0x04000000      /* No cache, precise */
  19 #define CACR_DDCM_IMP   0x06000000      /* No cache, imprecise */
  20 #define CACR_DCINVA     0x01000000      /* Invalidate data cache */
  21 #define CACR_BEC        0x00080000      /* Enable branch cache */
  22 #define CACR_BCINVA     0x00040000      /* Invalidate branch cache */
  23 #define CACR_IEC        0x00008000      /* Enable instruction cache */
  24 #define CACR_DNFB       0x00002000      /* Inhibited fill buffer */
  25 #define CACR_IDPI       0x00001000      /* Disable CPUSHL */
  26 #define CACR_IHLCK      0x00000800      /* Intruction cache half lock */
  27 #define CACR_IDCM       0x00000400      /* Intruction cache inhibit */
  28 #define CACR_ICINVA     0x00000100      /* Invalidate instr cache */
  29 #define CACR_EUSP       0x00000020      /* Enable separate user a7 */
  30
  31 #define ACR_BASE_POS    24              /* Address Base */
  32 #define ACR_MASK_POS    16              /* Address Mask */
  33 #define ACR_ENABLE      0x00008000      /* Enable address */
  34 #define ACR_USER        0x00000000      /* User mode access only */
  35 #define ACR_SUPER       0x00002000      /* Supervisor mode only */
  36 #define ACR_ANY         0x00004000      /* Match any access mode */
  37 #define ACR_CM_WT       0x00000000      /* Write through mode */
  38 #define ACR_CM_CP       0x00000020      /* Copyback mode */
  39 #define ACR_CM_OFF_PRE  0x00000040      /* No cache, precise */
  40 #define ACR_CM_OFF_IMP  0x00000060      /* No cache, imprecise */
  41 #define ACR_CM          0x00000060      /* Cache mode mask */
  42 #define ACR_WPROTECT    0x00000004      /* Write protect */
  43
  44 #if defined(CONFIG_M5407)
  45
  46 #define ICACHE_SIZE 0x4000      /* instruction - 16k */
  47 #define DCACHE_SIZE 0x2000      /* data - 8k */
  48
  49 #elif defined(CONFIG_M54xx)
  50
  51 #define ICACHE_SIZE 0x8000      /* instruction - 32k */
  52 #define DCACHE_SIZE 0x8000      /* data - 32k */
  53
  54 #endif
  55
  56 #define CACHE_LINE_SIZE 0x0010  /* 16 bytes */
  57 #define CACHE_WAYS 4            /* 4 ways */
  58
  59 /*
  60  *      Version 4 cores have a true harvard style separate instruction
  61  *      and data cache. Enable data and instruction caches, also enable write
  62  *      buffers and branch accelerator.
  63  */
  64 /* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */
  65 /* use '+' instead of '|' for assembler's sake */
  66
  67         /* Enable data cache */
  68         /* Enable data store buffer */
  69         /* outside ACRs : No cache, precise */
  70         /* Enable instruction+branch caches */
  71 #if defined(CONFIG_M5407)
  72 #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
  73 #else
  74 #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
  75 #endif
  76 #if defined(CONFIG_CACHE_COPYBACK)
  77 #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
  78 #else
  79 #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
  80 #endif
  81 #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
  82
  83 #define CACHE_INIT      (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
  84 #define CACHE_INVALIDATE  (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
  85 #define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA)
  86 #define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA)
  87 #define ACR0_MODE       (0x000f0000+DATA_CACHE_MODE)
  88 #define ACR1_MODE       0
  89 #define ACR2_MODE       (0x000f0000+INSN_CACHE_MODE)
  90 #define ACR3_MODE       0
  91
  92 #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
  93 /* Copyback cache mode must push dirty cache lines first */
  94 #define CACHE_PUSH
  95 #endif
  96
  97 #endif  /* m54xxacr_h */