arch/m68k/include/asm/mcfintc.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      mcfintc.h -- support definitions for the simple ColdFire
   5  *                   Interrupt Controller
   6  *
   7  *      (C) Copyright 2009,  Greg Ungerer <gerg@uclinux.org>
   8  */
   9
  10 /****************************************************************************/
  11 #ifndef mcfintc_h
  12 #define mcfintc_h
  13 /****************************************************************************/
  14
  15 /*
  16  * Most of the older ColdFire parts use the same simple interrupt
  17  * controller. This is currently used on the 5206, 5206e, 5249, 5307
  18  * and 5407 parts.
  19  *
  20  * The builtin peripherals are masked through dedicated bits in the
  21  * Interrupt Mask register (IMR) - and this is not indexed (or in any way
  22  * related to) the actual interrupt number they use. So knowing the IRQ
  23  * number doesn't explicitly map to a certain internal device for
  24  * interrupt control purposes.
  25  */
  26
  27 /*
  28  * Bit definitions for the ICR family of registers.
  29  */
  30 #define MCFSIM_ICR_AUTOVEC      0x80            /* Auto-vectored intr */
  31 #define MCFSIM_ICR_LEVEL0       0x00            /* Level 0 intr */
  32 #define MCFSIM_ICR_LEVEL1       0x04            /* Level 1 intr */
  33 #define MCFSIM_ICR_LEVEL2       0x08            /* Level 2 intr */
  34 #define MCFSIM_ICR_LEVEL3       0x0c            /* Level 3 intr */
  35 #define MCFSIM_ICR_LEVEL4       0x10            /* Level 4 intr */
  36 #define MCFSIM_ICR_LEVEL5       0x14            /* Level 5 intr */
  37 #define MCFSIM_ICR_LEVEL6       0x18            /* Level 6 intr */
  38 #define MCFSIM_ICR_LEVEL7       0x1c            /* Level 7 intr */
  39
  40 #define MCFSIM_ICR_PRI0         0x00            /* Priority 0 intr */
  41 #define MCFSIM_ICR_PRI1         0x01            /* Priority 1 intr */
  42 #define MCFSIM_ICR_PRI2         0x02            /* Priority 2 intr */
  43 #define MCFSIM_ICR_PRI3         0x03            /* Priority 3 intr */
  44
  45 /*
  46  * IMR bit position definitions. Not all ColdFire parts with this interrupt
  47  * controller actually support all of these interrupt sources. But the bit
  48  * numbers are the same in all cores.
  49  */
  50 #define MCFINTC_EINT1           1               /* External int #1 */
  51 #define MCFINTC_EINT2           2               /* External int #2 */
  52 #define MCFINTC_EINT3           3               /* External int #3 */
  53 #define MCFINTC_EINT4           4               /* External int #4 */
  54 #define MCFINTC_EINT5           5               /* External int #5 */
  55 #define MCFINTC_EINT6           6               /* External int #6 */
  56 #define MCFINTC_EINT7           7               /* External int #7 */
  57 #define MCFINTC_SWT             8               /* Software Watchdog */
  58 #define MCFINTC_TIMER1          9
  59 #define MCFINTC_TIMER2          10
  60 #define MCFINTC_I2C             11              /* I2C / MBUS */
  61 #define MCFINTC_UART0           12
  62 #define MCFINTC_UART1           13
  63 #define MCFINTC_DMA0            14
  64 #define MCFINTC_DMA1            15
  65 #define MCFINTC_DMA2            16
  66 #define MCFINTC_DMA3            17
  67 #define MCFINTC_QSPI            18
  68
  69 #ifndef __ASSEMBLER__
  70
  71 /*
  72  * There is no one-is-one correspondance between the interrupt number (irq)
  73  * and the bit fields on the mask register. So we create a per-cpu type
  74  * mapping of irq to mask bit. The CPU platform code needs to register
  75  * its supported irq's at init time, using this function.
  76  */
  77 extern unsigned char mcf_irq2imr[];
  78 static inline void mcf_mapirq2imr(int irq, int imr)
  79 {
  80         mcf_irq2imr[irq] = imr;
  81 }
  82
  83 void mcf_autovector(int irq);
  84 void mcf_setimr(int index);
  85 void mcf_clrimr(int index);
  86 #endif
  87
  88 /****************************************************************************/
  89 #endif  /* mcfintc_h */