arch/m68k/include/asm/mcfuart.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      mcfuart.h -- ColdFire internal UART support defines.
   5  *
   6  *      (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
   7  *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
   8  */
   9
  10 /****************************************************************************/
  11 #ifndef mcfuart_h
  12 #define mcfuart_h
  13 /****************************************************************************/
  14
  15 #include <linux/serial_core.h>
  16 #include <linux/platform_device.h>
  17
  18 struct mcf_platform_uart {
  19         unsigned long   mapbase;        /* Physical address base */
  20         void __iomem    *membase;       /* Virtual address if mapped */
  21         unsigned int    irq;            /* Interrupt vector */
  22         unsigned int    uartclk;        /* UART clock rate */
  23 };
  24
  25 /*
  26  *      Define the ColdFire UART register set addresses.
  27  */
  28 #define MCFUART_UMR             0x00            /* Mode register (r/w) */
  29 #define MCFUART_USR             0x04            /* Status register (r) */
  30 #define MCFUART_UCSR            0x04            /* Clock Select (w) */
  31 #define MCFUART_UCR             0x08            /* Command register (w) */
  32 #define MCFUART_URB             0x0c            /* Receiver Buffer (r) */
  33 #define MCFUART_UTB             0x0c            /* Transmit Buffer (w) */
  34 #define MCFUART_UIPCR           0x10            /* Input Port Change (r) */
  35 #define MCFUART_UACR            0x10            /* Auxiliary Control (w) */
  36 #define MCFUART_UISR            0x14            /* Interrupt Status (r) */
  37 #define MCFUART_UIMR            0x14            /* Interrupt Mask (w) */
  38 #define MCFUART_UBG1            0x18            /* Baud Rate MSB (r/w) */
  39 #define MCFUART_UBG2            0x1c            /* Baud Rate LSB (r/w) */
  40 #ifdef  CONFIG_M5272
  41 #define MCFUART_UTF             0x28            /* Transmitter FIFO (r/w) */
  42 #define MCFUART_URF             0x2c            /* Receiver FIFO (r/w) */
  43 #define MCFUART_UFPD            0x30            /* Frac Prec. Divider (r/w) */
  44 #else
  45 #define MCFUART_UIVR            0x30            /* Interrupt Vector (r/w) */
  46 #endif
  47 #define MCFUART_UIPR            0x34            /* Input Port (r) */
  48 #define MCFUART_UOP1            0x38            /* Output Port Bit Set (w) */
  49 #define MCFUART_UOP0            0x3c            /* Output Port Bit Reset (w) */
  50
  51
  52 /*
  53  *      Define bit flags in Mode Register 1 (MR1).
  54  */
  55 #define MCFUART_MR1_RXRTS       0x80            /* Auto RTS flow control */
  56 #define MCFUART_MR1_RXIRQFULL   0x40            /* RX IRQ type FULL */
  57 #define MCFUART_MR1_RXIRQRDY    0x00            /* RX IRQ type RDY */
  58 #define MCFUART_MR1_RXERRBLOCK  0x20            /* RX block error mode */
  59 #define MCFUART_MR1_RXERRCHAR   0x00            /* RX char error mode */
  60
  61 #define MCFUART_MR1_PARITYNONE  0x10            /* No parity */
  62 #define MCFUART_MR1_PARITYEVEN  0x00            /* Even parity */
  63 #define MCFUART_MR1_PARITYODD   0x04            /* Odd parity */
  64 #define MCFUART_MR1_PARITYSPACE 0x08            /* Space parity */
  65 #define MCFUART_MR1_PARITYMARK  0x0c            /* Mark parity */
  66
  67 #define MCFUART_MR1_CS5         0x00            /* 5 bits per char */
  68 #define MCFUART_MR1_CS6         0x01            /* 6 bits per char */
  69 #define MCFUART_MR1_CS7         0x02            /* 7 bits per char */
  70 #define MCFUART_MR1_CS8         0x03            /* 8 bits per char */
  71
  72 /*
  73  *      Define bit flags in Mode Register 2 (MR2).
  74  */
  75 #define MCFUART_MR2_LOOPBACK    0x80            /* Loopback mode */
  76 #define MCFUART_MR2_REMOTELOOP  0xc0            /* Remote loopback mode */
  77 #define MCFUART_MR2_AUTOECHO    0x40            /* Automatic echo */
  78 #define MCFUART_MR2_TXRTS       0x20            /* Assert RTS on TX */
  79 #define MCFUART_MR2_TXCTS       0x10            /* Auto CTS flow control */
  80
  81 #define MCFUART_MR2_STOP1       0x07            /* 1 stop bit */
  82 #define MCFUART_MR2_STOP15      0x08            /* 1.5 stop bits */
  83 #define MCFUART_MR2_STOP2       0x0f            /* 2 stop bits */
  84
  85 /*
  86  *      Define bit flags in Status Register (USR).
  87  */
  88 #define MCFUART_USR_RXBREAK     0x80            /* Received BREAK */
  89 #define MCFUART_USR_RXFRAMING   0x40            /* Received framing error */
  90 #define MCFUART_USR_RXPARITY    0x20            /* Received parity error */
  91 #define MCFUART_USR_RXOVERRUN   0x10            /* Received overrun error */
  92 #define MCFUART_USR_TXEMPTY     0x08            /* Transmitter empty */
  93 #define MCFUART_USR_TXREADY     0x04            /* Transmitter ready */
  94 #define MCFUART_USR_RXFULL      0x02            /* Receiver full */
  95 #define MCFUART_USR_RXREADY     0x01            /* Receiver ready */
  96
  97 #define MCFUART_USR_RXERR       (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
  98                                 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
  99
 100 /*
 101  *      Define bit flags in Clock Select Register (UCSR).
 102  */
 103 #define MCFUART_UCSR_RXCLKTIMER 0xd0            /* RX clock is timer */
 104 #define MCFUART_UCSR_RXCLKEXT16 0xe0            /* RX clock is external x16 */
 105 #define MCFUART_UCSR_RXCLKEXT1  0xf0            /* RX clock is external x1 */
 106
 107 #define MCFUART_UCSR_TXCLKTIMER 0x0d            /* TX clock is timer */
 108 #define MCFUART_UCSR_TXCLKEXT16 0x0e            /* TX clock is external x16 */
 109 #define MCFUART_UCSR_TXCLKEXT1  0x0f            /* TX clock is external x1 */
 110
 111 /*
 112  *      Define bit flags in Command Register (UCR).
 113  */
 114 #define MCFUART_UCR_CMDNULL             0x00    /* No command */
 115 #define MCFUART_UCR_CMDRESETMRPTR       0x10    /* Reset MR pointer */
 116 #define MCFUART_UCR_CMDRESETRX          0x20    /* Reset receiver */
 117 #define MCFUART_UCR_CMDRESETTX          0x30    /* Reset transmitter */
 118 #define MCFUART_UCR_CMDRESETERR         0x40    /* Reset error status */
 119 #define MCFUART_UCR_CMDRESETBREAK       0x50    /* Reset BREAK change */
 120 #define MCFUART_UCR_CMDBREAKSTART       0x60    /* Start BREAK */
 121 #define MCFUART_UCR_CMDBREAKSTOP        0x70    /* Stop BREAK */
 122
 123 #define MCFUART_UCR_TXNULL      0x00            /* No TX command */
 124 #define MCFUART_UCR_TXENABLE    0x04            /* Enable TX */
 125 #define MCFUART_UCR_TXDISABLE   0x08            /* Disable TX */
 126 #define MCFUART_UCR_RXNULL      0x00            /* No RX command */
 127 #define MCFUART_UCR_RXENABLE    0x01            /* Enable RX */
 128 #define MCFUART_UCR_RXDISABLE   0x02            /* Disable RX */
 129
 130 /*
 131  *      Define bit flags in Input Port Change Register (UIPCR).
 132  */
 133 #define MCFUART_UIPCR_CTSCOS    0x10            /* CTS change of state */
 134 #define MCFUART_UIPCR_CTS       0x01            /* CTS value */
 135
 136 /*
 137  *      Define bit flags in Input Port Register (UIP).
 138  */
 139 #define MCFUART_UIPR_CTS        0x01            /* CTS value */
 140
 141 /*
 142  *      Define bit flags in Output Port Registers (UOP).
 143  *      Clear bit by writing to UOP0, set by writing to UOP1.
 144  */
 145 #define MCFUART_UOP_RTS         0x01            /* RTS set or clear */
 146
 147 /*
 148  *      Define bit flags in the Auxiliary Control Register (UACR).
 149  */
 150 #define MCFUART_UACR_IEC        0x01            /* Input enable control */
 151
 152 /*
 153  *      Define bit flags in Interrupt Status Register (UISR).
 154  *      These same bits are used for the Interrupt Mask Register (UIMR).
 155  */
 156 #define MCFUART_UIR_COS         0x80            /* Change of state (CTS) */
 157 #define MCFUART_UIR_DELTABREAK  0x04            /* Break start or stop */
 158 #define MCFUART_UIR_RXREADY     0x02            /* Receiver ready */
 159 #define MCFUART_UIR_TXREADY     0x01            /* Transmitter ready */
 160
 161 #ifdef  CONFIG_M5272
 162 /*
 163  *      Define bit flags in the Transmitter FIFO Register (UTF).
 164  */
 165 #define MCFUART_UTF_TXB         0x1f            /* Transmitter data level */
 166 #define MCFUART_UTF_FULL        0x20            /* Transmitter fifo full */
 167 #define MCFUART_UTF_TXS         0xc0            /* Transmitter status */
 168
 169 /*
 170  *      Define bit flags in the Receiver FIFO Register (URF).
 171  */
 172 #define MCFUART_URF_RXB         0x1f            /* Receiver data level */
 173 #define MCFUART_URF_FULL        0x20            /* Receiver fifo full */
 174 #define MCFUART_URF_RXS         0xc0            /* Receiver status */
 175 #endif
 176
 177 #if defined(CONFIG_M54xx)
 178 #define MCFUART_TXFIFOSIZE      512
 179 #elif defined(CONFIG_M5272)
 180 #define MCFUART_TXFIFOSIZE      25
 181 #else
 182 #define MCFUART_TXFIFOSIZE      1
 183 #endif
 184 /****************************************************************************/
 185 #endif  /* mcfuart_h */