drivers/media/video/bt8xx/bt832.h

   1 /* Bt832 CMOS Camera Video Processor (VP)
   2
   3  The Bt832 CMOS Camera Video Processor chip connects a Quartsight CMOS
   4   color digital camera directly to video capture devices via an 8-bit,
   5   4:2:2 YUV or YCrCb video interface.
   6
   7  i2c addresses: 0x88 or 0x8a
   8  */
   9
  10 /* The 64 registers: */
  11
  12 // Input Processor
  13 #define BT832_OFFSET 0
  14 #define BT832_RCOMP     1
  15 #define BT832_G1COMP    2
  16 #define BT832_G2COMP    3
  17 #define BT832_BCOMP     4
  18 // Exposures:
  19 #define BT832_FINEH     5
  20 #define BT832_FINEL     6
  21 #define BT832_COARSEH   7
  22 #define BT832_COARSEL   8
  23 #define BT832_CAMGAIN   9
  24 // Main Processor:
  25 #define BT832_M00       10
  26 #define BT832_M01       11
  27 #define BT832_M02       12
  28 #define BT832_M10       13
  29 #define BT832_M11       14
  30 #define BT832_M12       15
  31 #define BT832_M20       16
  32 #define BT832_M21       17
  33 #define BT832_M22       18
  34 #define BT832_APCOR     19
  35 #define BT832_GAMCOR    20
  36 // Level Accumulator Inputs
  37 #define BT832_VPCONTROL2        21
  38 #define BT832_ZONECODE0 22
  39 #define BT832_ZONECODE1 23
  40 #define BT832_ZONECODE2 24
  41 #define BT832_ZONECODE3 25
  42 // Level Accumulator Outputs:
  43 #define BT832_RACC      26
  44 #define BT832_GACC      27
  45 #define BT832_BACC      28
  46 #define BT832_BLACKACC  29
  47 #define BT832_EXP_AGC   30
  48 #define BT832_LACC0     31
  49 #define BT832_LACC1     32
  50 #define BT832_LACC2     33
  51 #define BT832_LACC3     34
  52 #define BT832_LACC4     35
  53 #define BT832_LACC5     36
  54 #define BT832_LACC6     37
  55 #define BT832_LACC7     38
  56 // System:
  57 #define BT832_VP_CONTROL0       39
  58 #define BT832_VP_CONTROL1       40
  59 #define BT832_THRESH    41
  60 #define BT832_VP_TESTCONTROL0   42
  61 #define BT832_VP_DMCODE 43
  62 #define BT832_ACB_CONFIG        44
  63 #define BT832_ACB_GNBASE        45
  64 #define BT832_ACB_MU    46
  65 #define BT832_CAM_TEST0 47
  66 #define BT832_AEC_CONFIG        48
  67 #define BT832_AEC_TL    49
  68 #define BT832_AEC_TC    50
  69 #define BT832_AEC_TH    51
  70 // Status:
  71 #define BT832_VP_STATUS 52
  72 #define BT832_VP_LINECOUNT      53
  73 #define BT832_CAM_DEVICEL       54 // e.g. 0x19
  74 #define BT832_CAM_DEVICEH       55 // e.g. 0x40  == 0x194 Mask0, 0x194 = 404 decimal (VVL-404 camera)
  75 #define BT832_CAM_STATUS                56
  76  #define BT832_56_CAMERA_PRESENT 0x20
  77 //Camera Setups:
  78 #define BT832_CAM_SETUP0        57
  79 #define BT832_CAM_SETUP1        58
  80 #define BT832_CAM_SETUP2        59
  81 #define BT832_CAM_SETUP3        60
  82 // System:
  83 #define BT832_DEFCOR            61
  84 #define BT832_VP_TESTCONTROL1   62
  85 #define BT832_DEVICE_ID         63
  86 # define BT832_DEVICE_ID__31            0x31 // Bt832 has ID 0x31
  87
  88 /* STMicroelectronivcs VV5404 camera module
  89    i2c: 0x20: sensor address
  90    i2c: 0xa0: eeprom for ccd defect map
  91  */
  92 #define VV5404_device_h         0x00  // 0x19
  93 #define VV5404_device_l         0x01  // 0x40
  94 #define VV5404_status0          0x02
  95 #define VV5404_linecountc       0x03 // current line counter
  96 #define VV5404_linecountl       0x04
  97 #define VV5404_setup0           0x10
  98 #define VV5404_setup1           0x11
  99 #define VV5404_setup2           0x12
 100 #define VV5404_setup4           0x14
 101 #define VV5404_setup5           0x15
 102 #define VV5404_fine_h           0x20  // fine exposure
 103 #define VV5404_fine_l           0x21
 104 #define VV5404_coarse_h         0x22  //coarse exposure
 105 #define VV5404_coarse_l         0x23
 106 #define VV5404_gain             0x24 // ADC pre-amp gain setting
 107 #define VV5404_clk_div          0x25
 108 #define VV5404_cr               0x76 // control register
 109 #define VV5404_as0              0x77 // ADC setup register
 110
 111
 112 // IOCTL
 113 #define BT832_HEXDUMP   _IOR('b',1,int)
 114 #define BT832_REATTACH  _IOR('b',2,int)
 115
 116 /* from BT8x8VXD/capdrv/dialogs.cpp */
 117
 118 /*
 119 typedef enum { SVI, Logitech, Rockwell } CAMERA;
 120
 121 static COMBOBOX_ENTRY gwCameraOptions[] =
 122 {
 123    { SVI,      "Silicon Vision 512N" },
 124    { Logitech, "Logitech VideoMan 1.3"  },
 125    { Rockwell, "Rockwell QuartzSight PCI 1.0"   }
 126 };
 127
 128 // SRAM table values
 129 //===========================================================================
 130 typedef enum { TGB_NTSC624, TGB_NTSC780, TGB_NTSC858, TGB_NTSC392 } TimeGenByte;
 131
 132 BYTE SRAMTable[][ 60 ] =
 133 {
 134    // TGB_NTSC624
 135    {
 136       0x33, // size of table = 51
 137       0x0E, 0xC0, 0x00, 0x00, 0x90, 0x02, 0x03, 0x10, 0x03, 0x06,
 138       0x10, 0x04, 0x12, 0x12, 0x05, 0x02, 0x13, 0x04, 0x19, 0x00,
 139       0x04, 0x39, 0x00, 0x06, 0x59, 0x08, 0x03, 0x85, 0x08, 0x07,
 140       0x03, 0x50, 0x00, 0x91, 0x40, 0x00, 0x11, 0x01, 0x01, 0x4D,
 141       0x0D, 0x02, 0x03, 0x11, 0x01, 0x05, 0x37, 0x00, 0x37, 0x21, 0x00
 142    },
 143    // TGB_NTSC780
 144    {
 145       0x33, // size of table = 51
 146       0x0e, 0xc0, 0x00, 0x00, 0x90, 0xe2, 0x03, 0x10, 0x03, 0x06,
 147       0x10, 0x34, 0x12, 0x12, 0x65, 0x02, 0x13, 0x24, 0x19, 0x00,
 148       0x24, 0x39, 0x00, 0x96, 0x59, 0x08, 0x93, 0x85, 0x08, 0x97,
 149       0x03, 0x50, 0x50, 0xaf, 0x40, 0x30, 0x5f, 0x01, 0xf1, 0x7f,
 150       0x0d, 0xf2, 0x03, 0x11, 0xf1, 0x05, 0x37, 0x30, 0x85, 0x21, 0x50
 151    },
 152    // TGB_NTSC858
 153    {
 154       0x33, // size of table = 51
 155       0x0c, 0xc0, 0x00, 0x00, 0x90, 0xc2, 0x03, 0x10, 0x03, 0x06,
 156       0x10, 0x34, 0x12, 0x12, 0x65, 0x02, 0x13, 0x24, 0x19, 0x00,
 157       0x24, 0x39, 0x00, 0x96, 0x59, 0x08, 0x93, 0x83, 0x08, 0x97,
 158       0x03, 0x50, 0x30, 0xc0, 0x40, 0x30, 0x86, 0x01, 0x01, 0xa6,
 159       0x0d, 0x62, 0x03, 0x11, 0x61, 0x05, 0x37, 0x30, 0xac, 0x21, 0x50
 160    },
 161    // TGB_NTSC392
 162    // This table has been modified to be used for Fusion Rev D
 163    {
 164       0x2A, // size of table = 42
 165       0x06, 0x08, 0x04, 0x0a, 0xc0, 0x00, 0x18, 0x08, 0x03, 0x24,
 166       0x08, 0x07, 0x02, 0x90, 0x02, 0x08, 0x10, 0x04, 0x0c, 0x10,
 167       0x05, 0x2c, 0x11, 0x04, 0x55, 0x48, 0x00, 0x05, 0x50, 0x00,
 168       0xbf, 0x0c, 0x02, 0x2f, 0x3d, 0x00, 0x2f, 0x3f, 0x00, 0xc3,
 169       0x20, 0x00
 170    }
 171 };
 172
 173 //===========================================================================
 174 // This is the structure of the camera specifications
 175 //===========================================================================
 176 typedef struct tag_cameraSpec
 177 {
 178    SignalFormat signal;       // which digital signal format the camera has
 179    VideoFormat  vidFormat;    // video standard
 180    SyncVideoRef syncRef;      // which sync video reference is used
 181    State        syncOutput;   // enable sync output for sync video input?
 182    DecInputClk  iClk;         // which input clock is used
 183    TimeGenByte  tgb;          // which timing generator byte does the camera use
 184    int          HReset;       // select 64, 48, 32, or 16 CLKx1 for HReset
 185    PLLFreq      pllFreq;      // what synthesized frequency to set PLL to
 186    VSIZEPARMS   vSize;        // video size the camera produces
 187    int          lineCount;    // expected total number of half-line per frame - 1
 188    BOOL         interlace;    // interlace signal?
 189 } CameraSpec;
 190
 191 //===========================================================================
 192 // <UPDATE REQUIRED>
 193 // Camera specifications database. Update this table whenever camera spec
 194 // has been changed or added/deleted supported camera models
 195 //===========================================================================
 196 static CameraSpec dbCameraSpec[ N_CAMERAOPTIONS ] =
 197 {  // Silicon Vision 512N
 198    { Signal_CCIR656, VFormat_NTSC, VRef_alignedCb, Off, DecClk_GPCLK, TGB_NTSC624, 64, KHz19636,
 199       // Clkx1_HACTIVE, Clkx1_HDELAY, VActive, VDelay, linesPerField; lineCount, Interlace
 200    {         512,           0x64,       480,    0x13,      240 },         0,       TRUE
 201    },
 202    // Logitech VideoMan 1.3
 203    { Signal_CCIR656, VFormat_NTSC, VRef_alignedCb, Off, DecClk_GPCLK, TGB_NTSC780, 64, KHz24545,
 204       // Clkx1_HACTIVE, Clkx1_HDELAY, VActive, VDelay, linesPerField; lineCount, Interlace
 205       {      640,           0x80,       480,    0x1A,      240 },         0,       TRUE
 206    },
 207    // Rockwell QuartzSight
 208    // Note: Fusion Rev D (rev ID 0x02) and later supports 16 pixels for HReset which is preferable.
 209    //       Use 32 for earlier version of hardware. Clkx1_HDELAY also changed from 0x27 to 0x20.
 210    { Signal_CCIR656, VFormat_NTSC, VRef_alignedCb, Off, DecClk_GPCLK, TGB_NTSC392, 16, KHz28636,
 211       // Clkx1_HACTIVE, Clkx1_HDELAY, VActive, VDelay, linesPerField; lineCount, Interlace
 212       {      352,           0x20,       576,    0x08,      288 },       607,       FALSE
 213    }
 214 };
 215 */
 216
 217 /*
 218 The corresponding APIs required to be invoked are:
 219 SetConnector( ConCamera, TRUE/FALSE );
 220 SetSignalFormat( spec.signal );
 221 SetVideoFormat( spec.vidFormat );
 222 SetSyncVideoRef( spec.syncRef );
 223 SetEnableSyncOutput( spec.syncOutput );
 224 SetTimGenByte( SRAMTable[ spec.tgb ], SRAMTableSize[ spec.tgb ] );
 225 SetHReset( spec.HReset );
 226 SetPLL( spec.pllFreq );
 227 SetDecInputClock( spec.iClk );
 228 SetVideoInfo( spec.vSize );
 229 SetTotalLineCount( spec.lineCount );
 230 SetInterlaceMode( spec.interlace );
 231 */
 232
 233 /* from web:
 234  Video Sampling
 235 Digital video is a sampled form of analog video. The most common sampling schemes in use today are:
 236                   Pixel Clock   Horiz    Horiz    Vert
 237                    Rate         Total    Active
 238 NTSC square pixel  12.27 MHz    780      640      525
 239 NTSC CCIR-601      13.5  MHz    858      720      525
 240 NTSC 4FSc          14.32 MHz    910      768      525
 241 PAL  square pixel  14.75 MHz    944      768      625
 242 PAL  CCIR-601      13.5  MHz    864      720      625
 243 PAL  4FSc          17.72 MHz   1135      948      625
 244
 245 For the CCIR-601 standards, the sampling is based on a static orthogonal sampling grid. The luminance component (Y) is sampled at 13.5 MHz, while the two color difference signals, Cr and Cb are sampled at half that, or 6.75 MHz. The Cr and Cb samples are colocated with alternate Y samples, and they are taken at the same position on each line, such that one sample is coincident with the 50% point of the falling edge of analog sync. The samples are coded to either 8 or 10 bits per component.
 246 */
 247
 248 /* from DScaler:*/
 249 /*
 250 //===========================================================================
 251 // CCIR656 Digital Input Support: The tables were taken from DScaler proyect
 252 //
 253 // 13 Dec 2000 - Michael Eskin, Conexant Systems - Initial version
 254 //
 255
 256 //===========================================================================
 257 // Timing generator SRAM table values for CCIR601 720x480 NTSC
 258 //===========================================================================
 259 // For NTSC CCIR656
 260 BYTE BtCard::SRAMTable_NTSC[] =
 261 {
 262     // SRAM Timing Table for NTSC
 263     0x0c, 0xc0, 0x00,
 264     0x00, 0x90, 0xc2,
 265     0x03, 0x10, 0x03,
 266     0x06, 0x10, 0x34,
 267     0x12, 0x12, 0x65,
 268     0x02, 0x13, 0x24,
 269     0x19, 0x00, 0x24,
 270     0x39, 0x00, 0x96,
 271     0x59, 0x08, 0x93,
 272     0x83, 0x08, 0x97,
 273     0x03, 0x50, 0x30,
 274     0xc0, 0x40, 0x30,
 275     0x86, 0x01, 0x01,
 276     0xa6, 0x0d, 0x62,
 277     0x03, 0x11, 0x61,
 278     0x05, 0x37, 0x30,
 279     0xac, 0x21, 0x50
 280 };
 281
 282 //===========================================================================
 283 // Timing generator SRAM table values for CCIR601 720x576 NTSC
 284 //===========================================================================
 285 // For PAL CCIR656
 286 BYTE BtCard::SRAMTable_PAL[] =
 287 {
 288     // SRAM Timing Table for PAL
 289     0x36, 0x11, 0x01,
 290     0x00, 0x90, 0x02,
 291     0x05, 0x10, 0x04,
 292     0x16, 0x14, 0x05,
 293     0x11, 0x00, 0x04,
 294     0x12, 0xc0, 0x00,
 295     0x31, 0x00, 0x06,
 296     0x51, 0x08, 0x03,
 297     0x89, 0x08, 0x07,
 298     0xc0, 0x44, 0x00,
 299     0x81, 0x01, 0x01,
 300     0xa9, 0x0d, 0x02,
 301     0x02, 0x50, 0x03,
 302     0x37, 0x3d, 0x00,
 303     0xaf, 0x21, 0x00,
 304 };
 305 */