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Merge tag 'extcon-next-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / clk / clk-aspeed.c
blob42b4df6ba249f2ec3b7382cfb2a732358473affb
1 // SPDX-License-Identifier: GPL-2.0+
2
3 #define pr_fmt(fmt) "clk-aspeed: " fmt
4
5 #include <linux/clk-provider.h>
6 #include <linux/mfd/syscon.h>
7 #include <linux/of_address.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <linux/reset-controller.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14
15 #include <dt-bindings/clock/aspeed-clock.h>
16
17 #define ASPEED_NUM_CLKS 36
18
19 #define ASPEED_RESET2_OFFSET 32
20
21 #define ASPEED_RESET_CTRL 0x04
22 #define ASPEED_CLK_SELECTION 0x08
23 #define ASPEED_CLK_STOP_CTRL 0x0c
24 #define ASPEED_MPLL_PARAM 0x20
25 #define ASPEED_HPLL_PARAM 0x24
26 #define AST2500_HPLL_BYPASS_EN BIT(20)
27 #define AST2400_HPLL_PROGRAMMED BIT(18)
28 #define AST2400_HPLL_BYPASS_EN BIT(17)
29 #define ASPEED_MISC_CTRL 0x2c
30 #define UART_DIV13_EN BIT(12)
31 #define ASPEED_STRAP 0x70
32 #define CLKIN_25MHZ_EN BIT(23)
33 #define AST2400_CLK_SOURCE_SEL BIT(18)
34 #define ASPEED_CLK_SELECTION_2 0xd8
35 #define ASPEED_RESET_CTRL2 0xd4
36
37 /* Globally visible clocks */
38 static DEFINE_SPINLOCK(aspeed_clk_lock);
39
40 /* Keeps track of all clocks */
41 static struct clk_hw_onecell_data *aspeed_clk_data;
42
43 static void __iomem *scu_base;
44
45 /**
46 * struct aspeed_gate_data - Aspeed gated clocks
47 * @clock_idx: bit used to gate this clock in the clock register
48 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
49 * reset is required when enabling the clock
50 * @name: the clock name
51 * @parent_name: the name of the parent clock
52 * @flags: standard clock framework flags
53 */
54 struct aspeed_gate_data {
55 u8 clock_idx;
56 s8 reset_idx;
57 const char *name;
58 const char *parent_name;
59 unsigned long flags;
60 };
61
62 /**
63 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
64 * @hw: handle between common and hardware-specific interfaces
65 * @reg: register controlling gate
66 * @clock_idx: bit used to gate this clock in the clock register
67 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
68 * reset is required when enabling the clock
69 * @flags: hardware-specific flags
70 * @lock: register lock
71 *
72 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
73 * This modified version of clk_gate allows an optional reset bit to be
74 * specified.
75 */
76 struct aspeed_clk_gate {
77 struct clk_hw hw;
78 struct regmap *map;
79 u8 clock_idx;
80 s8 reset_idx;
81 u8 flags;
82 spinlock_t *lock;
83 };
84
85 #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
86
87 /* TODO: ask Aspeed about the actual parent data */
88 static const struct aspeed_gate_data aspeed_gates[] = {
89 /* clk rst name parent flags */
90 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
91 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
92 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
93 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
94 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
95 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
96 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
97 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
98 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
99 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
100 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
101 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
102 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
103 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
104 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
105 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
106 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
107 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
108 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
109 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
110 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
111 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
112 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
113 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
114 };
115
116 static const char * const eclk_parent_names[] = {
117 "mpll",
118 "hpll",
119 "dpll",
120 };
121
122 static const struct clk_div_table ast2500_eclk_div_table[] = {
123 { 0x0, 2 },
124 { 0x1, 2 },
125 { 0x2, 3 },
126 { 0x3, 4 },
127 { 0x4, 5 },
128 { 0x5, 6 },
129 { 0x6, 7 },
130 { 0x7, 8 },
131 { 0 }
132 };
133
134 static const struct clk_div_table ast2500_mac_div_table[] = {
135 { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
136 { 0x1, 4 },
137 { 0x2, 6 },
138 { 0x3, 8 },
139 { 0x4, 10 },
140 { 0x5, 12 },
141 { 0x6, 14 },
142 { 0x7, 16 },
143 { 0 }
144 };
145
146 static const struct clk_div_table ast2400_div_table[] = {
147 { 0x0, 2 },
148 { 0x1, 4 },
149 { 0x2, 6 },
150 { 0x3, 8 },
151 { 0x4, 10 },
152 { 0x5, 12 },
153 { 0x6, 14 },
154 { 0x7, 16 },
155 { 0 }
156 };
157
158 static const struct clk_div_table ast2500_div_table[] = {
159 { 0x0, 4 },
160 { 0x1, 8 },
161 { 0x2, 12 },
162 { 0x3, 16 },
163 { 0x4, 20 },
164 { 0x5, 24 },
165 { 0x6, 28 },
166 { 0x7, 32 },
167 { 0 }
168 };
169
170 static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
171 {
172 unsigned int mult, div;
173
174 if (val & AST2400_HPLL_BYPASS_EN) {
175 /* Pass through mode */
176 mult = div = 1;
177 } else {
178 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
179 u32 n = (val >> 5) & 0x3f;
180 u32 od = (val >> 4) & 0x1;
181 u32 d = val & 0xf;
182
183 mult = (2 - od) * (n + 2);
184 div = d + 1;
185 }
186 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
187 mult, div);
188 };
189
190 static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
191 {
192 unsigned int mult, div;
193
194 if (val & AST2500_HPLL_BYPASS_EN) {
195 /* Pass through mode */
196 mult = div = 1;
197 } else {
198 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */
199 u32 p = (val >> 13) & 0x3f;
200 u32 m = (val >> 5) & 0xff;
201 u32 n = val & 0x1f;
202
203 mult = (m + 1) / (n + 1);
204 div = p + 1;
205 }
206
207 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
208 mult, div);
209 }
210
211 struct aspeed_clk_soc_data {
212 const struct clk_div_table *div_table;
213 const struct clk_div_table *eclk_div_table;
214 const struct clk_div_table *mac_div_table;
215 struct clk_hw *(*calc_pll)(const char *name, u32 val);
216 };
217
218 static const struct aspeed_clk_soc_data ast2500_data = {
219 .div_table = ast2500_div_table,
220 .eclk_div_table = ast2500_eclk_div_table,
221 .mac_div_table = ast2500_mac_div_table,
222 .calc_pll = aspeed_ast2500_calc_pll,
223 };
224
225 static const struct aspeed_clk_soc_data ast2400_data = {
226 .div_table = ast2400_div_table,
227 .eclk_div_table = ast2400_div_table,
228 .mac_div_table = ast2400_div_table,
229 .calc_pll = aspeed_ast2400_calc_pll,
230 };
231
232 static int aspeed_clk_is_enabled(struct clk_hw *hw)
233 {
234 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
235 u32 clk = BIT(gate->clock_idx);
236 u32 rst = BIT(gate->reset_idx);
237 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
238 u32 reg;
239
240 /*
241 * If the IP is in reset, treat the clock as not enabled,
242 * this happens with some clocks such as the USB one when
243 * coming from cold reset. Without this, aspeed_clk_enable()
244 * will fail to lift the reset.
245 */
246 if (gate->reset_idx >= 0) {
247 regmap_read(gate->map, ASPEED_RESET_CTRL, &reg);
248 if (reg & rst)
249 return 0;
250 }
251
252 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg);
253
254 return ((reg & clk) == enval) ? 1 : 0;
255 }
256
257 static int aspeed_clk_enable(struct clk_hw *hw)
258 {
259 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
260 unsigned long flags;
261 u32 clk = BIT(gate->clock_idx);
262 u32 rst = BIT(gate->reset_idx);
263 u32 enval;
264
265 spin_lock_irqsave(gate->lock, flags);
266
267 if (aspeed_clk_is_enabled(hw)) {
268 spin_unlock_irqrestore(gate->lock, flags);
269 return 0;
270 }
271
272 if (gate->reset_idx >= 0) {
273 /* Put IP in reset */
274 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
275
276 /* Delay 100us */
277 udelay(100);
278 }
279
280 /* Enable clock */
281 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
282 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
283
284 if (gate->reset_idx >= 0) {
285 /* A delay of 10ms is specified by the ASPEED docs */
286 mdelay(10);
287
288 /* Take IP out of reset */
289 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
290 }
291
292 spin_unlock_irqrestore(gate->lock, flags);
293
294 return 0;
295 }
296
297 static void aspeed_clk_disable(struct clk_hw *hw)
298 {
299 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
300 unsigned long flags;
301 u32 clk = BIT(gate->clock_idx);
302 u32 enval;
303
304 spin_lock_irqsave(gate->lock, flags);
305
306 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0;
307 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
308
309 spin_unlock_irqrestore(gate->lock, flags);
310 }
311
312 static const struct clk_ops aspeed_clk_gate_ops = {
313 .enable = aspeed_clk_enable,
314 .disable = aspeed_clk_disable,
315 .is_enabled = aspeed_clk_is_enabled,
316 };
317
318 /**
319 * struct aspeed_reset - Aspeed reset controller
320 * @map: regmap to access the containing system controller
321 * @rcdev: reset controller device
322 */
323 struct aspeed_reset {
324 struct regmap *map;
325 struct reset_controller_dev rcdev;
326 };
327
328 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
329
330 static const u8 aspeed_resets[] = {
331 /* SCU04 resets */
332 [ASPEED_RESET_XDMA] = 25,
333 [ASPEED_RESET_MCTP] = 24,
334 [ASPEED_RESET_ADC] = 23,
335 [ASPEED_RESET_JTAG_MASTER] = 22,
336 [ASPEED_RESET_MIC] = 18,
337 [ASPEED_RESET_PWM] = 9,
338 [ASPEED_RESET_PECI] = 10,
339 [ASPEED_RESET_I2C] = 2,
340 [ASPEED_RESET_AHB] = 1,
341
342 /*
343 * SCUD4 resets start at an offset to separate them from
344 * the SCU04 resets.
345 */
346 [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5,
347 };
348
349 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
350 unsigned long id)
351 {
352 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
353 u32 reg = ASPEED_RESET_CTRL;
354 u32 bit = aspeed_resets[id];
355
356 if (bit >= ASPEED_RESET2_OFFSET) {
357 bit -= ASPEED_RESET2_OFFSET;
358 reg = ASPEED_RESET_CTRL2;
359 }
360
361 return regmap_update_bits(ar->map, reg, BIT(bit), 0);
362 }
363
364 static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
365 unsigned long id)
366 {
367 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
368 u32 reg = ASPEED_RESET_CTRL;
369 u32 bit = aspeed_resets[id];
370
371 if (bit >= ASPEED_RESET2_OFFSET) {
372 bit -= ASPEED_RESET2_OFFSET;
373 reg = ASPEED_RESET_CTRL2;
374 }
375
376 return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
377 }
378
379 static int aspeed_reset_status(struct reset_controller_dev *rcdev,
380 unsigned long id)
381 {
382 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
383 u32 reg = ASPEED_RESET_CTRL;
384 u32 bit = aspeed_resets[id];
385 int ret, val;
386
387 if (bit >= ASPEED_RESET2_OFFSET) {
388 bit -= ASPEED_RESET2_OFFSET;
389 reg = ASPEED_RESET_CTRL2;
390 }
391
392 ret = regmap_read(ar->map, reg, &val);
393 if (ret)
394 return ret;
395
396 return !!(val & BIT(bit));
397 }
398
399 static const struct reset_control_ops aspeed_reset_ops = {
400 .assert = aspeed_reset_assert,
401 .deassert = aspeed_reset_deassert,
402 .status = aspeed_reset_status,
403 };
404
405 static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,
406 const char *name, const char *parent_name, unsigned long flags,
407 struct regmap *map, u8 clock_idx, u8 reset_idx,
408 u8 clk_gate_flags, spinlock_t *lock)
409 {
410 struct aspeed_clk_gate *gate;
411 struct clk_init_data init;
412 struct clk_hw *hw;
413 int ret;
414
415 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
416 if (!gate)
417 return ERR_PTR(-ENOMEM);
418
419 init.name = name;
420 init.ops = &aspeed_clk_gate_ops;
421 init.flags = flags;
422 init.parent_names = parent_name ? &parent_name : NULL;
423 init.num_parents = parent_name ? 1 : 0;
424
425 gate->map = map;
426 gate->clock_idx = clock_idx;
427 gate->reset_idx = reset_idx;
428 gate->flags = clk_gate_flags;
429 gate->lock = lock;
430 gate->hw.init = &init;
431
432 hw = &gate->hw;
433 ret = clk_hw_register(dev, hw);
434 if (ret) {
435 kfree(gate);
436 hw = ERR_PTR(ret);
437 }
438
439 return hw;
440 }
441
442 static int aspeed_clk_probe(struct platform_device *pdev)
443 {
444 const struct aspeed_clk_soc_data *soc_data;
445 struct device *dev = &pdev->dev;
446 struct aspeed_reset *ar;
447 struct regmap *map;
448 struct clk_hw *hw;
449 u32 val, rate;
450 int i, ret;
451
452 map = syscon_node_to_regmap(dev->of_node);
453 if (IS_ERR(map)) {
454 dev_err(dev, "no syscon regmap\n");
455 return PTR_ERR(map);
456 }
457
458 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
459 if (!ar)
460 return -ENOMEM;
461
462 ar->map = map;
463 ar->rcdev.owner = THIS_MODULE;
464 ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);
465 ar->rcdev.ops = &aspeed_reset_ops;
466 ar->rcdev.of_node = dev->of_node;
467
468 ret = devm_reset_controller_register(dev, &ar->rcdev);
469 if (ret) {
470 dev_err(dev, "could not register reset controller\n");
471 return ret;
472 }
473
474 /* SoC generations share common layouts but have different divisors */
475 soc_data = of_device_get_match_data(dev);
476 if (!soc_data) {
477 dev_err(dev, "no match data for platform\n");
478 return -EINVAL;
479 }
480
481 /* UART clock div13 setting */
482 regmap_read(map, ASPEED_MISC_CTRL, &val);
483 if (val & UART_DIV13_EN)
484 rate = 24000000 / 13;
485 else
486 rate = 24000000;
487 /* TODO: Find the parent data for the uart clock */
488 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
489 if (IS_ERR(hw))
490 return PTR_ERR(hw);
491 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;
492
493 /*
494 * Memory controller (M-PLL) PLL. This clock is configured by the
495 * bootloader, and is exposed to Linux as a read-only clock rate.
496 */
497 regmap_read(map, ASPEED_MPLL_PARAM, &val);
498 hw = soc_data->calc_pll("mpll", val);
499 if (IS_ERR(hw))
500 return PTR_ERR(hw);
501 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
502
503 /* SD/SDIO clock divider (TODO: There's a gate too) */
504 hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0,
505 scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
506 soc_data->div_table,
507 &aspeed_clk_lock);
508 if (IS_ERR(hw))
509 return PTR_ERR(hw);
510 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;
511
512 /* MAC AHB bus clock divider */
513 hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
514 scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
515 soc_data->mac_div_table,
516 &aspeed_clk_lock);
517 if (IS_ERR(hw))
518 return PTR_ERR(hw);
519 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
520
521 /* LPC Host (LHCLK) clock divider */
522 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
523 scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
524 soc_data->div_table,
525 &aspeed_clk_lock);
526 if (IS_ERR(hw))
527 return PTR_ERR(hw);
528 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
529
530 /* P-Bus (BCLK) clock divider */
531 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
532 scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
533 soc_data->div_table,
534 &aspeed_clk_lock);
535 if (IS_ERR(hw))
536 return PTR_ERR(hw);
537 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
538
539 /* Fixed 24MHz clock */
540 hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
541 0, 24000000);
542 if (IS_ERR(hw))
543 return PTR_ERR(hw);
544 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
545
546 hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names,
547 ARRAY_SIZE(eclk_parent_names), 0,
548 scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,
549 &aspeed_clk_lock);
550 if (IS_ERR(hw))
551 return PTR_ERR(hw);
552 aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;
553
554 hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0,
555 scu_base + ASPEED_CLK_SELECTION, 28,
556 3, 0, soc_data->eclk_div_table,
557 &aspeed_clk_lock);
558 if (IS_ERR(hw))
559 return PTR_ERR(hw);
560 aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;
561
562 /*
563 * TODO: There are a number of clocks that not included in this driver
564 * as more information is required:
565 * D2-PLL
566 * D-PLL
567 * YCLK
568 * RGMII
569 * RMII
570 * UART[1..5] clock source mux
571 */
572
573 for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
574 const struct aspeed_gate_data *gd = &aspeed_gates[i];
575 u32 gate_flags;
576
577 /* Special case: the USB port 1 clock (bit 14) is always
578 * working the opposite way from the other ones.
579 */
580 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
581 hw = aspeed_clk_hw_register_gate(dev,
582 gd->name,
583 gd->parent_name,
584 gd->flags,
585 map,
586 gd->clock_idx,
587 gd->reset_idx,
588 gate_flags,
589 &aspeed_clk_lock);
590 if (IS_ERR(hw))
591 return PTR_ERR(hw);
592 aspeed_clk_data->hws[i] = hw;
593 }
594
595 return 0;
596 };
597
598 static const struct of_device_id aspeed_clk_dt_ids[] = {
599 { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
600 { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
601 { }
602 };
603
604 static struct platform_driver aspeed_clk_driver = {
605 .probe = aspeed_clk_probe,
606 .driver = {
607 .name = "aspeed-clk",
608 .of_match_table = aspeed_clk_dt_ids,
609 .suppress_bind_attrs = true,
610 },
611 };
612 builtin_platform_driver(aspeed_clk_driver);
613
614 static void __init aspeed_ast2400_cc(struct regmap *map)
615 {
616 struct clk_hw *hw;
617 u32 val, div, clkin, hpll;
618 const u16 hpll_rates[][4] = {
619 {384, 360, 336, 408},
620 {400, 375, 350, 425},
621 };
622 int rate;
623
624 /*
625 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
626 * strapping
627 */
628 regmap_read(map, ASPEED_STRAP, &val);
629 rate = (val >> 8) & 3;
630 if (val & CLKIN_25MHZ_EN) {
631 clkin = 25000000;
632 hpll = hpll_rates[1][rate];
633 } else if (val & AST2400_CLK_SOURCE_SEL) {
634 clkin = 48000000;
635 hpll = hpll_rates[0][rate];
636 } else {
637 clkin = 24000000;
638 hpll = hpll_rates[0][rate];
639 }
640 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, clkin);
641 pr_debug("clkin @%u MHz\n", clkin / 1000000);
642
643 /*
644 * High-speed PLL clock derived from the crystal. This the CPU clock,
645 * and we assume that it is enabled. It can be configured through the
646 * HPLL_PARAM register, or set to a specified frequency by strapping.
647 */
648 regmap_read(map, ASPEED_HPLL_PARAM, &val);
649 if (val & AST2400_HPLL_PROGRAMMED)
650 hw = aspeed_ast2400_calc_pll("hpll", val);
651 else
652 hw = clk_hw_register_fixed_rate(NULL, "hpll", "clkin", 0,
653 hpll * 1000000);
654
655 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw;
656
657 /*
658 * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
659 * 00: Select CPU:AHB = 1:1
660 * 01: Select CPU:AHB = 2:1
661 * 10: Select CPU:AHB = 4:1
662 * 11: Select CPU:AHB = 3:1
663 */
664 regmap_read(map, ASPEED_STRAP, &val);
665 val = (val >> 10) & 0x3;
666 div = val + 1;
667 if (div == 3)
668 div = 4;
669 else if (div == 4)
670 div = 3;
671 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
672 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
673
674 /* APB clock clock selection register SCU08 (aka PCLK) */
675 hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
676 scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
677 ast2400_div_table,
678 &aspeed_clk_lock);
679 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
680 }
681
682 static void __init aspeed_ast2500_cc(struct regmap *map)
683 {
684 struct clk_hw *hw;
685 u32 val, freq, div;
686
687 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
688 regmap_read(map, ASPEED_STRAP, &val);
689 if (val & CLKIN_25MHZ_EN)
690 freq = 25000000;
691 else
692 freq = 24000000;
693 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
694 pr_debug("clkin @%u MHz\n", freq / 1000000);
695
696 /*
697 * High-speed PLL clock derived from the crystal. This the CPU clock,
698 * and we assume that it is enabled
699 */
700 regmap_read(map, ASPEED_HPLL_PARAM, &val);
701 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);
702
703 /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
704 regmap_read(map, ASPEED_STRAP, &val);
705 val = (val >> 9) & 0x7;
706 WARN(val == 0, "strapping is zero: cannot determine ahb clock");
707 div = 2 * (val + 1);
708 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
709 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
710
711 /* APB clock clock selection register SCU08 (aka PCLK) */
712 regmap_read(map, ASPEED_CLK_SELECTION, &val);
713 val = (val >> 23) & 0x7;
714 div = 4 * (val + 1);
715 hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
716 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
717 };
718
719 static void __init aspeed_cc_init(struct device_node *np)
720 {
721 struct regmap *map;
722 u32 val;
723 int ret;
724 int i;
725
726 scu_base = of_iomap(np, 0);
727 if (!scu_base)
728 return;
729
730 aspeed_clk_data = kzalloc(struct_size(aspeed_clk_data, hws,
731 ASPEED_NUM_CLKS),
732 GFP_KERNEL);
733 if (!aspeed_clk_data)
734 return;
735
736 /*
737 * This way all clocks fetched before the platform device probes,
738 * except those we assign here for early use, will be deferred.
739 */
740 for (i = 0; i < ASPEED_NUM_CLKS; i++)
741 aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
742
743 map = syscon_node_to_regmap(np);
744 if (IS_ERR(map)) {
745 pr_err("no syscon regmap\n");
746 return;
747 }
748 /*
749 * We check that the regmap works on this very first access,
750 * but as this is an MMIO-backed regmap, subsequent regmap
751 * access is not going to fail and we skip error checks from
752 * this point.
753 */
754 ret = regmap_read(map, ASPEED_STRAP, &val);
755 if (ret) {
756 pr_err("failed to read strapping register\n");
757 return;
758 }
759
760 if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
761 aspeed_ast2400_cc(map);
762 else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
763 aspeed_ast2500_cc(map);
764 else
765 pr_err("unknown platform, failed to add clocks\n");
766
767 aspeed_clk_data->num = ASPEED_NUM_CLKS;
768 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
769 if (ret)
770 pr_err("failed to add DT provider: %d\n", ret);
771 };
772 CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
773 CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
Linux with added FPC-III support