drivers/pci/controller/pcie-mobiveil.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCIe host controller driver for Mobiveil PCIe Host controller
   4  *
   5  * Copyright (c) 2018 Mobiveil Inc.
   6  * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/irqchip/chained_irq.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/msi.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_pci.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25
  26 #include "../pci.h"
  27
  28 /* register offsets and bit positions */
  29
  30 /*
  31  * translation tables are grouped into windows, each window registers are
  32  * grouped into blocks of 4 or 16 registers each
  33  */
  34 #define PAB_REG_BLOCK_SIZE              16
  35 #define PAB_EXT_REG_BLOCK_SIZE          4
  36
  37 #define PAB_REG_ADDR(offset, win)       \
  38         (offset + (win * PAB_REG_BLOCK_SIZE))
  39 #define PAB_EXT_REG_ADDR(offset, win)   \
  40         (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
  41
  42 #define LTSSM_STATUS                    0x0404
  43 #define  LTSSM_STATUS_L0_MASK           0x3f
  44 #define  LTSSM_STATUS_L0                0x2d
  45
  46 #define PAB_CTRL                        0x0808
  47 #define  AMBA_PIO_ENABLE_SHIFT          0
  48 #define  PEX_PIO_ENABLE_SHIFT           1
  49 #define  PAGE_SEL_SHIFT                 13
  50 #define  PAGE_SEL_MASK                  0x3f
  51 #define  PAGE_LO_MASK                   0x3ff
  52 #define  PAGE_SEL_OFFSET_SHIFT          10
  53
  54 #define PAB_AXI_PIO_CTRL                0x0840
  55 #define  APIO_EN_MASK                   0xf
  56
  57 #define PAB_PEX_PIO_CTRL                0x08c0
  58 #define  PIO_ENABLE_SHIFT               0
  59
  60 #define PAB_INTP_AMBA_MISC_ENB          0x0b0c
  61 #define PAB_INTP_AMBA_MISC_STAT         0x0b1c
  62 #define  PAB_INTP_INTX_MASK             0x01e0
  63 #define  PAB_INTP_MSI_MASK              0x8
  64
  65 #define PAB_AXI_AMAP_CTRL(win)          PAB_REG_ADDR(0x0ba0, win)
  66 #define  WIN_ENABLE_SHIFT               0
  67 #define  WIN_TYPE_SHIFT                 1
  68 #define  WIN_TYPE_MASK                  0x3
  69 #define  WIN_SIZE_MASK                  0xfffffc00
  70
  71 #define PAB_EXT_AXI_AMAP_SIZE(win)      PAB_EXT_REG_ADDR(0xbaf0, win)
  72
  73 #define PAB_EXT_AXI_AMAP_AXI_WIN(win)   PAB_EXT_REG_ADDR(0x80a0, win)
  74 #define PAB_AXI_AMAP_AXI_WIN(win)       PAB_REG_ADDR(0x0ba4, win)
  75 #define  AXI_WINDOW_ALIGN_MASK          3
  76
  77 #define PAB_AXI_AMAP_PEX_WIN_L(win)     PAB_REG_ADDR(0x0ba8, win)
  78 #define  PAB_BUS_SHIFT                  24
  79 #define  PAB_DEVICE_SHIFT               19
  80 #define  PAB_FUNCTION_SHIFT             16
  81
  82 #define PAB_AXI_AMAP_PEX_WIN_H(win)     PAB_REG_ADDR(0x0bac, win)
  83 #define PAB_INTP_AXI_PIO_CLASS          0x474
  84
  85 #define PAB_PEX_AMAP_CTRL(win)          PAB_REG_ADDR(0x4ba0, win)
  86 #define  AMAP_CTRL_EN_SHIFT             0
  87 #define  AMAP_CTRL_TYPE_SHIFT           1
  88 #define  AMAP_CTRL_TYPE_MASK            3
  89
  90 #define PAB_EXT_PEX_AMAP_SIZEN(win)     PAB_EXT_REG_ADDR(0xbef0, win)
  91 #define PAB_PEX_AMAP_AXI_WIN(win)       PAB_REG_ADDR(0x4ba4, win)
  92 #define PAB_PEX_AMAP_PEX_WIN_L(win)     PAB_REG_ADDR(0x4ba8, win)
  93 #define PAB_PEX_AMAP_PEX_WIN_H(win)     PAB_REG_ADDR(0x4bac, win)
  94
  95 /* starting offset of INTX bits in status register */
  96 #define PAB_INTX_START                  5
  97
  98 /* supported number of MSI interrupts */
  99 #define PCI_NUM_MSI                     16
 100
 101 /* MSI registers */
 102 #define MSI_BASE_LO_OFFSET              0x04
 103 #define MSI_BASE_HI_OFFSET              0x08
 104 #define MSI_SIZE_OFFSET                 0x0c
 105 #define MSI_ENABLE_OFFSET               0x14
 106 #define MSI_STATUS_OFFSET               0x18
 107 #define MSI_DATA_OFFSET                 0x20
 108 #define MSI_ADDR_L_OFFSET               0x24
 109 #define MSI_ADDR_H_OFFSET               0x28
 110
 111 /* outbound and inbound window definitions */
 112 #define WIN_NUM_0                       0
 113 #define WIN_NUM_1                       1
 114 #define CFG_WINDOW_TYPE                 0
 115 #define IO_WINDOW_TYPE                  1
 116 #define MEM_WINDOW_TYPE                 2
 117 #define IB_WIN_SIZE                     ((u64)256 * 1024 * 1024 * 1024)
 118 #define MAX_PIO_WINDOWS                 8
 119
 120 /* Parameters for the waiting for link up routine */
 121 #define LINK_WAIT_MAX_RETRIES           10
 122 #define LINK_WAIT_MIN                   90000
 123 #define LINK_WAIT_MAX                   100000
 124
 125 #define PAGED_ADDR_BNDRY                0xc00
 126 #define OFFSET_TO_PAGE_ADDR(off)        \
 127         ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
 128 #define OFFSET_TO_PAGE_IDX(off)         \
 129         ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
 130
 131 struct mobiveil_msi {                   /* MSI information */
 132         struct mutex lock;              /* protect bitmap variable */
 133         struct irq_domain *msi_domain;
 134         struct irq_domain *dev_domain;
 135         phys_addr_t msi_pages_phys;
 136         int num_of_vectors;
 137         DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
 138 };
 139
 140 struct mobiveil_pcie {
 141         struct platform_device *pdev;
 142         struct list_head resources;
 143         void __iomem *config_axi_slave_base;    /* endpoint config base */
 144         void __iomem *csr_axi_slave_base;       /* root port config base */
 145         void __iomem *apb_csr_base;     /* MSI register base */
 146         phys_addr_t pcie_reg_base;      /* Physical PCIe Controller Base */
 147         struct irq_domain *intx_domain;
 148         raw_spinlock_t intx_mask_lock;
 149         int irq;
 150         int apio_wins;
 151         int ppio_wins;
 152         int ob_wins_configured;         /* configured outbound windows */
 153         int ib_wins_configured;         /* configured inbound windows */
 154         struct resource *ob_io_res;
 155         char root_bus_nr;
 156         struct mobiveil_msi msi;
 157 };
 158
 159 /*
 160  * mobiveil_pcie_sel_page - routine to access paged register
 161  *
 162  * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
 163  * for this scheme to work extracted higher 6 bits of the offset will be
 164  * written to pg_sel field of PAB_CTRL register and rest of the lower 10
 165  * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
 166  */
 167 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
 168 {
 169         u32 val;
 170
 171         val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
 172         val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
 173         val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
 174
 175         writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
 176 }
 177
 178 static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
 179 {
 180         if (off < PAGED_ADDR_BNDRY) {
 181                 /* For directly accessed registers, clear the pg_sel field */
 182                 mobiveil_pcie_sel_page(pcie, 0);
 183                 return pcie->csr_axi_slave_base + off;
 184         }
 185
 186         mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
 187         return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
 188 }
 189
 190 static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
 191 {
 192         if ((uintptr_t)addr & (size - 1)) {
 193                 *val = 0;
 194                 return PCIBIOS_BAD_REGISTER_NUMBER;
 195         }
 196
 197         switch (size) {
 198         case 4:
 199                 *val = readl(addr);
 200                 break;
 201         case 2:
 202                 *val = readw(addr);
 203                 break;
 204         case 1:
 205                 *val = readb(addr);
 206                 break;
 207         default:
 208                 *val = 0;
 209                 return PCIBIOS_BAD_REGISTER_NUMBER;
 210         }
 211
 212         return PCIBIOS_SUCCESSFUL;
 213 }
 214
 215 static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
 216 {
 217         if ((uintptr_t)addr & (size - 1))
 218                 return PCIBIOS_BAD_REGISTER_NUMBER;
 219
 220         switch (size) {
 221         case 4:
 222                 writel(val, addr);
 223                 break;
 224         case 2:
 225                 writew(val, addr);
 226                 break;
 227         case 1:
 228                 writeb(val, addr);
 229                 break;
 230         default:
 231                 return PCIBIOS_BAD_REGISTER_NUMBER;
 232         }
 233
 234         return PCIBIOS_SUCCESSFUL;
 235 }
 236
 237 static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
 238 {
 239         void *addr;
 240         u32 val;
 241         int ret;
 242
 243         addr = mobiveil_pcie_comp_addr(pcie, off);
 244
 245         ret = mobiveil_pcie_read(addr, size, &val);
 246         if (ret)
 247                 dev_err(&pcie->pdev->dev, "read CSR address failed\n");
 248
 249         return val;
 250 }
 251
 252 static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
 253 {
 254         void *addr;
 255         int ret;
 256
 257         addr = mobiveil_pcie_comp_addr(pcie, off);
 258
 259         ret = mobiveil_pcie_write(addr, size, val);
 260         if (ret)
 261                 dev_err(&pcie->pdev->dev, "write CSR address failed\n");
 262 }
 263
 264 static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
 265 {
 266         return csr_read(pcie, off, 0x4);
 267 }
 268
 269 static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
 270 {
 271         csr_write(pcie, val, off, 0x4);
 272 }
 273
 274 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
 275 {
 276         return (csr_readl(pcie, LTSSM_STATUS) &
 277                 LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
 278 }
 279
 280 static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 281 {
 282         struct mobiveil_pcie *pcie = bus->sysdata;
 283
 284         /* Only one device down on each root port */
 285         if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
 286                 return false;
 287
 288         /*
 289          * Do not read more than one device on the bus directly
 290          * attached to RC
 291          */
 292         if ((bus->primary == pcie->root_bus_nr) && (PCI_SLOT(devfn) > 0))
 293                 return false;
 294
 295         return true;
 296 }
 297
 298 /*
 299  * mobiveil_pcie_map_bus - routine to get the configuration base of either
 300  * root port or endpoint
 301  */
 302 static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
 303                                            unsigned int devfn, int where)
 304 {
 305         struct mobiveil_pcie *pcie = bus->sysdata;
 306         u32 value;
 307
 308         if (!mobiveil_pcie_valid_device(bus, devfn))
 309                 return NULL;
 310
 311         /* RC config access */
 312         if (bus->number == pcie->root_bus_nr)
 313                 return pcie->csr_axi_slave_base + where;
 314
 315         /*
 316          * EP config access (in Config/APIO space)
 317          * Program PEX Address base (31..16 bits) with appropriate value
 318          * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
 319          * Relies on pci_lock serialization
 320          */
 321         value = bus->number << PAB_BUS_SHIFT |
 322                 PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
 323                 PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
 324
 325         csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
 326
 327         return pcie->config_axi_slave_base + where;
 328 }
 329
 330 static struct pci_ops mobiveil_pcie_ops = {
 331         .map_bus = mobiveil_pcie_map_bus,
 332         .read = pci_generic_config_read,
 333         .write = pci_generic_config_write,
 334 };
 335
 336 static void mobiveil_pcie_isr(struct irq_desc *desc)
 337 {
 338         struct irq_chip *chip = irq_desc_get_chip(desc);
 339         struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
 340         struct device *dev = &pcie->pdev->dev;
 341         struct mobiveil_msi *msi = &pcie->msi;
 342         u32 msi_data, msi_addr_lo, msi_addr_hi;
 343         u32 intr_status, msi_status;
 344         unsigned long shifted_status;
 345         u32 bit, virq, val, mask;
 346
 347         /*
 348          * The core provides a single interrupt for both INTx/MSI messages.
 349          * So we'll read both INTx and MSI status
 350          */
 351
 352         chained_irq_enter(chip, desc);
 353
 354         /* read INTx status */
 355         val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
 356         mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
 357         intr_status = val & mask;
 358
 359         /* Handle INTx */
 360         if (intr_status & PAB_INTP_INTX_MASK) {
 361                 shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
 362                 shifted_status &= PAB_INTP_INTX_MASK;
 363                 shifted_status >>= PAB_INTX_START;
 364                 do {
 365                         for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
 366                                 virq = irq_find_mapping(pcie->intx_domain,
 367                                                         bit + 1);
 368                                 if (virq)
 369                                         generic_handle_irq(virq);
 370                                 else
 371                                         dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
 372                                                             bit);
 373
 374                                 /* clear interrupt handled */
 375                                 csr_writel(pcie, 1 << (PAB_INTX_START + bit),
 376                                            PAB_INTP_AMBA_MISC_STAT);
 377                         }
 378
 379                         shifted_status = csr_readl(pcie,
 380                                                    PAB_INTP_AMBA_MISC_STAT);
 381                         shifted_status &= PAB_INTP_INTX_MASK;
 382                         shifted_status >>= PAB_INTX_START;
 383                 } while (shifted_status != 0);
 384         }
 385
 386         /* read extra MSI status register */
 387         msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
 388
 389         /* handle MSI interrupts */
 390         while (msi_status & 1) {
 391                 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
 392
 393                 /*
 394                  * MSI_STATUS_OFFSET register gets updated to zero
 395                  * once we pop not only the MSI data but also address
 396                  * from MSI hardware FIFO. So keeping these following
 397                  * two dummy reads.
 398                  */
 399                 msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
 400                                             MSI_ADDR_L_OFFSET);
 401                 msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
 402                                             MSI_ADDR_H_OFFSET);
 403                 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
 404                         msi_data, msi_addr_hi, msi_addr_lo);
 405
 406                 virq = irq_find_mapping(msi->dev_domain, msi_data);
 407                 if (virq)
 408                         generic_handle_irq(virq);
 409
 410                 msi_status = readl_relaxed(pcie->apb_csr_base +
 411                                            MSI_STATUS_OFFSET);
 412         }
 413
 414         /* Clear the interrupt status */
 415         csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
 416         chained_irq_exit(chip, desc);
 417 }
 418
 419 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
 420 {
 421         struct device *dev = &pcie->pdev->dev;
 422         struct platform_device *pdev = pcie->pdev;
 423         struct device_node *node = dev->of_node;
 424         struct resource *res;
 425
 426         /* map config resource */
 427         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 428                                            "config_axi_slave");
 429         pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
 430         if (IS_ERR(pcie->config_axi_slave_base))
 431                 return PTR_ERR(pcie->config_axi_slave_base);
 432         pcie->ob_io_res = res;
 433
 434         /* map csr resource */
 435         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 436                                            "csr_axi_slave");
 437         pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
 438         if (IS_ERR(pcie->csr_axi_slave_base))
 439                 return PTR_ERR(pcie->csr_axi_slave_base);
 440         pcie->pcie_reg_base = res->start;
 441
 442         /* map MSI config resource */
 443         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
 444         pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
 445         if (IS_ERR(pcie->apb_csr_base))
 446                 return PTR_ERR(pcie->apb_csr_base);
 447
 448         /* read the number of windows requested */
 449         if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
 450                 pcie->apio_wins = MAX_PIO_WINDOWS;
 451
 452         if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
 453                 pcie->ppio_wins = MAX_PIO_WINDOWS;
 454
 455         pcie->irq = platform_get_irq(pdev, 0);
 456         if (pcie->irq <= 0) {
 457                 dev_err(dev, "failed to map IRQ: %d\n", pcie->irq);
 458                 return -ENODEV;
 459         }
 460
 461         return 0;
 462 }
 463
 464 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
 465                                u64 pci_addr, u32 type, u64 size)
 466 {
 467         u32 value;
 468         u64 size64 = ~(size - 1);
 469
 470         if (win_num >= pcie->ppio_wins) {
 471                 dev_err(&pcie->pdev->dev,
 472                         "ERROR: max inbound windows reached !\n");
 473                 return;
 474         }
 475
 476         value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
 477         value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
 478         value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
 479                  (lower_32_bits(size64) & WIN_SIZE_MASK);
 480         csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
 481
 482         csr_writel(pcie, upper_32_bits(size64),
 483                    PAB_EXT_PEX_AMAP_SIZEN(win_num));
 484
 485         csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
 486
 487         csr_writel(pcie, lower_32_bits(pci_addr),
 488                    PAB_PEX_AMAP_PEX_WIN_L(win_num));
 489         csr_writel(pcie, upper_32_bits(pci_addr),
 490                    PAB_PEX_AMAP_PEX_WIN_H(win_num));
 491
 492         pcie->ib_wins_configured++;
 493 }
 494
 495 /*
 496  * routine to program the outbound windows
 497  */
 498 static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
 499                                u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
 500 {
 501         u32 value;
 502         u64 size64 = ~(size - 1);
 503
 504         if (win_num >= pcie->apio_wins) {
 505                 dev_err(&pcie->pdev->dev,
 506                         "ERROR: max outbound windows reached !\n");
 507                 return;
 508         }
 509
 510         /*
 511          * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
 512          * to 4 KB in PAB_AXI_AMAP_CTRL register
 513          */
 514         value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
 515         value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
 516         value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
 517                  (lower_32_bits(size64) & WIN_SIZE_MASK);
 518         csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
 519
 520         csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
 521
 522         /*
 523          * program AXI window base with appropriate value in
 524          * PAB_AXI_AMAP_AXI_WIN0 register
 525          */
 526         csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
 527                    PAB_AXI_AMAP_AXI_WIN(win_num));
 528         csr_writel(pcie, upper_32_bits(cpu_addr),
 529                    PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
 530
 531         csr_writel(pcie, lower_32_bits(pci_addr),
 532                    PAB_AXI_AMAP_PEX_WIN_L(win_num));
 533         csr_writel(pcie, upper_32_bits(pci_addr),
 534                    PAB_AXI_AMAP_PEX_WIN_H(win_num));
 535
 536         pcie->ob_wins_configured++;
 537 }
 538
 539 static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 540 {
 541         int retries;
 542
 543         /* check if the link is up or not */
 544         for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
 545                 if (mobiveil_pcie_link_up(pcie))
 546                         return 0;
 547
 548                 usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
 549         }
 550
 551         dev_err(&pcie->pdev->dev, "link never came up\n");
 552
 553         return -ETIMEDOUT;
 554 }
 555
 556 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
 557 {
 558         phys_addr_t msg_addr = pcie->pcie_reg_base;
 559         struct mobiveil_msi *msi = &pcie->msi;
 560
 561         pcie->msi.num_of_vectors = PCI_NUM_MSI;
 562         msi->msi_pages_phys = (phys_addr_t)msg_addr;
 563
 564         writel_relaxed(lower_32_bits(msg_addr),
 565                        pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
 566         writel_relaxed(upper_32_bits(msg_addr),
 567                        pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
 568         writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
 569         writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
 570 }
 571
 572 static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 573 {
 574         u32 value, pab_ctrl, type;
 575         struct resource_entry *win;
 576
 577         /* setup bus numbers */
 578         value = csr_readl(pcie, PCI_PRIMARY_BUS);
 579         value &= 0xff000000;
 580         value |= 0x00ff0100;
 581         csr_writel(pcie, value, PCI_PRIMARY_BUS);
 582
 583         /*
 584          * program Bus Master Enable Bit in Command Register in PAB Config
 585          * Space
 586          */
 587         value = csr_readl(pcie, PCI_COMMAND);
 588         value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 589         csr_writel(pcie, value, PCI_COMMAND);
 590
 591         /*
 592          * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
 593          * register
 594          */
 595         pab_ctrl = csr_readl(pcie, PAB_CTRL);
 596         pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
 597         csr_writel(pcie, pab_ctrl, PAB_CTRL);
 598
 599         csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
 600                    PAB_INTP_AMBA_MISC_ENB);
 601
 602         /*
 603          * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
 604          * PAB_AXI_PIO_CTRL Register
 605          */
 606         value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
 607         value |= APIO_EN_MASK;
 608         csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
 609
 610         /* Enable PCIe PIO master */
 611         value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
 612         value |= 1 << PIO_ENABLE_SHIFT;
 613         csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
 614
 615         /*
 616          * we'll program one outbound window for config reads and
 617          * another default inbound window for all the upstream traffic
 618          * rest of the outbound windows will be configured according to
 619          * the "ranges" field defined in device tree
 620          */
 621
 622         /* config outbound translation window */
 623         program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0,
 624                            CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
 625
 626         /* memory inbound translation window */
 627         program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
 628
 629         /* Get the I/O and memory ranges from DT */
 630         resource_list_for_each_entry(win, &pcie->resources) {
 631                 if (resource_type(win->res) == IORESOURCE_MEM)
 632                         type = MEM_WINDOW_TYPE;
 633                 else if (resource_type(win->res) == IORESOURCE_IO)
 634                         type = IO_WINDOW_TYPE;
 635                 else
 636                         continue;
 637
 638                 /* configure outbound translation window */
 639                 program_ob_windows(pcie, pcie->ob_wins_configured,
 640                                    win->res->start,
 641                                    win->res->start - win->offset,
 642                                    type, resource_size(win->res));
 643         }
 644
 645         /* fixup for PCIe class register */
 646         value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
 647         value &= 0xff;
 648         value |= (PCI_CLASS_BRIDGE_PCI << 16);
 649         csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
 650
 651         /* setup MSI hardware registers */
 652         mobiveil_pcie_enable_msi(pcie);
 653
 654         return 0;
 655 }
 656
 657 static void mobiveil_mask_intx_irq(struct irq_data *data)
 658 {
 659         struct irq_desc *desc = irq_to_desc(data->irq);
 660         struct mobiveil_pcie *pcie;
 661         unsigned long flags;
 662         u32 mask, shifted_val;
 663
 664         pcie = irq_desc_get_chip_data(desc);
 665         mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
 666         raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
 667         shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
 668         shifted_val &= ~mask;
 669         csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
 670         raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
 671 }
 672
 673 static void mobiveil_unmask_intx_irq(struct irq_data *data)
 674 {
 675         struct irq_desc *desc = irq_to_desc(data->irq);
 676         struct mobiveil_pcie *pcie;
 677         unsigned long flags;
 678         u32 shifted_val, mask;
 679
 680         pcie = irq_desc_get_chip_data(desc);
 681         mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
 682         raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
 683         shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
 684         shifted_val |= mask;
 685         csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
 686         raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
 687 }
 688
 689 static struct irq_chip intx_irq_chip = {
 690         .name = "mobiveil_pcie:intx",
 691         .irq_enable = mobiveil_unmask_intx_irq,
 692         .irq_disable = mobiveil_mask_intx_irq,
 693         .irq_mask = mobiveil_mask_intx_irq,
 694         .irq_unmask = mobiveil_unmask_intx_irq,
 695 };
 696
 697 /* routine to setup the INTx related data */
 698 static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 699                                   irq_hw_number_t hwirq)
 700 {
 701         irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
 702         irq_set_chip_data(irq, domain->host_data);
 703
 704         return 0;
 705 }
 706
 707 /* INTx domain operations structure */
 708 static const struct irq_domain_ops intx_domain_ops = {
 709         .map = mobiveil_pcie_intx_map,
 710 };
 711
 712 static struct irq_chip mobiveil_msi_irq_chip = {
 713         .name = "Mobiveil PCIe MSI",
 714         .irq_mask = pci_msi_mask_irq,
 715         .irq_unmask = pci_msi_unmask_irq,
 716 };
 717
 718 static struct msi_domain_info mobiveil_msi_domain_info = {
 719         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 720                    MSI_FLAG_PCI_MSIX),
 721         .chip   = &mobiveil_msi_irq_chip,
 722 };
 723
 724 static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 725 {
 726         struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
 727         phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
 728
 729         msg->address_lo = lower_32_bits(addr);
 730         msg->address_hi = upper_32_bits(addr);
 731         msg->data = data->hwirq;
 732
 733         dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
 734                 (int)data->hwirq, msg->address_hi, msg->address_lo);
 735 }
 736
 737 static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
 738                                      const struct cpumask *mask, bool force)
 739 {
 740         return -EINVAL;
 741 }
 742
 743 static struct irq_chip mobiveil_msi_bottom_irq_chip = {
 744         .name                   = "Mobiveil MSI",
 745         .irq_compose_msi_msg    = mobiveil_compose_msi_msg,
 746         .irq_set_affinity       = mobiveil_msi_set_affinity,
 747 };
 748
 749 static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
 750                                          unsigned int virq,
 751                                          unsigned int nr_irqs, void *args)
 752 {
 753         struct mobiveil_pcie *pcie = domain->host_data;
 754         struct mobiveil_msi *msi = &pcie->msi;
 755         unsigned long bit;
 756
 757         WARN_ON(nr_irqs != 1);
 758         mutex_lock(&msi->lock);
 759
 760         bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
 761         if (bit >= msi->num_of_vectors) {
 762                 mutex_unlock(&msi->lock);
 763                 return -ENOSPC;
 764         }
 765
 766         set_bit(bit, msi->msi_irq_in_use);
 767
 768         mutex_unlock(&msi->lock);
 769
 770         irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
 771                             domain->host_data, handle_level_irq, NULL, NULL);
 772         return 0;
 773 }
 774
 775 static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
 776                                          unsigned int virq,
 777                                          unsigned int nr_irqs)
 778 {
 779         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 780         struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
 781         struct mobiveil_msi *msi = &pcie->msi;
 782
 783         mutex_lock(&msi->lock);
 784
 785         if (!test_bit(d->hwirq, msi->msi_irq_in_use))
 786                 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
 787                         d->hwirq);
 788         else
 789                 __clear_bit(d->hwirq, msi->msi_irq_in_use);
 790
 791         mutex_unlock(&msi->lock);
 792 }
 793 static const struct irq_domain_ops msi_domain_ops = {
 794         .alloc  = mobiveil_irq_msi_domain_alloc,
 795         .free   = mobiveil_irq_msi_domain_free,
 796 };
 797
 798 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
 799 {
 800         struct device *dev = &pcie->pdev->dev;
 801         struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
 802         struct mobiveil_msi *msi = &pcie->msi;
 803
 804         mutex_init(&pcie->msi.lock);
 805         msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
 806                                                 &msi_domain_ops, pcie);
 807         if (!msi->dev_domain) {
 808                 dev_err(dev, "failed to create IRQ domain\n");
 809                 return -ENOMEM;
 810         }
 811
 812         msi->msi_domain = pci_msi_create_irq_domain(fwnode,
 813                                                     &mobiveil_msi_domain_info,
 814                                                     msi->dev_domain);
 815         if (!msi->msi_domain) {
 816                 dev_err(dev, "failed to create MSI domain\n");
 817                 irq_domain_remove(msi->dev_domain);
 818                 return -ENOMEM;
 819         }
 820
 821         return 0;
 822 }
 823
 824 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
 825 {
 826         struct device *dev = &pcie->pdev->dev;
 827         struct device_node *node = dev->of_node;
 828         int ret;
 829
 830         /* setup INTx */
 831         pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
 832                                                   &intx_domain_ops, pcie);
 833
 834         if (!pcie->intx_domain) {
 835                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 836                 return -ENOMEM;
 837         }
 838
 839         raw_spin_lock_init(&pcie->intx_mask_lock);
 840
 841         /* setup MSI */
 842         ret = mobiveil_allocate_msi_domains(pcie);
 843         if (ret)
 844                 return ret;
 845
 846         return 0;
 847 }
 848
 849 static int mobiveil_pcie_probe(struct platform_device *pdev)
 850 {
 851         struct mobiveil_pcie *pcie;
 852         struct pci_bus *bus;
 853         struct pci_bus *child;
 854         struct pci_host_bridge *bridge;
 855         struct device *dev = &pdev->dev;
 856         resource_size_t iobase;
 857         int ret;
 858
 859         /* allocate the PCIe port */
 860         bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 861         if (!bridge)
 862                 return -ENOMEM;
 863
 864         pcie = pci_host_bridge_priv(bridge);
 865
 866         pcie->pdev = pdev;
 867
 868         ret = mobiveil_pcie_parse_dt(pcie);
 869         if (ret) {
 870                 dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
 871                 return ret;
 872         }
 873
 874         INIT_LIST_HEAD(&pcie->resources);
 875
 876         /* parse the host bridge base addresses from the device tree file */
 877         ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
 878                                                     &pcie->resources, &iobase);
 879         if (ret) {
 880                 dev_err(dev, "Getting bridge resources failed\n");
 881                 return ret;
 882         }
 883
 884         /*
 885          * configure all inbound and outbound windows and prepare the RC for
 886          * config access
 887          */
 888         ret = mobiveil_host_init(pcie);
 889         if (ret) {
 890                 dev_err(dev, "Failed to initialize host\n");
 891                 goto error;
 892         }
 893
 894         /* initialize the IRQ domains */
 895         ret = mobiveil_pcie_init_irq_domain(pcie);
 896         if (ret) {
 897                 dev_err(dev, "Failed creating IRQ Domain\n");
 898                 goto error;
 899         }
 900
 901         irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
 902
 903         ret = devm_request_pci_bus_resources(dev, &pcie->resources);
 904         if (ret)
 905                 goto error;
 906
 907         /* Initialize bridge */
 908         list_splice_init(&pcie->resources, &bridge->windows);
 909         bridge->dev.parent = dev;
 910         bridge->sysdata = pcie;
 911         bridge->busnr = pcie->root_bus_nr;
 912         bridge->ops = &mobiveil_pcie_ops;
 913         bridge->map_irq = of_irq_parse_and_map_pci;
 914         bridge->swizzle_irq = pci_common_swizzle;
 915
 916         ret = mobiveil_bringup_link(pcie);
 917         if (ret) {
 918                 dev_info(dev, "link bring-up failed\n");
 919                 goto error;
 920         }
 921
 922         /* setup the kernel resources for the newly added PCIe root bus */
 923         ret = pci_scan_root_bus_bridge(bridge);
 924         if (ret)
 925                 goto error;
 926
 927         bus = bridge->bus;
 928
 929         pci_assign_unassigned_bus_resources(bus);
 930         list_for_each_entry(child, &bus->children, node)
 931                 pcie_bus_configure_settings(child);
 932         pci_bus_add_devices(bus);
 933
 934         return 0;
 935 error:
 936         pci_free_resource_list(&pcie->resources);
 937         return ret;
 938 }
 939
 940 static const struct of_device_id mobiveil_pcie_of_match[] = {
 941         {.compatible = "mbvl,gpex40-pcie",},
 942         {},
 943 };
 944
 945 MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
 946
 947 static struct platform_driver mobiveil_pcie_driver = {
 948         .probe = mobiveil_pcie_probe,
 949         .driver = {
 950                 .name = "mobiveil-pcie",
 951                 .of_match_table = mobiveil_pcie_of_match,
 952                 .suppress_bind_attrs = true,
 953         },
 954 };
 955
 956 builtin_platform_driver(mobiveil_pcie_driver);
 957
 958 MODULE_LICENSE("GPL v2");
 959 MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
 960 MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");