drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/mlx5/driver.h>
  41 #include <linux/mlx5/qp.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/port.h>
  44 #include <linux/mlx5/vport.h>
  45 #include <linux/mlx5/transobj.h>
  46 #include <linux/rhashtable.h>
  47 #include <net/switchdev.h>
  48 #include "wq.h"
  49 #include "mlx5_core.h"
  50 #include "en_stats.h"
  51
  52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
  53
  54 #define MLX5E_MAX_NUM_TC        8
  55
  56 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  57 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  58 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  59
  60 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  61 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  62 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  63
  64 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x1
  65 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3
  66 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6
  67
  68 #define MLX5_RX_HEADROOM NET_SKB_PAD
  69
  70 #define MLX5_MPWRQ_LOG_STRIDE_SIZE              6  /* >= 6, HW restriction */
  71 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8  /* >= 6, HW restriction */
  72 #define MLX5_MPWRQ_LOG_WQE_SZ                   18
  73 #define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
  74                                     MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
  75 #define MLX5_MPWRQ_PAGES_PER_WQE                BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
  76 #define MLX5_MPWRQ_STRIDES_PER_PAGE             (MLX5_MPWRQ_NUM_STRIDES >> \
  77                                                  MLX5_MPWRQ_WQE_PAGE_ORDER)
  78
  79 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
  80 #define MLX5E_REQUIRED_MTTS(rqs, wqes)\
  81         (rqs * wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
  82 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) <= U16_MAX)
  83
  84 #define MLX5_UMR_ALIGN                          (2048)
  85 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD       (256)
  86
  87 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
  88 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
  89 #define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4
  90
  91 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
  92 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
  93 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
  94 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
  95 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
  96 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
  97 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
  98
  99 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
 100 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
 101 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
 102 #define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
 103 #define MLX5E_TX_CQ_POLL_BUDGET        128
 104 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
 105 #define MLX5E_SQ_BF_BUDGET             16
 106
 107 #define MLX5E_ICOSQ_MAX_WQEBBS \
 108         (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
 109
 110 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
 111 #define MLX5E_XDP_IHS_DS_COUNT \
 112         DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)
 113 #define MLX5E_XDP_TX_DS_COUNT \
 114         (MLX5E_XDP_IHS_DS_COUNT + \
 115          (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
 116 #define MLX5E_XDP_TX_WQEBBS \
 117         DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)
 118
 119 #define MLX5E_NUM_MAIN_GROUPS 9
 120
 121 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
 122 {
 123         switch (wq_type) {
 124         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 125                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
 126                              wq_size / 2);
 127         default:
 128                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
 129                              wq_size / 2);
 130         }
 131 }
 132
 133 static inline int mlx5_min_log_rq_size(int wq_type)
 134 {
 135         switch (wq_type) {
 136         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 137                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 138         default:
 139                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 140         }
 141 }
 142
 143 static inline int mlx5_max_log_rq_size(int wq_type)
 144 {
 145         switch (wq_type) {
 146         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 147                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
 148         default:
 149                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 150         }
 151 }
 152
 153 enum {
 154         MLX5E_INLINE_MODE_L2,
 155         MLX5E_INLINE_MODE_VPORT_CONTEXT,
 156         MLX5_INLINE_MODE_NOT_REQUIRED,
 157 };
 158
 159 struct mlx5e_tx_wqe {
 160         struct mlx5_wqe_ctrl_seg ctrl;
 161         struct mlx5_wqe_eth_seg  eth;
 162 };
 163
 164 struct mlx5e_rx_wqe {
 165         struct mlx5_wqe_srq_next_seg  next;
 166         struct mlx5_wqe_data_seg      data;
 167 };
 168
 169 struct mlx5e_umr_wqe {
 170         struct mlx5_wqe_ctrl_seg       ctrl;
 171         struct mlx5_wqe_umr_ctrl_seg   uctrl;
 172         struct mlx5_mkey_seg           mkc;
 173         struct mlx5_wqe_data_seg       data;
 174 };
 175
 176 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
 177         "rx_cqe_moder",
 178 };
 179
 180 enum mlx5e_priv_flag {
 181         MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
 182 };
 183
 184 #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable)    \
 185         do {                                        \
 186                 if (enable)                         \
 187                         priv->pflags |= pflag;      \
 188                 else                                \
 189                         priv->pflags &= ~pflag;     \
 190         } while (0)
 191
 192 #ifdef CONFIG_MLX5_CORE_EN_DCB
 193 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 194 #endif
 195
 196 struct mlx5e_cq_moder {
 197         u16 usec;
 198         u16 pkts;
 199 };
 200
 201 struct mlx5e_params {
 202         u8  log_sq_size;
 203         u8  rq_wq_type;
 204         u8  mpwqe_log_stride_sz;
 205         u8  mpwqe_log_num_strides;
 206         u8  log_rq_size;
 207         u16 num_channels;
 208         u8  num_tc;
 209         u8  rx_cq_period_mode;
 210         bool rx_cqe_compress_admin;
 211         bool rx_cqe_compress;
 212         struct mlx5e_cq_moder rx_cq_moderation;
 213         struct mlx5e_cq_moder tx_cq_moderation;
 214         u16 min_rx_wqes;
 215         bool lro_en;
 216         u32 lro_wqe_sz;
 217         u16 tx_max_inline;
 218         u8  tx_min_inline_mode;
 219         u8  rss_hfunc;
 220         u8  toeplitz_hash_key[40];
 221         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 222         bool vlan_strip_disable;
 223 #ifdef CONFIG_MLX5_CORE_EN_DCB
 224         struct ieee_ets ets;
 225 #endif
 226         bool rx_am_enabled;
 227         u32 lro_timeout;
 228 };
 229
 230 struct mlx5e_tstamp {
 231         rwlock_t                   lock;
 232         struct cyclecounter        cycles;
 233         struct timecounter         clock;
 234         struct hwtstamp_config     hwtstamp_config;
 235         u32                        nominal_c_mult;
 236         unsigned long              overflow_period;
 237         struct delayed_work        overflow_work;
 238         struct mlx5_core_dev      *mdev;
 239         struct ptp_clock          *ptp;
 240         struct ptp_clock_info      ptp_info;
 241 };
 242
 243 enum {
 244         MLX5E_RQ_STATE_ENABLED,
 245         MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
 246         MLX5E_RQ_STATE_AM,
 247 };
 248
 249 struct mlx5e_cq {
 250         /* data path - accessed per cqe */
 251         struct mlx5_cqwq           wq;
 252
 253         /* data path - accessed per napi poll */
 254         u16                        event_ctr;
 255         struct napi_struct        *napi;
 256         struct mlx5_core_cq        mcq;
 257         struct mlx5e_channel      *channel;
 258         struct mlx5e_priv         *priv;
 259
 260         /* cqe decompression */
 261         struct mlx5_cqe64          title;
 262         struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
 263         u8                         mini_arr_idx;
 264         u16                        decmprs_left;
 265         u16                        decmprs_wqe_counter;
 266
 267         /* control */
 268         struct mlx5_wq_ctrl        wq_ctrl;
 269 } ____cacheline_aligned_in_smp;
 270
 271 struct mlx5e_rq;
 272 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
 273                                        struct mlx5_cqe64 *cqe);
 274 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
 275                                   u16 ix);
 276
 277 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
 278
 279 struct mlx5e_dma_info {
 280         struct page     *page;
 281         dma_addr_t      addr;
 282 };
 283
 284 struct mlx5e_rx_am_stats {
 285         int ppms; /* packets per msec */
 286         int bpms; /* bytes per msec */
 287         int epms; /* events per msec */
 288 };
 289
 290 struct mlx5e_rx_am_sample {
 291         ktime_t time;
 292         u32     pkt_ctr;
 293         u32     byte_ctr;
 294         u16     event_ctr;
 295 };
 296
 297 struct mlx5e_rx_am { /* Adaptive Moderation */
 298         u8                                      state;
 299         struct mlx5e_rx_am_stats                prev_stats;
 300         struct mlx5e_rx_am_sample               start_sample;
 301         struct work_struct                      work;
 302         u8                                      profile_ix;
 303         u8                                      mode;
 304         u8                                      tune_state;
 305         u8                                      steps_right;
 306         u8                                      steps_left;
 307         u8                                      tired;
 308 };
 309
 310 /* a single cache unit is capable to serve one napi call (for non-striding rq)
 311  * or a MPWQE (for striding rq).
 312  */
 313 #define MLX5E_CACHE_UNIT        (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
 314                                  MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
 315 #define MLX5E_CACHE_SIZE        (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
 316 struct mlx5e_page_cache {
 317         u32 head;
 318         u32 tail;
 319         struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
 320 };
 321
 322 struct mlx5e_rq {
 323         /* data path */
 324         struct mlx5_wq_ll      wq;
 325
 326         union {
 327                 struct mlx5e_dma_info *dma_info;
 328                 struct {
 329                         struct mlx5e_mpw_info *info;
 330                         void                  *mtt_no_align;
 331                         u32                    mtt_offset;
 332                 } mpwqe;
 333         };
 334         struct {
 335                 u8             page_order;
 336                 u32            wqe_sz;    /* wqe data buffer size */
 337                 u8             map_dir;   /* dma map direction */
 338         } buff;
 339         __be32                 mkey_be;
 340
 341         struct device         *pdev;
 342         struct net_device     *netdev;
 343         struct mlx5e_tstamp   *tstamp;
 344         struct mlx5e_rq_stats  stats;
 345         struct mlx5e_cq        cq;
 346         struct mlx5e_page_cache page_cache;
 347
 348         mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 349         mlx5e_fp_alloc_wqe     alloc_wqe;
 350         mlx5e_fp_dealloc_wqe   dealloc_wqe;
 351
 352         unsigned long          state;
 353         int                    ix;
 354
 355         struct mlx5e_rx_am     am; /* Adaptive Moderation */
 356         struct bpf_prog       *xdp_prog;
 357
 358         /* control */
 359         struct mlx5_wq_ctrl    wq_ctrl;
 360         u8                     wq_type;
 361         u32                    mpwqe_stride_sz;
 362         u32                    mpwqe_num_strides;
 363         u32                    rqn;
 364         struct mlx5e_channel  *channel;
 365         struct mlx5e_priv     *priv;
 366 } ____cacheline_aligned_in_smp;
 367
 368 struct mlx5e_umr_dma_info {
 369         __be64                *mtt;
 370         dma_addr_t             mtt_addr;
 371         struct mlx5e_dma_info  dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
 372         struct mlx5e_umr_wqe   wqe;
 373 };
 374
 375 struct mlx5e_mpw_info {
 376         struct mlx5e_umr_dma_info umr;
 377         u16 consumed_strides;
 378         u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
 379 };
 380
 381 struct mlx5e_tx_wqe_info {
 382         u32 num_bytes;
 383         u8  num_wqebbs;
 384         u8  num_dma;
 385 };
 386
 387 enum mlx5e_dma_map_type {
 388         MLX5E_DMA_MAP_SINGLE,
 389         MLX5E_DMA_MAP_PAGE
 390 };
 391
 392 struct mlx5e_sq_dma {
 393         dma_addr_t              addr;
 394         u32                     size;
 395         enum mlx5e_dma_map_type type;
 396 };
 397
 398 enum {
 399         MLX5E_SQ_STATE_ENABLED,
 400         MLX5E_SQ_STATE_BF_ENABLE,
 401 };
 402
 403 struct mlx5e_sq_wqe_info {
 404         u8  opcode;
 405         u8  num_wqebbs;
 406 };
 407
 408 enum mlx5e_sq_type {
 409         MLX5E_SQ_TXQ,
 410         MLX5E_SQ_ICO,
 411         MLX5E_SQ_XDP
 412 };
 413
 414 struct mlx5e_sq {
 415         /* data path */
 416
 417         /* dirtied @completion */
 418         u16                        cc;
 419         u32                        dma_fifo_cc;
 420
 421         /* dirtied @xmit */
 422         u16                        pc ____cacheline_aligned_in_smp;
 423         u32                        dma_fifo_pc;
 424         u16                        bf_offset;
 425         u16                        prev_cc;
 426         u8                         bf_budget;
 427         struct mlx5e_sq_stats      stats;
 428
 429         struct mlx5e_cq            cq;
 430
 431         /* pointers to per tx element info: write@xmit, read@completion */
 432         union {
 433                 struct {
 434                         struct sk_buff           **skb;
 435                         struct mlx5e_sq_dma       *dma_fifo;
 436                         struct mlx5e_tx_wqe_info  *wqe_info;
 437                 } txq;
 438                 struct mlx5e_sq_wqe_info *ico_wqe;
 439                 struct {
 440                         struct mlx5e_sq_wqe_info  *wqe_info;
 441                         struct mlx5e_dma_info     *di;
 442                         bool                       doorbell;
 443                 } xdp;
 444         } db;
 445
 446         /* read only */
 447         struct mlx5_wq_cyc         wq;
 448         u32                        dma_fifo_mask;
 449         void __iomem              *uar_map;
 450         struct netdev_queue       *txq;
 451         u32                        sqn;
 452         u16                        bf_buf_size;
 453         u16                        max_inline;
 454         u8                         min_inline_mode;
 455         u16                        edge;
 456         struct device             *pdev;
 457         struct mlx5e_tstamp       *tstamp;
 458         __be32                     mkey_be;
 459         unsigned long              state;
 460
 461         /* control path */
 462         struct mlx5_wq_ctrl        wq_ctrl;
 463         struct mlx5_uar            uar;
 464         struct mlx5e_channel      *channel;
 465         int                        tc;
 466         u32                        rate_limit;
 467         u8                         type;
 468 } ____cacheline_aligned_in_smp;
 469
 470 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
 471 {
 472         return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
 473                 (sq->cc  == sq->pc));
 474 }
 475
 476 enum channel_flags {
 477         MLX5E_CHANNEL_NAPI_SCHED = 1,
 478 };
 479
 480 struct mlx5e_channel {
 481         /* data path */
 482         struct mlx5e_rq            rq;
 483         struct mlx5e_sq            xdp_sq;
 484         struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
 485         struct mlx5e_sq            icosq;   /* internal control operations */
 486         bool                       xdp;
 487         struct napi_struct         napi;
 488         struct device             *pdev;
 489         struct net_device         *netdev;
 490         __be32                     mkey_be;
 491         u8                         num_tc;
 492         unsigned long              flags;
 493
 494         /* control */
 495         struct mlx5e_priv         *priv;
 496         int                        ix;
 497         int                        cpu;
 498 };
 499
 500 enum mlx5e_traffic_types {
 501         MLX5E_TT_IPV4_TCP,
 502         MLX5E_TT_IPV6_TCP,
 503         MLX5E_TT_IPV4_UDP,
 504         MLX5E_TT_IPV6_UDP,
 505         MLX5E_TT_IPV4_IPSEC_AH,
 506         MLX5E_TT_IPV6_IPSEC_AH,
 507         MLX5E_TT_IPV4_IPSEC_ESP,
 508         MLX5E_TT_IPV6_IPSEC_ESP,
 509         MLX5E_TT_IPV4,
 510         MLX5E_TT_IPV6,
 511         MLX5E_TT_ANY,
 512         MLX5E_NUM_TT,
 513         MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
 514 };
 515
 516 enum {
 517         MLX5E_STATE_ASYNC_EVENTS_ENABLED,
 518         MLX5E_STATE_OPENED,
 519         MLX5E_STATE_DESTROYING,
 520 };
 521
 522 struct mlx5e_vxlan_db {
 523         spinlock_t                      lock; /* protect vxlan table */
 524         struct radix_tree_root          tree;
 525 };
 526
 527 struct mlx5e_l2_rule {
 528         u8  addr[ETH_ALEN + 2];
 529         struct mlx5_flow_rule *rule;
 530 };
 531
 532 struct mlx5e_flow_table {
 533         int num_groups;
 534         struct mlx5_flow_table *t;
 535         struct mlx5_flow_group **g;
 536 };
 537
 538 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
 539
 540 struct mlx5e_tc_table {
 541         struct mlx5_flow_table          *t;
 542
 543         struct rhashtable_params        ht_params;
 544         struct rhashtable               ht;
 545 };
 546
 547 struct mlx5e_vlan_table {
 548         struct mlx5e_flow_table         ft;
 549         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 550         struct mlx5_flow_rule   *active_vlans_rule[VLAN_N_VID];
 551         struct mlx5_flow_rule   *untagged_rule;
 552         struct mlx5_flow_rule   *any_vlan_rule;
 553         bool          filter_disabled;
 554 };
 555
 556 struct mlx5e_l2_table {
 557         struct mlx5e_flow_table    ft;
 558         struct hlist_head          netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
 559         struct hlist_head          netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
 560         struct mlx5e_l2_rule       broadcast;
 561         struct mlx5e_l2_rule       allmulti;
 562         struct mlx5e_l2_rule       promisc;
 563         bool                       broadcast_enabled;
 564         bool                       allmulti_enabled;
 565         bool                       promisc_enabled;
 566 };
 567
 568 /* L3/L4 traffic type classifier */
 569 struct mlx5e_ttc_table {
 570         struct mlx5e_flow_table  ft;
 571         struct mlx5_flow_rule    *rules[MLX5E_NUM_TT];
 572 };
 573
 574 #define ARFS_HASH_SHIFT BITS_PER_BYTE
 575 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
 576 struct arfs_table {
 577         struct mlx5e_flow_table  ft;
 578         struct mlx5_flow_rule    *default_rule;
 579         struct hlist_head        rules_hash[ARFS_HASH_SIZE];
 580 };
 581
 582 enum  arfs_type {
 583         ARFS_IPV4_TCP,
 584         ARFS_IPV6_TCP,
 585         ARFS_IPV4_UDP,
 586         ARFS_IPV6_UDP,
 587         ARFS_NUM_TYPES,
 588 };
 589
 590 struct mlx5e_arfs_tables {
 591         struct arfs_table arfs_tables[ARFS_NUM_TYPES];
 592         /* Protect aRFS rules list */
 593         spinlock_t                     arfs_lock;
 594         struct list_head               rules;
 595         int                            last_filter_id;
 596         struct workqueue_struct        *wq;
 597 };
 598
 599 /* NIC prio FTS */
 600 enum {
 601         MLX5E_VLAN_FT_LEVEL = 0,
 602         MLX5E_L2_FT_LEVEL,
 603         MLX5E_TTC_FT_LEVEL,
 604         MLX5E_ARFS_FT_LEVEL
 605 };
 606
 607 struct mlx5e_ethtool_table {
 608         struct mlx5_flow_table *ft;
 609         int                    num_rules;
 610 };
 611
 612 #define ETHTOOL_NUM_L3_L4_FTS 7
 613 #define ETHTOOL_NUM_L2_FTS 4
 614
 615 struct mlx5e_ethtool_steering {
 616         struct mlx5e_ethtool_table      l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
 617         struct mlx5e_ethtool_table      l2_ft[ETHTOOL_NUM_L2_FTS];
 618         struct list_head                rules;
 619         int                             tot_num_rules;
 620 };
 621
 622 struct mlx5e_flow_steering {
 623         struct mlx5_flow_namespace      *ns;
 624         struct mlx5e_ethtool_steering   ethtool;
 625         struct mlx5e_tc_table           tc;
 626         struct mlx5e_vlan_table         vlan;
 627         struct mlx5e_l2_table           l2;
 628         struct mlx5e_ttc_table          ttc;
 629         struct mlx5e_arfs_tables        arfs;
 630 };
 631
 632 struct mlx5e_rqt {
 633         u32              rqtn;
 634         bool             enabled;
 635 };
 636
 637 struct mlx5e_tir {
 638         u32               tirn;
 639         struct mlx5e_rqt  rqt;
 640         struct list_head  list;
 641 };
 642
 643 enum {
 644         MLX5E_TC_PRIO = 0,
 645         MLX5E_NIC_PRIO
 646 };
 647
 648 struct mlx5e_profile {
 649         void    (*init)(struct mlx5_core_dev *mdev,
 650                         struct net_device *netdev,
 651                         const struct mlx5e_profile *profile, void *ppriv);
 652         void    (*cleanup)(struct mlx5e_priv *priv);
 653         int     (*init_rx)(struct mlx5e_priv *priv);
 654         void    (*cleanup_rx)(struct mlx5e_priv *priv);
 655         int     (*init_tx)(struct mlx5e_priv *priv);
 656         void    (*cleanup_tx)(struct mlx5e_priv *priv);
 657         void    (*enable)(struct mlx5e_priv *priv);
 658         void    (*disable)(struct mlx5e_priv *priv);
 659         void    (*update_stats)(struct mlx5e_priv *priv);
 660         int     (*max_nch)(struct mlx5_core_dev *mdev);
 661         int     max_tc;
 662 };
 663
 664 struct mlx5e_priv {
 665         /* priv data path fields - start */
 666         struct mlx5e_sq            **txq_to_sq_map;
 667         int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 668         struct bpf_prog *xdp_prog;
 669         /* priv data path fields - end */
 670
 671         unsigned long              state;
 672         struct mutex               state_lock; /* Protects Interface state */
 673         struct mlx5_core_mkey      umr_mkey;
 674         struct mlx5e_rq            drop_rq;
 675
 676         struct mlx5e_channel     **channel;
 677         u32                        tisn[MLX5E_MAX_NUM_TC];
 678         struct mlx5e_rqt           indir_rqt;
 679         struct mlx5e_tir           indir_tir[MLX5E_NUM_INDIR_TIRS];
 680         struct mlx5e_tir           direct_tir[MLX5E_MAX_NUM_CHANNELS];
 681         u32                        tx_rates[MLX5E_MAX_NUM_SQS];
 682
 683         struct mlx5e_flow_steering fs;
 684         struct mlx5e_vxlan_db      vxlan;
 685
 686         struct mlx5e_params        params;
 687         struct workqueue_struct    *wq;
 688         struct work_struct         update_carrier_work;
 689         struct work_struct         set_rx_mode_work;
 690         struct work_struct         tx_timeout_work;
 691         struct delayed_work        update_stats_work;
 692
 693         u32                        pflags;
 694         struct mlx5_core_dev      *mdev;
 695         struct net_device         *netdev;
 696         struct mlx5e_stats         stats;
 697         struct mlx5e_tstamp        tstamp;
 698         u16 q_counter;
 699         const struct mlx5e_profile *profile;
 700         void                      *ppriv;
 701 };
 702
 703 void mlx5e_build_ptys2ethtool_map(void);
 704
 705 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
 706 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 707                        void *accel_priv, select_queue_fallback_t fallback);
 708 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 709
 710 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 711 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 712 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 713 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 714 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 715 void mlx5e_free_sq_descs(struct mlx5e_sq *sq);
 716
 717 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 718                         bool recycle);
 719 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 720 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 721 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 722 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 723 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 724 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
 725 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 726 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
 727 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
 728 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 729
 730 void mlx5e_rx_am(struct mlx5e_rq *rq);
 731 void mlx5e_rx_am_work(struct work_struct *work);
 732 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
 733
 734 void mlx5e_update_stats(struct mlx5e_priv *priv);
 735
 736 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
 737 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
 738 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
 739 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
 740 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
 741                            int location);
 742 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
 743                                 struct ethtool_rxnfc *info, u32 *rule_locs);
 744 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
 745                                struct ethtool_rx_flow_spec *fs);
 746 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
 747                               int location);
 748 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
 749 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
 750 void mlx5e_set_rx_mode_work(struct work_struct *work);
 751
 752 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 753                         struct skb_shared_hwtstamps *hwts);
 754 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 755 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 756 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
 757 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
 758 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
 759
 760 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 761                           u16 vid);
 762 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 763                            u16 vid);
 764 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 765 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 766
 767 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
 768
 769 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
 770 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
 771                                     enum mlx5e_traffic_types tt);
 772
 773 int mlx5e_open_locked(struct net_device *netdev);
 774 int mlx5e_close_locked(struct net_device *netdev);
 775 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
 776                                    u32 *indirection_rqt, int len,
 777                                    int num_channels);
 778 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 779
 780 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
 781                                  u8 cq_period_mode);
 782
 783 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
 784                                       struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
 785 {
 786         u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
 787
 788         /* ensure wqe is visible to device before updating doorbell record */
 789         dma_wmb();
 790
 791         *sq->wq.db = cpu_to_be32(sq->pc);
 792
 793         /* ensure doorbell record is visible to device before ringing the
 794          * doorbell
 795          */
 796         wmb();
 797         if (bf_sz)
 798                 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
 799         else
 800                 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
 801         /* flush the write-combining mapped buffer */
 802         wmb();
 803
 804         sq->bf_offset ^= sq->bf_buf_size;
 805 }
 806
 807 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 808 {
 809         struct mlx5_core_cq *mcq;
 810
 811         mcq = &cq->mcq;
 812         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
 813 }
 814
 815 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 816 {
 817         return rq->mpwqe.mtt_offset +
 818                 wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
 819 }
 820
 821 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
 822 {
 823         return min_t(int, mdev->priv.eq_table.num_comp_vectors,
 824                      MLX5E_MAX_NUM_CHANNELS);
 825 }
 826
 827 extern const struct ethtool_ops mlx5e_ethtool_ops;
 828 #ifdef CONFIG_MLX5_CORE_EN_DCB
 829 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
 830 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
 831 #endif
 832
 833 #ifndef CONFIG_RFS_ACCEL
 834 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
 835 {
 836         return 0;
 837 }
 838
 839 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
 840
 841 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
 842 {
 843         return -ENOTSUPP;
 844 }
 845
 846 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
 847 {
 848         return -ENOTSUPP;
 849 }
 850 #else
 851 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
 852 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
 853 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
 854 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
 855 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
 856                         u16 rxq_index, u32 flow_id);
 857 #endif
 858
 859 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
 860 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
 861                      struct mlx5e_tir *tir, u32 *in, int inlen);
 862 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
 863                        struct mlx5e_tir *tir);
 864 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
 865 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
 866 int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev);
 867
 868 struct mlx5_eswitch_rep;
 869 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
 870                          struct mlx5_eswitch_rep *rep);
 871 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
 872                             struct mlx5_eswitch_rep *rep);
 873 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
 874 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
 875                           struct mlx5_eswitch_rep *rep);
 876 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
 877 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
 878 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
 879 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 880
 881 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
 882 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
 883 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
 884 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
 885 int mlx5e_create_tises(struct mlx5e_priv *priv);
 886 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
 887 int mlx5e_close(struct net_device *netdev);
 888 int mlx5e_open(struct net_device *netdev);
 889 void mlx5e_update_stats_work(struct work_struct *work);
 890 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
 891                                        const struct mlx5e_profile *profile,
 892                                        void *ppriv);
 893 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
 894 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 895 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 896 struct rtnl_link_stats64 *
 897 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
 898 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
 899
 900 #endif /* __MLX5_EN_H__ */