arch/arm/mach-imx/cpu.c

   1 #include <linux/err.h>
   2 #include <linux/module.h>
   3 #include <linux/io.h>
   4 #include <linux/of.h>
   5 #include <linux/of_address.h>
   6 #include <linux/slab.h>
   7 #include <linux/sys_soc.h>
   8
   9 #include "hardware.h"
  10 #include "common.h"
  11
  12 unsigned int __mxc_cpu_type;
  13 static unsigned int imx_soc_revision;
  14
  15 void mxc_set_cpu_type(unsigned int type)
  16 {
  17         __mxc_cpu_type = type;
  18 }
  19
  20 void imx_set_soc_revision(unsigned int rev)
  21 {
  22         imx_soc_revision = rev;
  23 }
  24
  25 unsigned int imx_get_soc_revision(void)
  26 {
  27         return imx_soc_revision;
  28 }
  29
  30 void imx_print_silicon_rev(const char *cpu, int srev)
  31 {
  32         if (srev == IMX_CHIP_REVISION_UNKNOWN)
  33                 pr_info("CPU identified as %s, unknown revision\n", cpu);
  34         else
  35                 pr_info("CPU identified as %s, silicon rev %d.%d\n",
  36                                 cpu, (srev >> 4) & 0xf, srev & 0xf);
  37 }
  38
  39 void __init imx_set_aips(void __iomem *base)
  40 {
  41         unsigned int reg;
  42 /*
  43  * Set all MPROTx to be non-bufferable, trusted for R/W,
  44  * not forced to user-mode.
  45  */
  46         imx_writel(0x77777777, base + 0x0);
  47         imx_writel(0x77777777, base + 0x4);
  48
  49 /*
  50  * Set all OPACRx to be non-bufferable, to not require
  51  * supervisor privilege level for access, allow for
  52  * write access and untrusted master access.
  53  */
  54         imx_writel(0x0, base + 0x40);
  55         imx_writel(0x0, base + 0x44);
  56         imx_writel(0x0, base + 0x48);
  57         imx_writel(0x0, base + 0x4C);
  58         reg = imx_readl(base + 0x50) & 0x00FFFFFF;
  59         imx_writel(reg, base + 0x50);
  60 }
  61
  62 void __init imx_aips_allow_unprivileged_access(
  63                 const char *compat)
  64 {
  65         void __iomem *aips_base_addr;
  66         struct device_node *np;
  67
  68         for_each_compatible_node(np, NULL, compat) {
  69                 aips_base_addr = of_iomap(np, 0);
  70                 imx_set_aips(aips_base_addr);
  71         }
  72 }
  73
  74 struct device * __init imx_soc_device_init(void)
  75 {
  76         struct soc_device_attribute *soc_dev_attr;
  77         struct soc_device *soc_dev;
  78         struct device_node *root;
  79         const char *soc_id;
  80         int ret;
  81
  82         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  83         if (!soc_dev_attr)
  84                 return NULL;
  85
  86         soc_dev_attr->family = "Freescale i.MX";
  87
  88         root = of_find_node_by_path("/");
  89         ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
  90         of_node_put(root);
  91         if (ret)
  92                 goto free_soc;
  93
  94         switch (__mxc_cpu_type) {
  95         case MXC_CPU_MX1:
  96                 soc_id = "i.MX1";
  97                 break;
  98         case MXC_CPU_MX21:
  99                 soc_id = "i.MX21";
 100                 break;
 101         case MXC_CPU_MX25:
 102                 soc_id = "i.MX25";
 103                 break;
 104         case MXC_CPU_MX27:
 105                 soc_id = "i.MX27";
 106                 break;
 107         case MXC_CPU_MX31:
 108                 soc_id = "i.MX31";
 109                 break;
 110         case MXC_CPU_MX35:
 111                 soc_id = "i.MX35";
 112                 break;
 113         case MXC_CPU_MX51:
 114                 soc_id = "i.MX51";
 115                 break;
 116         case MXC_CPU_MX53:
 117                 soc_id = "i.MX53";
 118                 break;
 119         case MXC_CPU_IMX6SL:
 120                 soc_id = "i.MX6SL";
 121                 break;
 122         case MXC_CPU_IMX6DL:
 123                 soc_id = "i.MX6DL";
 124                 break;
 125         case MXC_CPU_IMX6SX:
 126                 soc_id = "i.MX6SX";
 127                 break;
 128         case MXC_CPU_IMX6Q:
 129                 soc_id = "i.MX6Q";
 130                 break;
 131         case MXC_CPU_IMX6UL:
 132                 soc_id = "i.MX6UL";
 133                 break;
 134         case MXC_CPU_IMX6ULL:
 135                 soc_id = "i.MX6ULL";
 136                 break;
 137         case MXC_CPU_IMX7D:
 138                 soc_id = "i.MX7D";
 139                 break;
 140         default:
 141                 soc_id = "Unknown";
 142         }
 143         soc_dev_attr->soc_id = soc_id;
 144
 145         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
 146                                            (imx_soc_revision >> 4) & 0xf,
 147                                            imx_soc_revision & 0xf);
 148         if (!soc_dev_attr->revision)
 149                 goto free_soc;
 150
 151         soc_dev = soc_device_register(soc_dev_attr);
 152         if (IS_ERR(soc_dev))
 153                 goto free_rev;
 154
 155         return soc_device_to_device(soc_dev);
 156
 157 free_rev:
 158         kfree(soc_dev_attr->revision);
 159 free_soc:
 160         kfree(soc_dev_attr);
 161         return NULL;
 162 }