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Revert "ALSA: hda: Flush interrupts on disabling"
[linux/fpc-iii.git] / drivers / infiniband / hw / cxgb4 / mem.c
blob2b1dd60a29fa32a4200189f13de67a84f5419823
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <rdma/ib_umem.h>
36 #include <linux/atomic.h>
37 #include <rdma/ib_user_verbs.h>
38
39 #include "iw_cxgb4.h"
40
41 int use_dsgl = 0;
42 module_param(use_dsgl, int, 0644);
43 MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=0)");
44
45 #define T4_ULPTX_MIN_IO 32
46 #define C4IW_MAX_INLINE_SIZE 96
47 #define T4_ULPTX_MAX_DMA 1024
48 #define C4IW_INLINE_THRESHOLD 128
49
50 static int inline_threshold = C4IW_INLINE_THRESHOLD;
51 module_param(inline_threshold, int, 0644);
52 MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)");
53
54 static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
55 {
56 return (is_t4(dev->rdev.lldi.adapter_type) ||
57 is_t5(dev->rdev.lldi.adapter_type)) &&
58 length >= 8*1024*1024*1024ULL;
59 }
60
61 static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
62 u32 len, dma_addr_t data,
63 int wait, struct sk_buff *skb)
64 {
65 struct ulp_mem_io *req;
66 struct ulptx_sgl *sgl;
67 u8 wr_len;
68 int ret = 0;
69 struct c4iw_wr_wait wr_wait;
70
71 addr &= 0x7FFFFFF;
72
73 if (wait)
74 c4iw_init_wr_wait(&wr_wait);
75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16);
76
77 if (!skb) {
78 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
79 if (!skb)
80 return -ENOMEM;
81 }
82 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
83
84 req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
85 memset(req, 0, wr_len);
86 INIT_ULPTX_WR(req, wr_len, 0, 0);
87 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
88 (wait ? FW_WR_COMPL_F : 0));
89 req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L;
90 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
91 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
92 T5_ULP_MEMIO_ORDER_V(1) |
93 T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0]));
94 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5));
95 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16));
96 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr));
97
98 sgl = (struct ulptx_sgl *)(req + 1);
99 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
100 ULPTX_NSGE_V(1));
101 sgl->len0 = cpu_to_be32(len);
102 sgl->addr0 = cpu_to_be64(data);
103
104 ret = c4iw_ofld_send(rdev, skb);
105 if (ret)
106 return ret;
107 if (wait)
108 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
109 return ret;
110 }
111
112 static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
113 void *data, struct sk_buff *skb)
114 {
115 struct ulp_mem_io *req;
116 struct ulptx_idata *sc;
117 u8 wr_len, *to_dp, *from_dp;
118 int copy_len, num_wqe, i, ret = 0;
119 struct c4iw_wr_wait wr_wait;
120 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
121
122 if (is_t4(rdev->lldi.adapter_type))
123 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F);
124 else
125 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F);
126
127 addr &= 0x7FFFFFF;
128 PDBG("%s addr 0x%x len %u\n", __func__, addr, len);
129 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
130 c4iw_init_wr_wait(&wr_wait);
131 for (i = 0; i < num_wqe; i++) {
132
133 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
134 len;
135 wr_len = roundup(sizeof *req + sizeof *sc +
136 roundup(copy_len, T4_ULPTX_MIN_IO), 16);
137
138 if (!skb) {
139 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
140 if (!skb)
141 return -ENOMEM;
142 }
143 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
144
145 req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
146 memset(req, 0, wr_len);
147 INIT_ULPTX_WR(req, wr_len, 0, 0);
148
149 if (i == (num_wqe-1)) {
150 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
151 FW_WR_COMPL_F);
152 req->wr.wr_lo = (__force __be64)(unsigned long)&wr_wait;
153 } else
154 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
155 req->wr.wr_mid = cpu_to_be32(
156 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
157
158 req->cmd = cmd;
159 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(
160 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
161 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr),
162 16));
163 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3));
164
165 sc = (struct ulptx_idata *)(req + 1);
166 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM));
167 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
168
169 to_dp = (u8 *)(sc + 1);
170 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
171 if (data)
172 memcpy(to_dp, from_dp, copy_len);
173 else
174 memset(to_dp, 0, copy_len);
175 if (copy_len % T4_ULPTX_MIN_IO)
176 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
177 (copy_len % T4_ULPTX_MIN_IO));
178 ret = c4iw_ofld_send(rdev, skb);
179 skb = NULL;
180 if (ret)
181 return ret;
182 len -= C4IW_MAX_INLINE_SIZE;
183 }
184
185 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
186 return ret;
187 }
188
189 static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len,
190 void *data, struct sk_buff *skb)
191 {
192 u32 remain = len;
193 u32 dmalen;
194 int ret = 0;
195 dma_addr_t daddr;
196 dma_addr_t save;
197
198 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE);
199 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr))
200 return -1;
201 save = daddr;
202
203 while (remain > inline_threshold) {
204 if (remain < T4_ULPTX_MAX_DMA) {
205 if (remain & ~T4_ULPTX_MIN_IO)
206 dmalen = remain & ~(T4_ULPTX_MIN_IO-1);
207 else
208 dmalen = remain;
209 } else
210 dmalen = T4_ULPTX_MAX_DMA;
211 remain -= dmalen;
212 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
213 !remain, skb);
214 if (ret)
215 goto out;
216 addr += dmalen >> 5;
217 data += dmalen;
218 daddr += dmalen;
219 }
220 if (remain)
221 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb);
222 out:
223 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
224 return ret;
225 }
226
227 /*
228 * write len bytes of data into addr (32B aligned address)
229 * If data is NULL, clear len byte of memory to zero.
230 */
231 static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
232 void *data, struct sk_buff *skb)
233 {
234 if (is_t5(rdev->lldi.adapter_type) && use_dsgl) {
235 if (len > inline_threshold) {
236 if (_c4iw_write_mem_dma(rdev, addr, len, data, skb)) {
237 printk_ratelimited(KERN_WARNING
238 "%s: dma map"
239 " failure (non fatal)\n",
240 pci_name(rdev->lldi.pdev));
241 return _c4iw_write_mem_inline(rdev, addr, len,
242 data, skb);
243 } else {
244 return 0;
245 }
246 } else
247 return _c4iw_write_mem_inline(rdev, addr,
248 len, data, skb);
249 } else
250 return _c4iw_write_mem_inline(rdev, addr, len, data, skb);
251 }
252
253 /*
254 * Build and write a TPT entry.
255 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size,
256 * pbl_size and pbl_addr
257 * OUT: stag index
258 */
259 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
260 u32 *stag, u8 stag_state, u32 pdid,
261 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
262 int bind_enabled, u32 zbva, u64 to,
263 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr,
264 struct sk_buff *skb)
265 {
266 int err;
267 struct fw_ri_tpte *tpt;
268 u32 stag_idx;
269 static atomic_t key;
270
271 if (c4iw_fatal_error(rdev))
272 return -EIO;
273
274 tpt = kmalloc(sizeof(*tpt), GFP_KERNEL);
275 if (!tpt)
276 return -ENOMEM;
277
278 stag_state = stag_state > 0;
279 stag_idx = (*stag) >> 8;
280
281 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
282 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
283 if (!stag_idx) {
284 mutex_lock(&rdev->stats.lock);
285 rdev->stats.stag.fail++;
286 mutex_unlock(&rdev->stats.lock);
287 kfree(tpt);
288 return -ENOMEM;
289 }
290 mutex_lock(&rdev->stats.lock);
291 rdev->stats.stag.cur += 32;
292 if (rdev->stats.stag.cur > rdev->stats.stag.max)
293 rdev->stats.stag.max = rdev->stats.stag.cur;
294 mutex_unlock(&rdev->stats.lock);
295 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
296 }
297 PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
298 __func__, stag_state, type, pdid, stag_idx);
299
300 /* write TPT entry */
301 if (reset_tpt_entry)
302 memset(tpt, 0, sizeof(*tpt));
303 else {
304 tpt->valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
305 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) |
306 FW_RI_TPTE_STAGSTATE_V(stag_state) |
307 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid));
308 tpt->locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) |
309 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) |
310 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO :
311 FW_RI_VA_BASED_TO))|
312 FW_RI_TPTE_PS_V(page_size));
313 tpt->nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
314 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3));
315 tpt->len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
316 tpt->va_hi = cpu_to_be32((u32)(to >> 32));
317 tpt->va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
318 tpt->dca_mwbcnt_pstag = cpu_to_be32(0);
319 tpt->len_hi = cpu_to_be32((u32)(len >> 32));
320 }
321 err = write_adapter_mem(rdev, stag_idx +
322 (rdev->lldi.vr->stag.start >> 5),
323 sizeof(*tpt), tpt, skb);
324
325 if (reset_tpt_entry) {
326 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
327 mutex_lock(&rdev->stats.lock);
328 rdev->stats.stag.cur -= 32;
329 mutex_unlock(&rdev->stats.lock);
330 }
331 kfree(tpt);
332 return err;
333 }
334
335 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
336 u32 pbl_addr, u32 pbl_size)
337 {
338 int err;
339
340 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
341 __func__, pbl_addr, rdev->lldi.vr->pbl.start,
342 pbl_size);
343
344 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL);
345 return err;
346 }
347
348 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
349 u32 pbl_addr, struct sk_buff *skb)
350 {
351 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
352 pbl_size, pbl_addr, skb);
353 }
354
355 static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid)
356 {
357 *stag = T4_STAG_UNSET;
358 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
359 0UL, 0, 0, 0, 0, NULL);
360 }
361
362 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag,
363 struct sk_buff *skb)
364 {
365 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
366 0, skb);
367 }
368
369 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
370 u32 pbl_size, u32 pbl_addr)
371 {
372 *stag = T4_STAG_UNSET;
373 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
374 0UL, 0, 0, pbl_size, pbl_addr, NULL);
375 }
376
377 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
378 {
379 u32 mmid;
380
381 mhp->attr.state = 1;
382 mhp->attr.stag = stag;
383 mmid = stag >> 8;
384 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
385 PDBG("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp);
386 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
387 }
388
389 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
390 struct c4iw_mr *mhp, int shift)
391 {
392 u32 stag = T4_STAG_UNSET;
393 int ret;
394
395 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
396 FW_RI_STAG_NSMR, mhp->attr.len ?
397 mhp->attr.perms : 0,
398 mhp->attr.mw_bind_enable, mhp->attr.zbva,
399 mhp->attr.va_fbo, mhp->attr.len ?
400 mhp->attr.len : -1, shift - 12,
401 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL);
402 if (ret)
403 return ret;
404
405 ret = finish_mem_reg(mhp, stag);
406 if (ret) {
407 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
408 mhp->attr.pbl_addr, mhp->dereg_skb);
409 mhp->dereg_skb = NULL;
410 }
411 return ret;
412 }
413
414 static int alloc_pbl(struct c4iw_mr *mhp, int npages)
415 {
416 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
417 npages << 3);
418
419 if (!mhp->attr.pbl_addr)
420 return -ENOMEM;
421
422 mhp->attr.pbl_size = npages;
423
424 return 0;
425 }
426
427 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
428 {
429 struct c4iw_dev *rhp;
430 struct c4iw_pd *php;
431 struct c4iw_mr *mhp;
432 int ret;
433 u32 stag = T4_STAG_UNSET;
434
435 PDBG("%s ib_pd %p\n", __func__, pd);
436 php = to_c4iw_pd(pd);
437 rhp = php->rhp;
438
439 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
440 if (!mhp)
441 return ERR_PTR(-ENOMEM);
442
443 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
444 if (!mhp->dereg_skb) {
445 ret = -ENOMEM;
446 goto err0;
447 }
448
449 mhp->rhp = rhp;
450 mhp->attr.pdid = php->pdid;
451 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
452 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
453 mhp->attr.zbva = 0;
454 mhp->attr.va_fbo = 0;
455 mhp->attr.page_size = 0;
456 mhp->attr.len = ~0ULL;
457 mhp->attr.pbl_size = 0;
458
459 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
460 FW_RI_STAG_NSMR, mhp->attr.perms,
461 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0,
462 NULL);
463 if (ret)
464 goto err1;
465
466 ret = finish_mem_reg(mhp, stag);
467 if (ret)
468 goto err2;
469 return &mhp->ibmr;
470 err2:
471 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
472 mhp->attr.pbl_addr, mhp->dereg_skb);
473 err1:
474 kfree_skb(mhp->dereg_skb);
475 err0:
476 kfree(mhp);
477 return ERR_PTR(ret);
478 }
479
480 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
481 u64 virt, int acc, struct ib_udata *udata)
482 {
483 __be64 *pages;
484 int shift, n, len;
485 int i, k, entry;
486 int err = 0;
487 struct scatterlist *sg;
488 struct c4iw_dev *rhp;
489 struct c4iw_pd *php;
490 struct c4iw_mr *mhp;
491
492 PDBG("%s ib_pd %p\n", __func__, pd);
493
494 if (length == ~0ULL)
495 return ERR_PTR(-EINVAL);
496
497 if ((length + start) < start)
498 return ERR_PTR(-EINVAL);
499
500 php = to_c4iw_pd(pd);
501 rhp = php->rhp;
502
503 if (mr_exceeds_hw_limits(rhp, length))
504 return ERR_PTR(-EINVAL);
505
506 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
507 if (!mhp)
508 return ERR_PTR(-ENOMEM);
509
510 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
511 if (!mhp->dereg_skb) {
512 kfree(mhp);
513 return ERR_PTR(-ENOMEM);
514 }
515
516 mhp->rhp = rhp;
517
518 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0);
519 if (IS_ERR(mhp->umem)) {
520 err = PTR_ERR(mhp->umem);
521 kfree_skb(mhp->dereg_skb);
522 kfree(mhp);
523 return ERR_PTR(err);
524 }
525
526 shift = ffs(mhp->umem->page_size) - 1;
527
528 n = mhp->umem->nmap;
529 err = alloc_pbl(mhp, n);
530 if (err)
531 goto err;
532
533 pages = (__be64 *) __get_free_page(GFP_KERNEL);
534 if (!pages) {
535 err = -ENOMEM;
536 goto err_pbl;
537 }
538
539 i = n = 0;
540
541 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) {
542 len = sg_dma_len(sg) >> shift;
543 for (k = 0; k < len; ++k) {
544 pages[i++] = cpu_to_be64(sg_dma_address(sg) +
545 mhp->umem->page_size * k);
546 if (i == PAGE_SIZE / sizeof *pages) {
547 err = write_pbl(&mhp->rhp->rdev,
548 pages,
549 mhp->attr.pbl_addr + (n << 3), i);
550 if (err)
551 goto pbl_done;
552 n += i;
553 i = 0;
554 }
555 }
556 }
557
558 if (i)
559 err = write_pbl(&mhp->rhp->rdev, pages,
560 mhp->attr.pbl_addr + (n << 3), i);
561
562 pbl_done:
563 free_page((unsigned long) pages);
564 if (err)
565 goto err_pbl;
566
567 mhp->attr.pdid = php->pdid;
568 mhp->attr.zbva = 0;
569 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
570 mhp->attr.va_fbo = virt;
571 mhp->attr.page_size = shift - 12;
572 mhp->attr.len = length;
573
574 err = register_mem(rhp, php, mhp, shift);
575 if (err)
576 goto err_pbl;
577
578 return &mhp->ibmr;
579
580 err_pbl:
581 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
582 mhp->attr.pbl_size << 3);
583
584 err:
585 ib_umem_release(mhp->umem);
586 kfree_skb(mhp->dereg_skb);
587 kfree(mhp);
588 return ERR_PTR(err);
589 }
590
591 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
592 struct ib_udata *udata)
593 {
594 struct c4iw_dev *rhp;
595 struct c4iw_pd *php;
596 struct c4iw_mw *mhp;
597 u32 mmid;
598 u32 stag = 0;
599 int ret;
600
601 if (type != IB_MW_TYPE_1)
602 return ERR_PTR(-EINVAL);
603
604 php = to_c4iw_pd(pd);
605 rhp = php->rhp;
606 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
607 if (!mhp)
608 return ERR_PTR(-ENOMEM);
609
610 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
611 if (!mhp->dereg_skb) {
612 ret = -ENOMEM;
613 goto free_mhp;
614 }
615
616 ret = allocate_window(&rhp->rdev, &stag, php->pdid);
617 if (ret)
618 goto free_skb;
619 mhp->rhp = rhp;
620 mhp->attr.pdid = php->pdid;
621 mhp->attr.type = FW_RI_STAG_MW;
622 mhp->attr.stag = stag;
623 mmid = (stag) >> 8;
624 mhp->ibmw.rkey = stag;
625 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
626 ret = -ENOMEM;
627 goto dealloc_win;
628 }
629 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
630 return &(mhp->ibmw);
631
632 dealloc_win:
633 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb);
634 free_skb:
635 kfree_skb(mhp->dereg_skb);
636 free_mhp:
637 kfree(mhp);
638 return ERR_PTR(ret);
639 }
640
641 int c4iw_dealloc_mw(struct ib_mw *mw)
642 {
643 struct c4iw_dev *rhp;
644 struct c4iw_mw *mhp;
645 u32 mmid;
646
647 mhp = to_c4iw_mw(mw);
648 rhp = mhp->rhp;
649 mmid = (mw->rkey) >> 8;
650 remove_handle(rhp, &rhp->mmidr, mmid);
651 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb);
652 kfree_skb(mhp->dereg_skb);
653 kfree(mhp);
654 PDBG("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp);
655 return 0;
656 }
657
658 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
659 enum ib_mr_type mr_type,
660 u32 max_num_sg)
661 {
662 struct c4iw_dev *rhp;
663 struct c4iw_pd *php;
664 struct c4iw_mr *mhp;
665 u32 mmid;
666 u32 stag = 0;
667 int ret = 0;
668 int length = roundup(max_num_sg * sizeof(u64), 32);
669
670 php = to_c4iw_pd(pd);
671 rhp = php->rhp;
672
673 if (mr_type != IB_MR_TYPE_MEM_REG ||
674 max_num_sg > t4_max_fr_depth(&rhp->rdev.lldi.ulptx_memwrite_dsgl &&
675 use_dsgl))
676 return ERR_PTR(-EINVAL);
677
678 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
679 if (!mhp) {
680 ret = -ENOMEM;
681 goto err;
682 }
683
684 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev,
685 length, &mhp->mpl_addr, GFP_KERNEL);
686 if (!mhp->mpl) {
687 ret = -ENOMEM;
688 goto err_mpl;
689 }
690 mhp->max_mpl_len = length;
691
692 mhp->rhp = rhp;
693 ret = alloc_pbl(mhp, max_num_sg);
694 if (ret)
695 goto err1;
696 mhp->attr.pbl_size = max_num_sg;
697 ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
698 mhp->attr.pbl_size, mhp->attr.pbl_addr);
699 if (ret)
700 goto err2;
701 mhp->attr.pdid = php->pdid;
702 mhp->attr.type = FW_RI_STAG_NSMR;
703 mhp->attr.stag = stag;
704 mhp->attr.state = 0;
705 mmid = (stag) >> 8;
706 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
707 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
708 ret = -ENOMEM;
709 goto err3;
710 }
711
712 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
713 return &(mhp->ibmr);
714 err3:
715 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
716 mhp->attr.pbl_addr, mhp->dereg_skb);
717 err2:
718 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
719 mhp->attr.pbl_size << 3);
720 err1:
721 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
722 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
723 err_mpl:
724 kfree(mhp);
725 err:
726 return ERR_PTR(ret);
727 }
728
729 static int c4iw_set_page(struct ib_mr *ibmr, u64 addr)
730 {
731 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
732
733 if (unlikely(mhp->mpl_len == mhp->attr.pbl_size))
734 return -ENOMEM;
735
736 mhp->mpl[mhp->mpl_len++] = addr;
737
738 return 0;
739 }
740
741 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
742 unsigned int *sg_offset)
743 {
744 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
745
746 mhp->mpl_len = 0;
747
748 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page);
749 }
750
751 int c4iw_dereg_mr(struct ib_mr *ib_mr)
752 {
753 struct c4iw_dev *rhp;
754 struct c4iw_mr *mhp;
755 u32 mmid;
756
757 PDBG("%s ib_mr %p\n", __func__, ib_mr);
758
759 mhp = to_c4iw_mr(ib_mr);
760 rhp = mhp->rhp;
761 mmid = mhp->attr.stag >> 8;
762 remove_handle(rhp, &rhp->mmidr, mmid);
763 if (mhp->mpl)
764 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
765 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
766 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
767 mhp->attr.pbl_addr, mhp->dereg_skb);
768 if (mhp->attr.pbl_size)
769 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
770 mhp->attr.pbl_size << 3);
771 if (mhp->kva)
772 kfree((void *) (unsigned long) mhp->kva);
773 if (mhp->umem)
774 ib_umem_release(mhp->umem);
775 PDBG("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp);
776 kfree(mhp);
777 return 0;
778 }
779
780 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey)
781 {
782 struct c4iw_mr *mhp;
783 unsigned long flags;
784
785 spin_lock_irqsave(&rhp->lock, flags);
786 mhp = get_mhp(rhp, rkey >> 8);
787 if (mhp)
788 mhp->attr.state = 0;
789 spin_unlock_irqrestore(&rhp->lock, flags);
790 }
Linux with added FPC-III support