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Revert "ALSA: hda: Flush interrupts on disabling"
[linux/fpc-iii.git] / drivers / infiniband / hw / mlx5 / main.c
blobf94df0e6a0f2ee09ec28d0a28da2778f88151d81
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
41 #include <asm/pat.h>
42 #endif
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
53 #include <linux/in.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
56 #include "mlx5_ib.h"
57
58 #define DRIVER_NAME "mlx5_ib"
59 #define DRIVER_VERSION "2.2-1"
60 #define DRIVER_RELDATE "Feb 2014"
61
62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_VERSION(DRIVER_VERSION);
66
67 static int deprecated_prof_sel = 2;
68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
70
71 static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
74
75 enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77 };
78
79 static enum rdma_link_layer
80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
81 {
82 switch (port_type_cap) {
83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90 }
91
92 static enum rdma_link_layer
93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94 {
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99 }
100
101 static int mlx5_netdev_event(struct notifier_block *this,
102 unsigned long event, void *ptr)
103 {
104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
106 roce.nb);
107
108 switch (event) {
109 case NETDEV_REGISTER:
110 case NETDEV_UNREGISTER:
111 write_lock(&ibdev->roce.netdev_lock);
112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
114 NULL : ndev;
115 write_unlock(&ibdev->roce.netdev_lock);
116 break;
117
118 case NETDEV_UP:
119 case NETDEV_DOWN: {
120 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
121 struct net_device *upper = NULL;
122
123 if (lag_ndev) {
124 upper = netdev_master_upper_dev_get(lag_ndev);
125 dev_put(lag_ndev);
126 }
127
128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
129 && ibdev->ib_active) {
130 struct ib_event ibev = {0};
131
132 ibev.device = &ibdev->ib_dev;
133 ibev.event = (event == NETDEV_UP) ?
134 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
135 ibev.element.port_num = 1;
136 ib_dispatch_event(&ibev);
137 }
138 break;
139 }
140
141 default:
142 break;
143 }
144
145 return NOTIFY_DONE;
146 }
147
148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
149 u8 port_num)
150 {
151 struct mlx5_ib_dev *ibdev = to_mdev(device);
152 struct net_device *ndev;
153
154 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
155 if (ndev)
156 return ndev;
157
158 /* Ensure ndev does not disappear before we invoke dev_hold()
159 */
160 read_lock(&ibdev->roce.netdev_lock);
161 ndev = ibdev->roce.netdev;
162 if (ndev)
163 dev_hold(ndev);
164 read_unlock(&ibdev->roce.netdev_lock);
165
166 return ndev;
167 }
168
169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
170 struct ib_port_attr *props)
171 {
172 struct mlx5_ib_dev *dev = to_mdev(device);
173 struct net_device *ndev, *upper;
174 enum ib_mtu ndev_ib_mtu;
175 u16 qkey_viol_cntr;
176
177 memset(props, 0, sizeof(*props));
178
179 props->port_cap_flags |= IB_PORT_CM_SUP;
180 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
181
182 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
183 roce_address_table_size);
184 props->max_mtu = IB_MTU_4096;
185 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
186 props->pkey_tbl_len = 1;
187 props->state = IB_PORT_DOWN;
188 props->phys_state = 3;
189
190 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
191 props->qkey_viol_cntr = qkey_viol_cntr;
192
193 ndev = mlx5_ib_get_netdev(device, port_num);
194 if (!ndev)
195 return 0;
196
197 if (mlx5_lag_is_active(dev->mdev)) {
198 rcu_read_lock();
199 upper = netdev_master_upper_dev_get_rcu(ndev);
200 if (upper) {
201 dev_put(ndev);
202 ndev = upper;
203 dev_hold(ndev);
204 }
205 rcu_read_unlock();
206 }
207
208 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
209 props->state = IB_PORT_ACTIVE;
210 props->phys_state = 5;
211 }
212
213 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
214
215 dev_put(ndev);
216
217 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
218
219 props->active_width = IB_WIDTH_4X; /* TODO */
220 props->active_speed = IB_SPEED_QDR; /* TODO */
221
222 return 0;
223 }
224
225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
226 const struct ib_gid_attr *attr,
227 void *mlx5_addr)
228 {
229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
230 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
231 source_l3_address);
232 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
233 source_mac_47_32);
234
235 if (!gid)
236 return;
237
238 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
239
240 if (is_vlan_dev(attr->ndev)) {
241 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
242 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
243 }
244
245 switch (attr->gid_type) {
246 case IB_GID_TYPE_IB:
247 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
248 break;
249 case IB_GID_TYPE_ROCE_UDP_ENCAP:
250 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
251 break;
252
253 default:
254 WARN_ON(true);
255 }
256
257 if (attr->gid_type != IB_GID_TYPE_IB) {
258 if (ipv6_addr_v4mapped((void *)gid))
259 MLX5_SET_RA(mlx5_addr, roce_l3_type,
260 MLX5_ROCE_L3_TYPE_IPV4);
261 else
262 MLX5_SET_RA(mlx5_addr, roce_l3_type,
263 MLX5_ROCE_L3_TYPE_IPV6);
264 }
265
266 if ((attr->gid_type == IB_GID_TYPE_IB) ||
267 !ipv6_addr_v4mapped((void *)gid))
268 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
269 else
270 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
271 }
272
273 static int set_roce_addr(struct ib_device *device, u8 port_num,
274 unsigned int index,
275 const union ib_gid *gid,
276 const struct ib_gid_attr *attr)
277 {
278 struct mlx5_ib_dev *dev = to_mdev(device);
279 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
280 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
281 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
282 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
283
284 if (ll != IB_LINK_LAYER_ETHERNET)
285 return -EINVAL;
286
287 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
288
289 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
290 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
291 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
292 }
293
294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
295 unsigned int index, const union ib_gid *gid,
296 const struct ib_gid_attr *attr,
297 __always_unused void **context)
298 {
299 return set_roce_addr(device, port_num, index, gid, attr);
300 }
301
302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
303 unsigned int index, __always_unused void **context)
304 {
305 return set_roce_addr(device, port_num, index, NULL, NULL);
306 }
307
308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
309 int index)
310 {
311 struct ib_gid_attr attr;
312 union ib_gid gid;
313
314 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
315 return 0;
316
317 if (!attr.ndev)
318 return 0;
319
320 dev_put(attr.ndev);
321
322 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
323 return 0;
324
325 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
326 }
327
328 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
329 int index, enum ib_gid_type *gid_type)
330 {
331 struct ib_gid_attr attr;
332 union ib_gid gid;
333 int ret;
334
335 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
336 if (ret)
337 return ret;
338
339 if (!attr.ndev)
340 return -ENODEV;
341
342 dev_put(attr.ndev);
343
344 *gid_type = attr.gid_type;
345
346 return 0;
347 }
348
349 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
350 {
351 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
352 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
353 return 0;
354 }
355
356 enum {
357 MLX5_VPORT_ACCESS_METHOD_MAD,
358 MLX5_VPORT_ACCESS_METHOD_HCA,
359 MLX5_VPORT_ACCESS_METHOD_NIC,
360 };
361
362 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
363 {
364 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
365 return MLX5_VPORT_ACCESS_METHOD_MAD;
366
367 if (mlx5_ib_port_link_layer(ibdev, 1) ==
368 IB_LINK_LAYER_ETHERNET)
369 return MLX5_VPORT_ACCESS_METHOD_NIC;
370
371 return MLX5_VPORT_ACCESS_METHOD_HCA;
372 }
373
374 static void get_atomic_caps(struct mlx5_ib_dev *dev,
375 struct ib_device_attr *props)
376 {
377 u8 tmp;
378 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
379 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
380 u8 atomic_req_8B_endianness_mode =
381 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
382
383 /* Check if HW supports 8 bytes standard atomic operations and capable
384 * of host endianness respond
385 */
386 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
387 if (((atomic_operations & tmp) == tmp) &&
388 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
389 (atomic_req_8B_endianness_mode)) {
390 props->atomic_cap = IB_ATOMIC_HCA;
391 } else {
392 props->atomic_cap = IB_ATOMIC_NONE;
393 }
394 }
395
396 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
397 __be64 *sys_image_guid)
398 {
399 struct mlx5_ib_dev *dev = to_mdev(ibdev);
400 struct mlx5_core_dev *mdev = dev->mdev;
401 u64 tmp;
402 int err;
403
404 switch (mlx5_get_vport_access_method(ibdev)) {
405 case MLX5_VPORT_ACCESS_METHOD_MAD:
406 return mlx5_query_mad_ifc_system_image_guid(ibdev,
407 sys_image_guid);
408
409 case MLX5_VPORT_ACCESS_METHOD_HCA:
410 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
411 break;
412
413 case MLX5_VPORT_ACCESS_METHOD_NIC:
414 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 if (!err)
422 *sys_image_guid = cpu_to_be64(tmp);
423
424 return err;
425
426 }
427
428 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
429 u16 *max_pkeys)
430 {
431 struct mlx5_ib_dev *dev = to_mdev(ibdev);
432 struct mlx5_core_dev *mdev = dev->mdev;
433
434 switch (mlx5_get_vport_access_method(ibdev)) {
435 case MLX5_VPORT_ACCESS_METHOD_MAD:
436 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
437
438 case MLX5_VPORT_ACCESS_METHOD_HCA:
439 case MLX5_VPORT_ACCESS_METHOD_NIC:
440 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
441 pkey_table_size));
442 return 0;
443
444 default:
445 return -EINVAL;
446 }
447 }
448
449 static int mlx5_query_vendor_id(struct ib_device *ibdev,
450 u32 *vendor_id)
451 {
452 struct mlx5_ib_dev *dev = to_mdev(ibdev);
453
454 switch (mlx5_get_vport_access_method(ibdev)) {
455 case MLX5_VPORT_ACCESS_METHOD_MAD:
456 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
457
458 case MLX5_VPORT_ACCESS_METHOD_HCA:
459 case MLX5_VPORT_ACCESS_METHOD_NIC:
460 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
461
462 default:
463 return -EINVAL;
464 }
465 }
466
467 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
468 __be64 *node_guid)
469 {
470 u64 tmp;
471 int err;
472
473 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
474 case MLX5_VPORT_ACCESS_METHOD_MAD:
475 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
476
477 case MLX5_VPORT_ACCESS_METHOD_HCA:
478 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
479 break;
480
481 case MLX5_VPORT_ACCESS_METHOD_NIC:
482 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
483 break;
484
485 default:
486 return -EINVAL;
487 }
488
489 if (!err)
490 *node_guid = cpu_to_be64(tmp);
491
492 return err;
493 }
494
495 struct mlx5_reg_node_desc {
496 u8 desc[IB_DEVICE_NODE_DESC_MAX];
497 };
498
499 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
500 {
501 struct mlx5_reg_node_desc in;
502
503 if (mlx5_use_mad_ifc(dev))
504 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
505
506 memset(&in, 0, sizeof(in));
507
508 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
509 sizeof(struct mlx5_reg_node_desc),
510 MLX5_REG_NODE_DESC, 0, 0);
511 }
512
513 static int mlx5_ib_query_device(struct ib_device *ibdev,
514 struct ib_device_attr *props,
515 struct ib_udata *uhw)
516 {
517 struct mlx5_ib_dev *dev = to_mdev(ibdev);
518 struct mlx5_core_dev *mdev = dev->mdev;
519 int err = -ENOMEM;
520 int max_sq_desc;
521 int max_rq_sg;
522 int max_sq_sg;
523 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
524 struct mlx5_ib_query_device_resp resp = {};
525 size_t resp_len;
526 u64 max_tso;
527
528 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
529 if (uhw->outlen && uhw->outlen < resp_len)
530 return -EINVAL;
531 else
532 resp.response_length = resp_len;
533
534 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
535 return -EINVAL;
536
537 memset(props, 0, sizeof(*props));
538 err = mlx5_query_system_image_guid(ibdev,
539 &props->sys_image_guid);
540 if (err)
541 return err;
542
543 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
544 if (err)
545 return err;
546
547 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
548 if (err)
549 return err;
550
551 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
552 (fw_rev_min(dev->mdev) << 16) |
553 fw_rev_sub(dev->mdev);
554 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
555 IB_DEVICE_PORT_ACTIVE_EVENT |
556 IB_DEVICE_SYS_IMAGE_GUID |
557 IB_DEVICE_RC_RNR_NAK_GEN;
558
559 if (MLX5_CAP_GEN(mdev, pkv))
560 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
561 if (MLX5_CAP_GEN(mdev, qkv))
562 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
563 if (MLX5_CAP_GEN(mdev, apm))
564 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
565 if (MLX5_CAP_GEN(mdev, xrc))
566 props->device_cap_flags |= IB_DEVICE_XRC;
567 if (MLX5_CAP_GEN(mdev, imaicl)) {
568 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
569 IB_DEVICE_MEM_WINDOW_TYPE_2B;
570 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
571 /* We support 'Gappy' memory registration too */
572 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
573 }
574 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
575 if (MLX5_CAP_GEN(mdev, sho)) {
576 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
577 /* At this stage no support for signature handover */
578 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
579 IB_PROT_T10DIF_TYPE_2 |
580 IB_PROT_T10DIF_TYPE_3;
581 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
582 IB_GUARD_T10DIF_CSUM;
583 }
584 if (MLX5_CAP_GEN(mdev, block_lb_mc))
585 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
586
587 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
588 if (MLX5_CAP_ETH(mdev, csum_cap))
589 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
590
591 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
592 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
593 if (max_tso) {
594 resp.tso_caps.max_tso = 1 << max_tso;
595 resp.tso_caps.supported_qpts |=
596 1 << IB_QPT_RAW_PACKET;
597 resp.response_length += sizeof(resp.tso_caps);
598 }
599 }
600
601 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
602 resp.rss_caps.rx_hash_function =
603 MLX5_RX_HASH_FUNC_TOEPLITZ;
604 resp.rss_caps.rx_hash_fields_mask =
605 MLX5_RX_HASH_SRC_IPV4 |
606 MLX5_RX_HASH_DST_IPV4 |
607 MLX5_RX_HASH_SRC_IPV6 |
608 MLX5_RX_HASH_DST_IPV6 |
609 MLX5_RX_HASH_SRC_PORT_TCP |
610 MLX5_RX_HASH_DST_PORT_TCP |
611 MLX5_RX_HASH_SRC_PORT_UDP |
612 MLX5_RX_HASH_DST_PORT_UDP;
613 resp.response_length += sizeof(resp.rss_caps);
614 }
615 } else {
616 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
617 resp.response_length += sizeof(resp.tso_caps);
618 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
619 resp.response_length += sizeof(resp.rss_caps);
620 }
621
622 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
623 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
624 props->device_cap_flags |= IB_DEVICE_UD_TSO;
625 }
626
627 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
628 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
629 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
630
631 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
632 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
633
634 props->vendor_part_id = mdev->pdev->device;
635 props->hw_ver = mdev->pdev->revision;
636
637 props->max_mr_size = ~0ull;
638 props->page_size_cap = ~(min_page_size - 1);
639 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
640 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
641 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
642 sizeof(struct mlx5_wqe_data_seg);
643 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
644 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
645 sizeof(struct mlx5_wqe_raddr_seg)) /
646 sizeof(struct mlx5_wqe_data_seg);
647 props->max_sge = min(max_rq_sg, max_sq_sg);
648 props->max_sge_rd = MLX5_MAX_SGE_RD;
649 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
650 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
651 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
652 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
653 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
654 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
655 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
656 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
657 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
658 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
659 props->max_srq_sge = max_rq_sg - 1;
660 props->max_fast_reg_page_list_len =
661 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
662 get_atomic_caps(dev, props);
663 props->masked_atomic_cap = IB_ATOMIC_NONE;
664 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
665 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
666 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
667 props->max_mcast_grp;
668 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
669 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
670 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
671
672 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
673 if (MLX5_CAP_GEN(mdev, pg))
674 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
675 props->odp_caps = dev->odp_caps;
676 #endif
677
678 if (MLX5_CAP_GEN(mdev, cd))
679 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
680
681 if (!mlx5_core_is_pf(mdev))
682 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
683
684 if (mlx5_ib_port_link_layer(ibdev, 1) ==
685 IB_LINK_LAYER_ETHERNET) {
686 props->rss_caps.max_rwq_indirection_tables =
687 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
688 props->rss_caps.max_rwq_indirection_table_size =
689 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
690 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
691 props->max_wq_type_rq =
692 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
693 }
694
695 if (uhw->outlen) {
696 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
697
698 if (err)
699 return err;
700 }
701
702 return 0;
703 }
704
705 enum mlx5_ib_width {
706 MLX5_IB_WIDTH_1X = 1 << 0,
707 MLX5_IB_WIDTH_2X = 1 << 1,
708 MLX5_IB_WIDTH_4X = 1 << 2,
709 MLX5_IB_WIDTH_8X = 1 << 3,
710 MLX5_IB_WIDTH_12X = 1 << 4
711 };
712
713 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
714 u8 *ib_width)
715 {
716 struct mlx5_ib_dev *dev = to_mdev(ibdev);
717
718 if (active_width & MLX5_IB_WIDTH_1X)
719 *ib_width = IB_WIDTH_1X;
720 else if (active_width & MLX5_IB_WIDTH_4X)
721 *ib_width = IB_WIDTH_4X;
722 else if (active_width & MLX5_IB_WIDTH_8X)
723 *ib_width = IB_WIDTH_8X;
724 else if (active_width & MLX5_IB_WIDTH_12X)
725 *ib_width = IB_WIDTH_12X;
726 else {
727 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
728 (int)active_width);
729 *ib_width = IB_WIDTH_4X;
730 }
731
732 return;
733 }
734
735 static int mlx5_mtu_to_ib_mtu(int mtu)
736 {
737 switch (mtu) {
738 case 256: return 1;
739 case 512: return 2;
740 case 1024: return 3;
741 case 2048: return 4;
742 case 4096: return 5;
743 default:
744 pr_warn("invalid mtu\n");
745 return -1;
746 }
747 }
748
749 enum ib_max_vl_num {
750 __IB_MAX_VL_0 = 1,
751 __IB_MAX_VL_0_1 = 2,
752 __IB_MAX_VL_0_3 = 3,
753 __IB_MAX_VL_0_7 = 4,
754 __IB_MAX_VL_0_14 = 5,
755 };
756
757 enum mlx5_vl_hw_cap {
758 MLX5_VL_HW_0 = 1,
759 MLX5_VL_HW_0_1 = 2,
760 MLX5_VL_HW_0_2 = 3,
761 MLX5_VL_HW_0_3 = 4,
762 MLX5_VL_HW_0_4 = 5,
763 MLX5_VL_HW_0_5 = 6,
764 MLX5_VL_HW_0_6 = 7,
765 MLX5_VL_HW_0_7 = 8,
766 MLX5_VL_HW_0_14 = 15
767 };
768
769 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
770 u8 *max_vl_num)
771 {
772 switch (vl_hw_cap) {
773 case MLX5_VL_HW_0:
774 *max_vl_num = __IB_MAX_VL_0;
775 break;
776 case MLX5_VL_HW_0_1:
777 *max_vl_num = __IB_MAX_VL_0_1;
778 break;
779 case MLX5_VL_HW_0_3:
780 *max_vl_num = __IB_MAX_VL_0_3;
781 break;
782 case MLX5_VL_HW_0_7:
783 *max_vl_num = __IB_MAX_VL_0_7;
784 break;
785 case MLX5_VL_HW_0_14:
786 *max_vl_num = __IB_MAX_VL_0_14;
787 break;
788
789 default:
790 return -EINVAL;
791 }
792
793 return 0;
794 }
795
796 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
797 struct ib_port_attr *props)
798 {
799 struct mlx5_ib_dev *dev = to_mdev(ibdev);
800 struct mlx5_core_dev *mdev = dev->mdev;
801 struct mlx5_hca_vport_context *rep;
802 u16 max_mtu;
803 u16 oper_mtu;
804 int err;
805 u8 ib_link_width_oper;
806 u8 vl_hw_cap;
807
808 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
809 if (!rep) {
810 err = -ENOMEM;
811 goto out;
812 }
813
814 memset(props, 0, sizeof(*props));
815
816 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
817 if (err)
818 goto out;
819
820 props->lid = rep->lid;
821 props->lmc = rep->lmc;
822 props->sm_lid = rep->sm_lid;
823 props->sm_sl = rep->sm_sl;
824 props->state = rep->vport_state;
825 props->phys_state = rep->port_physical_state;
826 props->port_cap_flags = rep->cap_mask1;
827 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
828 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
829 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
830 props->bad_pkey_cntr = rep->pkey_violation_counter;
831 props->qkey_viol_cntr = rep->qkey_violation_counter;
832 props->subnet_timeout = rep->subnet_timeout;
833 props->init_type_reply = rep->init_type_reply;
834 props->grh_required = rep->grh_required;
835
836 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
837 if (err)
838 goto out;
839
840 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
841
842 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
843 if (err)
844 goto out;
845
846 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
847
848 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
849
850 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
851
852 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
853
854 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
855 if (err)
856 goto out;
857
858 err = translate_max_vl_num(ibdev, vl_hw_cap,
859 &props->max_vl_num);
860 out:
861 kfree(rep);
862 return err;
863 }
864
865 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
866 struct ib_port_attr *props)
867 {
868 switch (mlx5_get_vport_access_method(ibdev)) {
869 case MLX5_VPORT_ACCESS_METHOD_MAD:
870 return mlx5_query_mad_ifc_port(ibdev, port, props);
871
872 case MLX5_VPORT_ACCESS_METHOD_HCA:
873 return mlx5_query_hca_port(ibdev, port, props);
874
875 case MLX5_VPORT_ACCESS_METHOD_NIC:
876 return mlx5_query_port_roce(ibdev, port, props);
877
878 default:
879 return -EINVAL;
880 }
881 }
882
883 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
884 union ib_gid *gid)
885 {
886 struct mlx5_ib_dev *dev = to_mdev(ibdev);
887 struct mlx5_core_dev *mdev = dev->mdev;
888
889 switch (mlx5_get_vport_access_method(ibdev)) {
890 case MLX5_VPORT_ACCESS_METHOD_MAD:
891 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
892
893 case MLX5_VPORT_ACCESS_METHOD_HCA:
894 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
895
896 default:
897 return -EINVAL;
898 }
899
900 }
901
902 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
903 u16 *pkey)
904 {
905 struct mlx5_ib_dev *dev = to_mdev(ibdev);
906 struct mlx5_core_dev *mdev = dev->mdev;
907
908 switch (mlx5_get_vport_access_method(ibdev)) {
909 case MLX5_VPORT_ACCESS_METHOD_MAD:
910 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
911
912 case MLX5_VPORT_ACCESS_METHOD_HCA:
913 case MLX5_VPORT_ACCESS_METHOD_NIC:
914 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
915 pkey);
916 default:
917 return -EINVAL;
918 }
919 }
920
921 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
922 struct ib_device_modify *props)
923 {
924 struct mlx5_ib_dev *dev = to_mdev(ibdev);
925 struct mlx5_reg_node_desc in;
926 struct mlx5_reg_node_desc out;
927 int err;
928
929 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
930 return -EOPNOTSUPP;
931
932 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
933 return 0;
934
935 /*
936 * If possible, pass node desc to FW, so it can generate
937 * a 144 trap. If cmd fails, just ignore.
938 */
939 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
940 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
941 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
942 if (err)
943 return err;
944
945 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
946
947 return err;
948 }
949
950 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
951 struct ib_port_modify *props)
952 {
953 struct mlx5_ib_dev *dev = to_mdev(ibdev);
954 struct ib_port_attr attr;
955 u32 tmp;
956 int err;
957
958 mutex_lock(&dev->cap_mask_mutex);
959
960 err = mlx5_ib_query_port(ibdev, port, &attr);
961 if (err)
962 goto out;
963
964 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
965 ~props->clr_port_cap_mask;
966
967 err = mlx5_set_port_caps(dev->mdev, port, tmp);
968
969 out:
970 mutex_unlock(&dev->cap_mask_mutex);
971 return err;
972 }
973
974 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
975 struct ib_udata *udata)
976 {
977 struct mlx5_ib_dev *dev = to_mdev(ibdev);
978 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
979 struct mlx5_ib_alloc_ucontext_resp resp = {};
980 struct mlx5_ib_ucontext *context;
981 struct mlx5_uuar_info *uuari;
982 struct mlx5_uar *uars;
983 int gross_uuars;
984 int num_uars;
985 int ver;
986 int uuarn;
987 int err;
988 int i;
989 size_t reqlen;
990 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
991 max_cqe_version);
992
993 if (!dev->ib_active)
994 return ERR_PTR(-EAGAIN);
995
996 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
997 return ERR_PTR(-EINVAL);
998
999 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1000 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1001 ver = 0;
1002 else if (reqlen >= min_req_v2)
1003 ver = 2;
1004 else
1005 return ERR_PTR(-EINVAL);
1006
1007 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1008 if (err)
1009 return ERR_PTR(err);
1010
1011 if (req.flags)
1012 return ERR_PTR(-EINVAL);
1013
1014 if (req.total_num_uuars > MLX5_MAX_UUARS)
1015 return ERR_PTR(-ENOMEM);
1016
1017 if (req.total_num_uuars == 0)
1018 return ERR_PTR(-EINVAL);
1019
1020 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1021 return ERR_PTR(-EOPNOTSUPP);
1022
1023 if (reqlen > sizeof(req) &&
1024 !ib_is_udata_cleared(udata, sizeof(req),
1025 reqlen - sizeof(req)))
1026 return ERR_PTR(-EOPNOTSUPP);
1027
1028 req.total_num_uuars = ALIGN(req.total_num_uuars,
1029 MLX5_NON_FP_BF_REGS_PER_PAGE);
1030 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1031 return ERR_PTR(-EINVAL);
1032
1033 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1034 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1035 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1036 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1037 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1038 resp.cache_line_size = cache_line_size();
1039 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1040 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1041 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1042 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1043 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1044 resp.cqe_version = min_t(__u8,
1045 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1046 req.max_cqe_version);
1047 resp.response_length = min(offsetof(typeof(resp), response_length) +
1048 sizeof(resp.response_length), udata->outlen);
1049
1050 context = kzalloc(sizeof(*context), GFP_KERNEL);
1051 if (!context)
1052 return ERR_PTR(-ENOMEM);
1053
1054 uuari = &context->uuari;
1055 mutex_init(&uuari->lock);
1056 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1057 if (!uars) {
1058 err = -ENOMEM;
1059 goto out_ctx;
1060 }
1061
1062 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1063 sizeof(*uuari->bitmap),
1064 GFP_KERNEL);
1065 if (!uuari->bitmap) {
1066 err = -ENOMEM;
1067 goto out_uar_ctx;
1068 }
1069 /*
1070 * clear all fast path uuars
1071 */
1072 for (i = 0; i < gross_uuars; i++) {
1073 uuarn = i & 3;
1074 if (uuarn == 2 || uuarn == 3)
1075 set_bit(i, uuari->bitmap);
1076 }
1077
1078 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1079 if (!uuari->count) {
1080 err = -ENOMEM;
1081 goto out_bitmap;
1082 }
1083
1084 for (i = 0; i < num_uars; i++) {
1085 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1086 if (err)
1087 goto out_count;
1088 }
1089
1090 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1091 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1092 #endif
1093
1094 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1095 err = mlx5_core_alloc_transport_domain(dev->mdev,
1096 &context->tdn);
1097 if (err)
1098 goto out_uars;
1099 }
1100
1101 INIT_LIST_HEAD(&context->vma_private_list);
1102 INIT_LIST_HEAD(&context->db_page_list);
1103 mutex_init(&context->db_page_mutex);
1104
1105 resp.tot_uuars = req.total_num_uuars;
1106 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1107
1108 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1109 resp.response_length += sizeof(resp.cqe_version);
1110
1111 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1112 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1113 resp.response_length += sizeof(resp.cmds_supp_uhw);
1114 }
1115
1116 /*
1117 * We don't want to expose information from the PCI bar that is located
1118 * after 4096 bytes, so if the arch only supports larger pages, let's
1119 * pretend we don't support reading the HCA's core clock. This is also
1120 * forced by mmap function.
1121 */
1122 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1123 if (PAGE_SIZE <= 4096) {
1124 resp.comp_mask |=
1125 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1126 resp.hca_core_clock_offset =
1127 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1128 }
1129 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1130 sizeof(resp.reserved2);
1131 }
1132
1133 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1134 if (err)
1135 goto out_td;
1136
1137 uuari->ver = ver;
1138 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1139 uuari->uars = uars;
1140 uuari->num_uars = num_uars;
1141 context->cqe_version = resp.cqe_version;
1142
1143 return &context->ibucontext;
1144
1145 out_td:
1146 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1147 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1148
1149 out_uars:
1150 for (i--; i >= 0; i--)
1151 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1152 out_count:
1153 kfree(uuari->count);
1154
1155 out_bitmap:
1156 kfree(uuari->bitmap);
1157
1158 out_uar_ctx:
1159 kfree(uars);
1160
1161 out_ctx:
1162 kfree(context);
1163 return ERR_PTR(err);
1164 }
1165
1166 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1167 {
1168 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1169 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1170 struct mlx5_uuar_info *uuari = &context->uuari;
1171 int i;
1172
1173 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1174 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1175
1176 for (i = 0; i < uuari->num_uars; i++) {
1177 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1178 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1179 }
1180
1181 kfree(uuari->count);
1182 kfree(uuari->bitmap);
1183 kfree(uuari->uars);
1184 kfree(context);
1185
1186 return 0;
1187 }
1188
1189 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1190 {
1191 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1192 }
1193
1194 static int get_command(unsigned long offset)
1195 {
1196 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1197 }
1198
1199 static int get_arg(unsigned long offset)
1200 {
1201 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1202 }
1203
1204 static int get_index(unsigned long offset)
1205 {
1206 return get_arg(offset);
1207 }
1208
1209 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1210 {
1211 /* vma_open is called when a new VMA is created on top of our VMA. This
1212 * is done through either mremap flow or split_vma (usually due to
1213 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1214 * as this VMA is strongly hardware related. Therefore we set the
1215 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1216 * calling us again and trying to do incorrect actions. We assume that
1217 * the original VMA size is exactly a single page, and therefore all
1218 * "splitting" operation will not happen to it.
1219 */
1220 area->vm_ops = NULL;
1221 }
1222
1223 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1224 {
1225 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1226
1227 /* It's guaranteed that all VMAs opened on a FD are closed before the
1228 * file itself is closed, therefore no sync is needed with the regular
1229 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1230 * However need a sync with accessing the vma as part of
1231 * mlx5_ib_disassociate_ucontext.
1232 * The close operation is usually called under mm->mmap_sem except when
1233 * process is exiting.
1234 * The exiting case is handled explicitly as part of
1235 * mlx5_ib_disassociate_ucontext.
1236 */
1237 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1238
1239 /* setting the vma context pointer to null in the mlx5_ib driver's
1240 * private data, to protect a race condition in
1241 * mlx5_ib_disassociate_ucontext().
1242 */
1243 mlx5_ib_vma_priv_data->vma = NULL;
1244 list_del(&mlx5_ib_vma_priv_data->list);
1245 kfree(mlx5_ib_vma_priv_data);
1246 }
1247
1248 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1249 .open = mlx5_ib_vma_open,
1250 .close = mlx5_ib_vma_close
1251 };
1252
1253 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1254 struct mlx5_ib_ucontext *ctx)
1255 {
1256 struct mlx5_ib_vma_private_data *vma_prv;
1257 struct list_head *vma_head = &ctx->vma_private_list;
1258
1259 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1260 if (!vma_prv)
1261 return -ENOMEM;
1262
1263 vma_prv->vma = vma;
1264 vma->vm_private_data = vma_prv;
1265 vma->vm_ops = &mlx5_ib_vm_ops;
1266
1267 list_add(&vma_prv->list, vma_head);
1268
1269 return 0;
1270 }
1271
1272 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1273 {
1274 int ret;
1275 struct vm_area_struct *vma;
1276 struct mlx5_ib_vma_private_data *vma_private, *n;
1277 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1278 struct task_struct *owning_process = NULL;
1279 struct mm_struct *owning_mm = NULL;
1280
1281 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1282 if (!owning_process)
1283 return;
1284
1285 owning_mm = get_task_mm(owning_process);
1286 if (!owning_mm) {
1287 pr_info("no mm, disassociate ucontext is pending task termination\n");
1288 while (1) {
1289 put_task_struct(owning_process);
1290 usleep_range(1000, 2000);
1291 owning_process = get_pid_task(ibcontext->tgid,
1292 PIDTYPE_PID);
1293 if (!owning_process ||
1294 owning_process->state == TASK_DEAD) {
1295 pr_info("disassociate ucontext done, task was terminated\n");
1296 /* in case task was dead need to release the
1297 * task struct.
1298 */
1299 if (owning_process)
1300 put_task_struct(owning_process);
1301 return;
1302 }
1303 }
1304 }
1305
1306 /* need to protect from a race on closing the vma as part of
1307 * mlx5_ib_vma_close.
1308 */
1309 down_write(&owning_mm->mmap_sem);
1310 if (!mmget_still_valid(owning_mm))
1311 goto skip_mm;
1312 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1313 list) {
1314 vma = vma_private->vma;
1315 ret = zap_vma_ptes(vma, vma->vm_start,
1316 PAGE_SIZE);
1317 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1318 /* context going to be destroyed, should
1319 * not access ops any more.
1320 */
1321 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1322 vma->vm_ops = NULL;
1323 list_del(&vma_private->list);
1324 kfree(vma_private);
1325 }
1326 skip_mm:
1327 up_write(&owning_mm->mmap_sem);
1328 mmput(owning_mm);
1329 put_task_struct(owning_process);
1330 }
1331
1332 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1333 {
1334 switch (cmd) {
1335 case MLX5_IB_MMAP_WC_PAGE:
1336 return "WC";
1337 case MLX5_IB_MMAP_REGULAR_PAGE:
1338 return "best effort WC";
1339 case MLX5_IB_MMAP_NC_PAGE:
1340 return "NC";
1341 default:
1342 return NULL;
1343 }
1344 }
1345
1346 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1347 struct vm_area_struct *vma,
1348 struct mlx5_ib_ucontext *context)
1349 {
1350 struct mlx5_uuar_info *uuari = &context->uuari;
1351 int err;
1352 unsigned long idx;
1353 phys_addr_t pfn, pa;
1354 pgprot_t prot;
1355
1356 switch (cmd) {
1357 case MLX5_IB_MMAP_WC_PAGE:
1358 /* Some architectures don't support WC memory */
1359 #if defined(CONFIG_X86)
1360 if (!pat_enabled())
1361 return -EPERM;
1362 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1363 return -EPERM;
1364 #endif
1365 /* fall through */
1366 case MLX5_IB_MMAP_REGULAR_PAGE:
1367 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1368 prot = pgprot_writecombine(vma->vm_page_prot);
1369 break;
1370 case MLX5_IB_MMAP_NC_PAGE:
1371 prot = pgprot_noncached(vma->vm_page_prot);
1372 break;
1373 default:
1374 return -EINVAL;
1375 }
1376
1377 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1378 return -EINVAL;
1379
1380 idx = get_index(vma->vm_pgoff);
1381 if (idx >= uuari->num_uars)
1382 return -EINVAL;
1383
1384 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1385 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1386
1387 vma->vm_page_prot = prot;
1388 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1389 PAGE_SIZE, vma->vm_page_prot);
1390 if (err) {
1391 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1392 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1393 return -EAGAIN;
1394 }
1395
1396 pa = pfn << PAGE_SHIFT;
1397 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1398 vma->vm_start, &pa);
1399
1400 return mlx5_ib_set_vma_data(vma, context);
1401 }
1402
1403 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1404 {
1405 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1406 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1407 unsigned long command;
1408 phys_addr_t pfn;
1409
1410 command = get_command(vma->vm_pgoff);
1411 switch (command) {
1412 case MLX5_IB_MMAP_WC_PAGE:
1413 case MLX5_IB_MMAP_NC_PAGE:
1414 case MLX5_IB_MMAP_REGULAR_PAGE:
1415 return uar_mmap(dev, command, vma, context);
1416
1417 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1418 return -ENOSYS;
1419
1420 case MLX5_IB_MMAP_CORE_CLOCK:
1421 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1422 return -EINVAL;
1423
1424 if (vma->vm_flags & VM_WRITE)
1425 return -EPERM;
1426
1427 /* Don't expose to user-space information it shouldn't have */
1428 if (PAGE_SIZE > 4096)
1429 return -EOPNOTSUPP;
1430
1431 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1432 pfn = (dev->mdev->iseg_base +
1433 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1434 PAGE_SHIFT;
1435 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1436 PAGE_SIZE, vma->vm_page_prot))
1437 return -EAGAIN;
1438
1439 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1440 vma->vm_start,
1441 (unsigned long long)pfn << PAGE_SHIFT);
1442 break;
1443
1444 default:
1445 return -EINVAL;
1446 }
1447
1448 return 0;
1449 }
1450
1451 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1452 struct ib_ucontext *context,
1453 struct ib_udata *udata)
1454 {
1455 struct mlx5_ib_alloc_pd_resp resp;
1456 struct mlx5_ib_pd *pd;
1457 int err;
1458
1459 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1460 if (!pd)
1461 return ERR_PTR(-ENOMEM);
1462
1463 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1464 if (err) {
1465 kfree(pd);
1466 return ERR_PTR(err);
1467 }
1468
1469 if (context) {
1470 resp.pdn = pd->pdn;
1471 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1472 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1473 kfree(pd);
1474 return ERR_PTR(-EFAULT);
1475 }
1476 }
1477
1478 return &pd->ibpd;
1479 }
1480
1481 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1482 {
1483 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1484 struct mlx5_ib_pd *mpd = to_mpd(pd);
1485
1486 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1487 kfree(mpd);
1488
1489 return 0;
1490 }
1491
1492 enum {
1493 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1494 MATCH_CRITERIA_ENABLE_MISC_BIT,
1495 MATCH_CRITERIA_ENABLE_INNER_BIT
1496 };
1497
1498 #define HEADER_IS_ZERO(match_criteria, headers) \
1499 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1500 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1501
1502 static u8 get_match_criteria_enable(u32 *match_criteria)
1503 {
1504 u8 match_criteria_enable;
1505
1506 match_criteria_enable =
1507 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1508 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1509 match_criteria_enable |=
1510 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1511 MATCH_CRITERIA_ENABLE_MISC_BIT;
1512 match_criteria_enable |=
1513 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1514 MATCH_CRITERIA_ENABLE_INNER_BIT;
1515
1516 return match_criteria_enable;
1517 }
1518
1519 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1520 {
1521 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1522 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1523 }
1524
1525 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1526 {
1527 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1528 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1529 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1530 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1531 }
1532
1533 #define LAST_ETH_FIELD vlan_tag
1534 #define LAST_IB_FIELD sl
1535 #define LAST_IPV4_FIELD tos
1536 #define LAST_IPV6_FIELD traffic_class
1537 #define LAST_TCP_UDP_FIELD src_port
1538
1539 /* Field is the last supported field */
1540 #define FIELDS_NOT_SUPPORTED(filter, field)\
1541 memchr_inv((void *)&filter.field +\
1542 sizeof(filter.field), 0,\
1543 sizeof(filter) -\
1544 offsetof(typeof(filter), field) -\
1545 sizeof(filter.field))
1546
1547 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1548 const union ib_flow_spec *ib_spec)
1549 {
1550 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1551 outer_headers);
1552 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1553 outer_headers);
1554 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1555 misc_parameters);
1556 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1557 misc_parameters);
1558
1559 switch (ib_spec->type) {
1560 case IB_FLOW_SPEC_ETH:
1561 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1562 return -ENOTSUPP;
1563
1564 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1565 dmac_47_16),
1566 ib_spec->eth.mask.dst_mac);
1567 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1568 dmac_47_16),
1569 ib_spec->eth.val.dst_mac);
1570
1571 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1572 smac_47_16),
1573 ib_spec->eth.mask.src_mac);
1574 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1575 smac_47_16),
1576 ib_spec->eth.val.src_mac);
1577
1578 if (ib_spec->eth.mask.vlan_tag) {
1579 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1580 vlan_tag, 1);
1581 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1582 vlan_tag, 1);
1583
1584 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1585 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1586 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1587 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1588
1589 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1590 first_cfi,
1591 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1592 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1593 first_cfi,
1594 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1595
1596 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1597 first_prio,
1598 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1599 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1600 first_prio,
1601 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1602 }
1603 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1604 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1605 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1606 ethertype, ntohs(ib_spec->eth.val.ether_type));
1607 break;
1608 case IB_FLOW_SPEC_IPV4:
1609 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1610 return -ENOTSUPP;
1611
1612 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1613 ethertype, 0xffff);
1614 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1615 ethertype, ETH_P_IP);
1616
1617 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1618 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1619 &ib_spec->ipv4.mask.src_ip,
1620 sizeof(ib_spec->ipv4.mask.src_ip));
1621 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1622 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1623 &ib_spec->ipv4.val.src_ip,
1624 sizeof(ib_spec->ipv4.val.src_ip));
1625 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1626 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1627 &ib_spec->ipv4.mask.dst_ip,
1628 sizeof(ib_spec->ipv4.mask.dst_ip));
1629 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1630 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1631 &ib_spec->ipv4.val.dst_ip,
1632 sizeof(ib_spec->ipv4.val.dst_ip));
1633
1634 set_tos(outer_headers_c, outer_headers_v,
1635 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1636
1637 set_proto(outer_headers_c, outer_headers_v,
1638 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1639 break;
1640 case IB_FLOW_SPEC_IPV6:
1641 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1642 return -ENOTSUPP;
1643
1644 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1645 ethertype, 0xffff);
1646 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1647 ethertype, ETH_P_IPV6);
1648
1649 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1650 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1651 &ib_spec->ipv6.mask.src_ip,
1652 sizeof(ib_spec->ipv6.mask.src_ip));
1653 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1654 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1655 &ib_spec->ipv6.val.src_ip,
1656 sizeof(ib_spec->ipv6.val.src_ip));
1657 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1658 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1659 &ib_spec->ipv6.mask.dst_ip,
1660 sizeof(ib_spec->ipv6.mask.dst_ip));
1661 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1662 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1663 &ib_spec->ipv6.val.dst_ip,
1664 sizeof(ib_spec->ipv6.val.dst_ip));
1665
1666 set_tos(outer_headers_c, outer_headers_v,
1667 ib_spec->ipv6.mask.traffic_class,
1668 ib_spec->ipv6.val.traffic_class);
1669
1670 set_proto(outer_headers_c, outer_headers_v,
1671 ib_spec->ipv6.mask.next_hdr,
1672 ib_spec->ipv6.val.next_hdr);
1673
1674 MLX5_SET(fte_match_set_misc, misc_params_c,
1675 outer_ipv6_flow_label,
1676 ntohl(ib_spec->ipv6.mask.flow_label));
1677 MLX5_SET(fte_match_set_misc, misc_params_v,
1678 outer_ipv6_flow_label,
1679 ntohl(ib_spec->ipv6.val.flow_label));
1680 break;
1681 case IB_FLOW_SPEC_TCP:
1682 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1683 LAST_TCP_UDP_FIELD))
1684 return -ENOTSUPP;
1685
1686 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1687 0xff);
1688 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1689 IPPROTO_TCP);
1690
1691 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1692 ntohs(ib_spec->tcp_udp.mask.src_port));
1693 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1694 ntohs(ib_spec->tcp_udp.val.src_port));
1695
1696 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1697 ntohs(ib_spec->tcp_udp.mask.dst_port));
1698 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1699 ntohs(ib_spec->tcp_udp.val.dst_port));
1700 break;
1701 case IB_FLOW_SPEC_UDP:
1702 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1703 LAST_TCP_UDP_FIELD))
1704 return -ENOTSUPP;
1705
1706 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1707 0xff);
1708 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1709 IPPROTO_UDP);
1710
1711 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1712 ntohs(ib_spec->tcp_udp.mask.src_port));
1713 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1714 ntohs(ib_spec->tcp_udp.val.src_port));
1715
1716 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1717 ntohs(ib_spec->tcp_udp.mask.dst_port));
1718 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1719 ntohs(ib_spec->tcp_udp.val.dst_port));
1720 break;
1721 default:
1722 return -EINVAL;
1723 }
1724
1725 return 0;
1726 }
1727
1728 /* If a flow could catch both multicast and unicast packets,
1729 * it won't fall into the multicast flow steering table and this rule
1730 * could steal other multicast packets.
1731 */
1732 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1733 {
1734 struct ib_flow_spec_eth *eth_spec;
1735
1736 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1737 ib_attr->size < sizeof(struct ib_flow_attr) +
1738 sizeof(struct ib_flow_spec_eth) ||
1739 ib_attr->num_of_specs < 1)
1740 return false;
1741
1742 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1743 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1744 eth_spec->size != sizeof(*eth_spec))
1745 return false;
1746
1747 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1748 is_multicast_ether_addr(eth_spec->val.dst_mac);
1749 }
1750
1751 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1752 {
1753 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1754 bool has_ipv4_spec = false;
1755 bool eth_type_ipv4 = true;
1756 unsigned int spec_index;
1757
1758 /* Validate that ethertype is correct */
1759 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1760 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1761 ib_spec->eth.mask.ether_type) {
1762 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1763 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1764 eth_type_ipv4 = false;
1765 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1766 has_ipv4_spec = true;
1767 }
1768 ib_spec = (void *)ib_spec + ib_spec->size;
1769 }
1770 return !has_ipv4_spec || eth_type_ipv4;
1771 }
1772
1773 static void put_flow_table(struct mlx5_ib_dev *dev,
1774 struct mlx5_ib_flow_prio *prio, bool ft_added)
1775 {
1776 prio->refcount -= !!ft_added;
1777 if (!prio->refcount) {
1778 mlx5_destroy_flow_table(prio->flow_table);
1779 prio->flow_table = NULL;
1780 }
1781 }
1782
1783 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1784 {
1785 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1786 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1787 struct mlx5_ib_flow_handler,
1788 ibflow);
1789 struct mlx5_ib_flow_handler *iter, *tmp;
1790
1791 mutex_lock(&dev->flow_db.lock);
1792
1793 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1794 mlx5_del_flow_rule(iter->rule);
1795 put_flow_table(dev, iter->prio, true);
1796 list_del(&iter->list);
1797 kfree(iter);
1798 }
1799
1800 mlx5_del_flow_rule(handler->rule);
1801 put_flow_table(dev, handler->prio, true);
1802 mutex_unlock(&dev->flow_db.lock);
1803
1804 kfree(handler);
1805
1806 return 0;
1807 }
1808
1809 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1810 {
1811 priority *= 2;
1812 if (!dont_trap)
1813 priority++;
1814 return priority;
1815 }
1816
1817 enum flow_table_type {
1818 MLX5_IB_FT_RX,
1819 MLX5_IB_FT_TX
1820 };
1821
1822 #define MLX5_FS_MAX_TYPES 10
1823 #define MLX5_FS_MAX_ENTRIES 32000UL
1824 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1825 struct ib_flow_attr *flow_attr,
1826 enum flow_table_type ft_type)
1827 {
1828 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1829 struct mlx5_flow_namespace *ns = NULL;
1830 struct mlx5_ib_flow_prio *prio;
1831 struct mlx5_flow_table *ft;
1832 int num_entries;
1833 int num_groups;
1834 int priority;
1835 int err = 0;
1836
1837 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1838 if (flow_is_multicast_only(flow_attr) &&
1839 !dont_trap)
1840 priority = MLX5_IB_FLOW_MCAST_PRIO;
1841 else
1842 priority = ib_prio_to_core_prio(flow_attr->priority,
1843 dont_trap);
1844 ns = mlx5_get_flow_namespace(dev->mdev,
1845 MLX5_FLOW_NAMESPACE_BYPASS);
1846 num_entries = MLX5_FS_MAX_ENTRIES;
1847 num_groups = MLX5_FS_MAX_TYPES;
1848 prio = &dev->flow_db.prios[priority];
1849 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1850 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1851 ns = mlx5_get_flow_namespace(dev->mdev,
1852 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1853 build_leftovers_ft_param(&priority,
1854 &num_entries,
1855 &num_groups);
1856 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1857 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1858 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1859 allow_sniffer_and_nic_rx_shared_tir))
1860 return ERR_PTR(-ENOTSUPP);
1861
1862 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1863 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1864 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1865
1866 prio = &dev->flow_db.sniffer[ft_type];
1867 priority = 0;
1868 num_entries = 1;
1869 num_groups = 1;
1870 }
1871
1872 if (!ns)
1873 return ERR_PTR(-ENOTSUPP);
1874
1875 ft = prio->flow_table;
1876 if (!ft) {
1877 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1878 num_entries,
1879 num_groups,
1880 0);
1881
1882 if (!IS_ERR(ft)) {
1883 prio->refcount = 0;
1884 prio->flow_table = ft;
1885 } else {
1886 err = PTR_ERR(ft);
1887 }
1888 }
1889
1890 return err ? ERR_PTR(err) : prio;
1891 }
1892
1893 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1894 struct mlx5_ib_flow_prio *ft_prio,
1895 const struct ib_flow_attr *flow_attr,
1896 struct mlx5_flow_destination *dst)
1897 {
1898 struct mlx5_flow_table *ft = ft_prio->flow_table;
1899 struct mlx5_ib_flow_handler *handler;
1900 struct mlx5_flow_spec *spec;
1901 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1902 unsigned int spec_index;
1903 u32 action;
1904 int err = 0;
1905
1906 if (!is_valid_attr(flow_attr))
1907 return ERR_PTR(-EINVAL);
1908
1909 spec = mlx5_vzalloc(sizeof(*spec));
1910 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1911 if (!handler || !spec) {
1912 err = -ENOMEM;
1913 goto free;
1914 }
1915
1916 INIT_LIST_HEAD(&handler->list);
1917
1918 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1919 err = parse_flow_attr(spec->match_criteria,
1920 spec->match_value, ib_flow);
1921 if (err < 0)
1922 goto free;
1923
1924 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1925 }
1926
1927 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1928 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1929 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1930 handler->rule = mlx5_add_flow_rule(ft, spec,
1931 action,
1932 MLX5_FS_DEFAULT_FLOW_TAG,
1933 dst);
1934
1935 if (IS_ERR(handler->rule)) {
1936 err = PTR_ERR(handler->rule);
1937 goto free;
1938 }
1939
1940 ft_prio->refcount++;
1941 handler->prio = ft_prio;
1942
1943 ft_prio->flow_table = ft;
1944 free:
1945 if (err)
1946 kfree(handler);
1947 kvfree(spec);
1948 return err ? ERR_PTR(err) : handler;
1949 }
1950
1951 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1952 struct mlx5_ib_flow_prio *ft_prio,
1953 struct ib_flow_attr *flow_attr,
1954 struct mlx5_flow_destination *dst)
1955 {
1956 struct mlx5_ib_flow_handler *handler_dst = NULL;
1957 struct mlx5_ib_flow_handler *handler = NULL;
1958
1959 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1960 if (!IS_ERR(handler)) {
1961 handler_dst = create_flow_rule(dev, ft_prio,
1962 flow_attr, dst);
1963 if (IS_ERR(handler_dst)) {
1964 mlx5_del_flow_rule(handler->rule);
1965 ft_prio->refcount--;
1966 kfree(handler);
1967 handler = handler_dst;
1968 } else {
1969 list_add(&handler_dst->list, &handler->list);
1970 }
1971 }
1972
1973 return handler;
1974 }
1975 enum {
1976 LEFTOVERS_MC,
1977 LEFTOVERS_UC,
1978 };
1979
1980 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1981 struct mlx5_ib_flow_prio *ft_prio,
1982 struct ib_flow_attr *flow_attr,
1983 struct mlx5_flow_destination *dst)
1984 {
1985 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1986 struct mlx5_ib_flow_handler *handler = NULL;
1987
1988 static struct {
1989 struct ib_flow_attr flow_attr;
1990 struct ib_flow_spec_eth eth_flow;
1991 } leftovers_specs[] = {
1992 [LEFTOVERS_MC] = {
1993 .flow_attr = {
1994 .num_of_specs = 1,
1995 .size = sizeof(leftovers_specs[0])
1996 },
1997 .eth_flow = {
1998 .type = IB_FLOW_SPEC_ETH,
1999 .size = sizeof(struct ib_flow_spec_eth),
2000 .mask = {.dst_mac = {0x1} },
2001 .val = {.dst_mac = {0x1} }
2002 }
2003 },
2004 [LEFTOVERS_UC] = {
2005 .flow_attr = {
2006 .num_of_specs = 1,
2007 .size = sizeof(leftovers_specs[0])
2008 },
2009 .eth_flow = {
2010 .type = IB_FLOW_SPEC_ETH,
2011 .size = sizeof(struct ib_flow_spec_eth),
2012 .mask = {.dst_mac = {0x1} },
2013 .val = {.dst_mac = {} }
2014 }
2015 }
2016 };
2017
2018 handler = create_flow_rule(dev, ft_prio,
2019 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2020 dst);
2021 if (!IS_ERR(handler) &&
2022 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2023 handler_ucast = create_flow_rule(dev, ft_prio,
2024 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2025 dst);
2026 if (IS_ERR(handler_ucast)) {
2027 mlx5_del_flow_rule(handler->rule);
2028 ft_prio->refcount--;
2029 kfree(handler);
2030 handler = handler_ucast;
2031 } else {
2032 list_add(&handler_ucast->list, &handler->list);
2033 }
2034 }
2035
2036 return handler;
2037 }
2038
2039 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2040 struct mlx5_ib_flow_prio *ft_rx,
2041 struct mlx5_ib_flow_prio *ft_tx,
2042 struct mlx5_flow_destination *dst)
2043 {
2044 struct mlx5_ib_flow_handler *handler_rx;
2045 struct mlx5_ib_flow_handler *handler_tx;
2046 int err;
2047 static const struct ib_flow_attr flow_attr = {
2048 .num_of_specs = 0,
2049 .size = sizeof(flow_attr)
2050 };
2051
2052 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2053 if (IS_ERR(handler_rx)) {
2054 err = PTR_ERR(handler_rx);
2055 goto err;
2056 }
2057
2058 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2059 if (IS_ERR(handler_tx)) {
2060 err = PTR_ERR(handler_tx);
2061 goto err_tx;
2062 }
2063
2064 list_add(&handler_tx->list, &handler_rx->list);
2065
2066 return handler_rx;
2067
2068 err_tx:
2069 mlx5_del_flow_rule(handler_rx->rule);
2070 ft_rx->refcount--;
2071 kfree(handler_rx);
2072 err:
2073 return ERR_PTR(err);
2074 }
2075
2076 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2077 struct ib_flow_attr *flow_attr,
2078 int domain)
2079 {
2080 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2081 struct mlx5_ib_qp *mqp = to_mqp(qp);
2082 struct mlx5_ib_flow_handler *handler = NULL;
2083 struct mlx5_flow_destination *dst = NULL;
2084 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2085 struct mlx5_ib_flow_prio *ft_prio;
2086 int err;
2087
2088 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2089 return ERR_PTR(-ENOSPC);
2090
2091 if (domain != IB_FLOW_DOMAIN_USER ||
2092 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2093 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2094 return ERR_PTR(-EINVAL);
2095
2096 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2097 if (!dst)
2098 return ERR_PTR(-ENOMEM);
2099
2100 mutex_lock(&dev->flow_db.lock);
2101
2102 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2103 if (IS_ERR(ft_prio)) {
2104 err = PTR_ERR(ft_prio);
2105 goto unlock;
2106 }
2107 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2108 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2109 if (IS_ERR(ft_prio_tx)) {
2110 err = PTR_ERR(ft_prio_tx);
2111 ft_prio_tx = NULL;
2112 goto destroy_ft;
2113 }
2114 }
2115
2116 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2117 if (mqp->flags & MLX5_IB_QP_RSS)
2118 dst->tir_num = mqp->rss_qp.tirn;
2119 else
2120 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2121
2122 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2123 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2124 handler = create_dont_trap_rule(dev, ft_prio,
2125 flow_attr, dst);
2126 } else {
2127 handler = create_flow_rule(dev, ft_prio, flow_attr,
2128 dst);
2129 }
2130 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2131 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2132 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2133 dst);
2134 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2135 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2136 } else {
2137 err = -EINVAL;
2138 goto destroy_ft;
2139 }
2140
2141 if (IS_ERR(handler)) {
2142 err = PTR_ERR(handler);
2143 handler = NULL;
2144 goto destroy_ft;
2145 }
2146
2147 mutex_unlock(&dev->flow_db.lock);
2148 kfree(dst);
2149
2150 return &handler->ibflow;
2151
2152 destroy_ft:
2153 put_flow_table(dev, ft_prio, false);
2154 if (ft_prio_tx)
2155 put_flow_table(dev, ft_prio_tx, false);
2156 unlock:
2157 mutex_unlock(&dev->flow_db.lock);
2158 kfree(dst);
2159 kfree(handler);
2160 return ERR_PTR(err);
2161 }
2162
2163 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2164 {
2165 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2166 int err;
2167
2168 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2169 if (err)
2170 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2171 ibqp->qp_num, gid->raw);
2172
2173 return err;
2174 }
2175
2176 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2177 {
2178 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2179 int err;
2180
2181 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2182 if (err)
2183 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2184 ibqp->qp_num, gid->raw);
2185
2186 return err;
2187 }
2188
2189 static int init_node_data(struct mlx5_ib_dev *dev)
2190 {
2191 int err;
2192
2193 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2194 if (err)
2195 return err;
2196
2197 dev->mdev->rev_id = dev->mdev->pdev->revision;
2198
2199 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2200 }
2201
2202 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2203 char *buf)
2204 {
2205 struct mlx5_ib_dev *dev =
2206 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2207
2208 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2209 }
2210
2211 static ssize_t show_reg_pages(struct device *device,
2212 struct device_attribute *attr, char *buf)
2213 {
2214 struct mlx5_ib_dev *dev =
2215 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2216
2217 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2218 }
2219
2220 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2221 char *buf)
2222 {
2223 struct mlx5_ib_dev *dev =
2224 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2225 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2226 }
2227
2228 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2229 char *buf)
2230 {
2231 struct mlx5_ib_dev *dev =
2232 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2233 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2234 }
2235
2236 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2237 char *buf)
2238 {
2239 struct mlx5_ib_dev *dev =
2240 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2241 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2242 dev->mdev->board_id);
2243 }
2244
2245 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2246 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2247 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2248 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2249 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2250
2251 static struct device_attribute *mlx5_class_attributes[] = {
2252 &dev_attr_hw_rev,
2253 &dev_attr_hca_type,
2254 &dev_attr_board_id,
2255 &dev_attr_fw_pages,
2256 &dev_attr_reg_pages,
2257 };
2258
2259 static void pkey_change_handler(struct work_struct *work)
2260 {
2261 struct mlx5_ib_port_resources *ports =
2262 container_of(work, struct mlx5_ib_port_resources,
2263 pkey_change_work);
2264
2265 mutex_lock(&ports->devr->mutex);
2266 mlx5_ib_gsi_pkey_change(ports->gsi);
2267 mutex_unlock(&ports->devr->mutex);
2268 }
2269
2270 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2271 {
2272 struct mlx5_ib_qp *mqp;
2273 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2274 struct mlx5_core_cq *mcq;
2275 struct list_head cq_armed_list;
2276 unsigned long flags_qp;
2277 unsigned long flags_cq;
2278 unsigned long flags;
2279
2280 INIT_LIST_HEAD(&cq_armed_list);
2281
2282 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2283 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2284 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2285 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2286 if (mqp->sq.tail != mqp->sq.head) {
2287 send_mcq = to_mcq(mqp->ibqp.send_cq);
2288 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2289 if (send_mcq->mcq.comp &&
2290 mqp->ibqp.send_cq->comp_handler) {
2291 if (!send_mcq->mcq.reset_notify_added) {
2292 send_mcq->mcq.reset_notify_added = 1;
2293 list_add_tail(&send_mcq->mcq.reset_notify,
2294 &cq_armed_list);
2295 }
2296 }
2297 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2298 }
2299 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2300 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2301 /* no handling is needed for SRQ */
2302 if (!mqp->ibqp.srq) {
2303 if (mqp->rq.tail != mqp->rq.head) {
2304 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2305 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2306 if (recv_mcq->mcq.comp &&
2307 mqp->ibqp.recv_cq->comp_handler) {
2308 if (!recv_mcq->mcq.reset_notify_added) {
2309 recv_mcq->mcq.reset_notify_added = 1;
2310 list_add_tail(&recv_mcq->mcq.reset_notify,
2311 &cq_armed_list);
2312 }
2313 }
2314 spin_unlock_irqrestore(&recv_mcq->lock,
2315 flags_cq);
2316 }
2317 }
2318 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2319 }
2320 /*At that point all inflight post send were put to be executed as of we
2321 * lock/unlock above locks Now need to arm all involved CQs.
2322 */
2323 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2324 mcq->comp(mcq);
2325 }
2326 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2327 }
2328
2329 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2330 enum mlx5_dev_event event, unsigned long param)
2331 {
2332 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2333 struct ib_event ibev;
2334 bool fatal = false;
2335 u8 port = 0;
2336
2337 switch (event) {
2338 case MLX5_DEV_EVENT_SYS_ERROR:
2339 ibev.event = IB_EVENT_DEVICE_FATAL;
2340 mlx5_ib_handle_internal_error(ibdev);
2341 fatal = true;
2342 break;
2343
2344 case MLX5_DEV_EVENT_PORT_UP:
2345 case MLX5_DEV_EVENT_PORT_DOWN:
2346 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2347 port = (u8)param;
2348
2349 /* In RoCE, port up/down events are handled in
2350 * mlx5_netdev_event().
2351 */
2352 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2353 IB_LINK_LAYER_ETHERNET)
2354 return;
2355
2356 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2357 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2358 break;
2359
2360 case MLX5_DEV_EVENT_LID_CHANGE:
2361 ibev.event = IB_EVENT_LID_CHANGE;
2362 port = (u8)param;
2363 break;
2364
2365 case MLX5_DEV_EVENT_PKEY_CHANGE:
2366 ibev.event = IB_EVENT_PKEY_CHANGE;
2367 port = (u8)param;
2368
2369 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2370 break;
2371
2372 case MLX5_DEV_EVENT_GUID_CHANGE:
2373 ibev.event = IB_EVENT_GID_CHANGE;
2374 port = (u8)param;
2375 break;
2376
2377 case MLX5_DEV_EVENT_CLIENT_REREG:
2378 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2379 port = (u8)param;
2380 break;
2381 }
2382
2383 ibev.device = &ibdev->ib_dev;
2384 ibev.element.port_num = port;
2385
2386 if (port < 1 || port > ibdev->num_ports) {
2387 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2388 return;
2389 }
2390
2391 if (ibdev->ib_active)
2392 ib_dispatch_event(&ibev);
2393
2394 if (fatal)
2395 ibdev->ib_active = false;
2396 }
2397
2398 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2399 {
2400 int port;
2401
2402 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2403 mlx5_query_ext_port_caps(dev, port);
2404 }
2405
2406 static int get_port_caps(struct mlx5_ib_dev *dev)
2407 {
2408 struct ib_device_attr *dprops = NULL;
2409 struct ib_port_attr *pprops = NULL;
2410 int err = -ENOMEM;
2411 int port;
2412 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2413
2414 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2415 if (!pprops)
2416 goto out;
2417
2418 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2419 if (!dprops)
2420 goto out;
2421
2422 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2423 if (err) {
2424 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2425 goto out;
2426 }
2427
2428 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2429 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2430 if (err) {
2431 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2432 port, err);
2433 break;
2434 }
2435 dev->mdev->port_caps[port - 1].pkey_table_len =
2436 dprops->max_pkeys;
2437 dev->mdev->port_caps[port - 1].gid_table_len =
2438 pprops->gid_tbl_len;
2439 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2440 dprops->max_pkeys, pprops->gid_tbl_len);
2441 }
2442
2443 out:
2444 kfree(pprops);
2445 kfree(dprops);
2446
2447 return err;
2448 }
2449
2450 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2451 {
2452 int err;
2453
2454 err = mlx5_mr_cache_cleanup(dev);
2455 if (err)
2456 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2457
2458 mlx5_ib_destroy_qp(dev->umrc.qp);
2459 ib_free_cq(dev->umrc.cq);
2460 ib_dealloc_pd(dev->umrc.pd);
2461 }
2462
2463 enum {
2464 MAX_UMR_WR = 128,
2465 };
2466
2467 static int create_umr_res(struct mlx5_ib_dev *dev)
2468 {
2469 struct ib_qp_init_attr *init_attr = NULL;
2470 struct ib_qp_attr *attr = NULL;
2471 struct ib_pd *pd;
2472 struct ib_cq *cq;
2473 struct ib_qp *qp;
2474 int ret;
2475
2476 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2477 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2478 if (!attr || !init_attr) {
2479 ret = -ENOMEM;
2480 goto error_0;
2481 }
2482
2483 pd = ib_alloc_pd(&dev->ib_dev, 0);
2484 if (IS_ERR(pd)) {
2485 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2486 ret = PTR_ERR(pd);
2487 goto error_0;
2488 }
2489
2490 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2491 if (IS_ERR(cq)) {
2492 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2493 ret = PTR_ERR(cq);
2494 goto error_2;
2495 }
2496
2497 init_attr->send_cq = cq;
2498 init_attr->recv_cq = cq;
2499 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2500 init_attr->cap.max_send_wr = MAX_UMR_WR;
2501 init_attr->cap.max_send_sge = 1;
2502 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2503 init_attr->port_num = 1;
2504 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2505 if (IS_ERR(qp)) {
2506 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2507 ret = PTR_ERR(qp);
2508 goto error_3;
2509 }
2510 qp->device = &dev->ib_dev;
2511 qp->real_qp = qp;
2512 qp->uobject = NULL;
2513 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2514 qp->send_cq = init_attr->send_cq;
2515 qp->recv_cq = init_attr->recv_cq;
2516
2517 attr->qp_state = IB_QPS_INIT;
2518 attr->port_num = 1;
2519 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2520 IB_QP_PORT, NULL);
2521 if (ret) {
2522 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2523 goto error_4;
2524 }
2525
2526 memset(attr, 0, sizeof(*attr));
2527 attr->qp_state = IB_QPS_RTR;
2528 attr->path_mtu = IB_MTU_256;
2529
2530 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2531 if (ret) {
2532 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2533 goto error_4;
2534 }
2535
2536 memset(attr, 0, sizeof(*attr));
2537 attr->qp_state = IB_QPS_RTS;
2538 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2539 if (ret) {
2540 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2541 goto error_4;
2542 }
2543
2544 dev->umrc.qp = qp;
2545 dev->umrc.cq = cq;
2546 dev->umrc.pd = pd;
2547
2548 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2549 ret = mlx5_mr_cache_init(dev);
2550 if (ret) {
2551 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2552 goto error_4;
2553 }
2554
2555 kfree(attr);
2556 kfree(init_attr);
2557
2558 return 0;
2559
2560 error_4:
2561 mlx5_ib_destroy_qp(qp);
2562
2563 error_3:
2564 ib_free_cq(cq);
2565
2566 error_2:
2567 ib_dealloc_pd(pd);
2568
2569 error_0:
2570 kfree(attr);
2571 kfree(init_attr);
2572 return ret;
2573 }
2574
2575 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2576 {
2577 switch (umr_fence_cap) {
2578 case MLX5_CAP_UMR_FENCE_NONE:
2579 return MLX5_FENCE_MODE_NONE;
2580 case MLX5_CAP_UMR_FENCE_SMALL:
2581 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2582 default:
2583 return MLX5_FENCE_MODE_STRONG_ORDERING;
2584 }
2585 }
2586
2587 static int create_dev_resources(struct mlx5_ib_resources *devr)
2588 {
2589 struct ib_srq_init_attr attr;
2590 struct mlx5_ib_dev *dev;
2591 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2592 int port;
2593 int ret = 0;
2594
2595 dev = container_of(devr, struct mlx5_ib_dev, devr);
2596
2597 mutex_init(&devr->mutex);
2598
2599 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2600 if (IS_ERR(devr->p0)) {
2601 ret = PTR_ERR(devr->p0);
2602 goto error0;
2603 }
2604 devr->p0->device = &dev->ib_dev;
2605 devr->p0->uobject = NULL;
2606 atomic_set(&devr->p0->usecnt, 0);
2607
2608 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2609 if (IS_ERR(devr->c0)) {
2610 ret = PTR_ERR(devr->c0);
2611 goto error1;
2612 }
2613 devr->c0->device = &dev->ib_dev;
2614 devr->c0->uobject = NULL;
2615 devr->c0->comp_handler = NULL;
2616 devr->c0->event_handler = NULL;
2617 devr->c0->cq_context = NULL;
2618 atomic_set(&devr->c0->usecnt, 0);
2619
2620 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2621 if (IS_ERR(devr->x0)) {
2622 ret = PTR_ERR(devr->x0);
2623 goto error2;
2624 }
2625 devr->x0->device = &dev->ib_dev;
2626 devr->x0->inode = NULL;
2627 atomic_set(&devr->x0->usecnt, 0);
2628 mutex_init(&devr->x0->tgt_qp_mutex);
2629 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2630
2631 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2632 if (IS_ERR(devr->x1)) {
2633 ret = PTR_ERR(devr->x1);
2634 goto error3;
2635 }
2636 devr->x1->device = &dev->ib_dev;
2637 devr->x1->inode = NULL;
2638 atomic_set(&devr->x1->usecnt, 0);
2639 mutex_init(&devr->x1->tgt_qp_mutex);
2640 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2641
2642 memset(&attr, 0, sizeof(attr));
2643 attr.attr.max_sge = 1;
2644 attr.attr.max_wr = 1;
2645 attr.srq_type = IB_SRQT_XRC;
2646 attr.ext.xrc.cq = devr->c0;
2647 attr.ext.xrc.xrcd = devr->x0;
2648
2649 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2650 if (IS_ERR(devr->s0)) {
2651 ret = PTR_ERR(devr->s0);
2652 goto error4;
2653 }
2654 devr->s0->device = &dev->ib_dev;
2655 devr->s0->pd = devr->p0;
2656 devr->s0->uobject = NULL;
2657 devr->s0->event_handler = NULL;
2658 devr->s0->srq_context = NULL;
2659 devr->s0->srq_type = IB_SRQT_XRC;
2660 devr->s0->ext.xrc.xrcd = devr->x0;
2661 devr->s0->ext.xrc.cq = devr->c0;
2662 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2663 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2664 atomic_inc(&devr->p0->usecnt);
2665 atomic_set(&devr->s0->usecnt, 0);
2666
2667 memset(&attr, 0, sizeof(attr));
2668 attr.attr.max_sge = 1;
2669 attr.attr.max_wr = 1;
2670 attr.srq_type = IB_SRQT_BASIC;
2671 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2672 if (IS_ERR(devr->s1)) {
2673 ret = PTR_ERR(devr->s1);
2674 goto error5;
2675 }
2676 devr->s1->device = &dev->ib_dev;
2677 devr->s1->pd = devr->p0;
2678 devr->s1->uobject = NULL;
2679 devr->s1->event_handler = NULL;
2680 devr->s1->srq_context = NULL;
2681 devr->s1->srq_type = IB_SRQT_BASIC;
2682 devr->s1->ext.xrc.cq = devr->c0;
2683 atomic_inc(&devr->p0->usecnt);
2684 atomic_set(&devr->s0->usecnt, 0);
2685
2686 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2687 INIT_WORK(&devr->ports[port].pkey_change_work,
2688 pkey_change_handler);
2689 devr->ports[port].devr = devr;
2690 }
2691
2692 return 0;
2693
2694 error5:
2695 mlx5_ib_destroy_srq(devr->s0);
2696 error4:
2697 mlx5_ib_dealloc_xrcd(devr->x1);
2698 error3:
2699 mlx5_ib_dealloc_xrcd(devr->x0);
2700 error2:
2701 mlx5_ib_destroy_cq(devr->c0);
2702 error1:
2703 mlx5_ib_dealloc_pd(devr->p0);
2704 error0:
2705 return ret;
2706 }
2707
2708 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2709 {
2710 struct mlx5_ib_dev *dev =
2711 container_of(devr, struct mlx5_ib_dev, devr);
2712 int port;
2713
2714 mlx5_ib_destroy_srq(devr->s1);
2715 mlx5_ib_destroy_srq(devr->s0);
2716 mlx5_ib_dealloc_xrcd(devr->x0);
2717 mlx5_ib_dealloc_xrcd(devr->x1);
2718 mlx5_ib_destroy_cq(devr->c0);
2719 mlx5_ib_dealloc_pd(devr->p0);
2720
2721 /* Make sure no change P_Key work items are still executing */
2722 for (port = 0; port < dev->num_ports; ++port)
2723 cancel_work_sync(&devr->ports[port].pkey_change_work);
2724 }
2725
2726 static u32 get_core_cap_flags(struct ib_device *ibdev)
2727 {
2728 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2729 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2730 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2731 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2732 u32 ret = 0;
2733
2734 if (ll == IB_LINK_LAYER_INFINIBAND)
2735 return RDMA_CORE_PORT_IBA_IB;
2736
2737 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2738 return 0;
2739
2740 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2741 return 0;
2742
2743 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2744 ret |= RDMA_CORE_PORT_IBA_ROCE;
2745
2746 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2747 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2748
2749 return ret;
2750 }
2751
2752 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2753 struct ib_port_immutable *immutable)
2754 {
2755 struct ib_port_attr attr;
2756 int err;
2757
2758 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2759 if (err)
2760 return err;
2761
2762 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2763 immutable->gid_tbl_len = attr.gid_tbl_len;
2764 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2765 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2766
2767 return 0;
2768 }
2769
2770 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2771 size_t str_len)
2772 {
2773 struct mlx5_ib_dev *dev =
2774 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2775 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2776 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2777 }
2778
2779 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2780 {
2781 struct mlx5_core_dev *mdev = dev->mdev;
2782 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2783 MLX5_FLOW_NAMESPACE_LAG);
2784 struct mlx5_flow_table *ft;
2785 int err;
2786
2787 if (!ns || !mlx5_lag_is_active(mdev))
2788 return 0;
2789
2790 err = mlx5_cmd_create_vport_lag(mdev);
2791 if (err)
2792 return err;
2793
2794 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2795 if (IS_ERR(ft)) {
2796 err = PTR_ERR(ft);
2797 goto err_destroy_vport_lag;
2798 }
2799
2800 dev->flow_db.lag_demux_ft = ft;
2801 return 0;
2802
2803 err_destroy_vport_lag:
2804 mlx5_cmd_destroy_vport_lag(mdev);
2805 return err;
2806 }
2807
2808 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2809 {
2810 struct mlx5_core_dev *mdev = dev->mdev;
2811
2812 if (dev->flow_db.lag_demux_ft) {
2813 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2814 dev->flow_db.lag_demux_ft = NULL;
2815
2816 mlx5_cmd_destroy_vport_lag(mdev);
2817 }
2818 }
2819
2820 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2821 {
2822 if (dev->roce.nb.notifier_call) {
2823 unregister_netdevice_notifier(&dev->roce.nb);
2824 dev->roce.nb.notifier_call = NULL;
2825 }
2826 }
2827
2828 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2829 {
2830 int err;
2831
2832 dev->roce.nb.notifier_call = mlx5_netdev_event;
2833 err = register_netdevice_notifier(&dev->roce.nb);
2834 if (err) {
2835 dev->roce.nb.notifier_call = NULL;
2836 return err;
2837 }
2838
2839 err = mlx5_nic_vport_enable_roce(dev->mdev);
2840 if (err)
2841 goto err_unregister_netdevice_notifier;
2842
2843 err = mlx5_roce_lag_init(dev);
2844 if (err)
2845 goto err_disable_roce;
2846
2847 return 0;
2848
2849 err_disable_roce:
2850 mlx5_nic_vport_disable_roce(dev->mdev);
2851
2852 err_unregister_netdevice_notifier:
2853 mlx5_remove_roce_notifier(dev);
2854 return err;
2855 }
2856
2857 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2858 {
2859 mlx5_roce_lag_cleanup(dev);
2860 mlx5_nic_vport_disable_roce(dev->mdev);
2861 }
2862
2863 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2864 {
2865 unsigned int i;
2866
2867 for (i = 0; i < dev->num_ports; i++)
2868 mlx5_core_dealloc_q_counter(dev->mdev,
2869 dev->port[i].q_cnt_id);
2870 }
2871
2872 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2873 {
2874 int i;
2875 int ret;
2876
2877 for (i = 0; i < dev->num_ports; i++) {
2878 ret = mlx5_core_alloc_q_counter(dev->mdev,
2879 &dev->port[i].q_cnt_id);
2880 if (ret) {
2881 mlx5_ib_warn(dev,
2882 "couldn't allocate queue counter for port %d, err %d\n",
2883 i + 1, ret);
2884 goto dealloc_counters;
2885 }
2886 }
2887
2888 return 0;
2889
2890 dealloc_counters:
2891 while (--i >= 0)
2892 mlx5_core_dealloc_q_counter(dev->mdev,
2893 dev->port[i].q_cnt_id);
2894
2895 return ret;
2896 }
2897
2898 static const char * const names[] = {
2899 "rx_write_requests",
2900 "rx_read_requests",
2901 "rx_atomic_requests",
2902 "out_of_buffer",
2903 "out_of_sequence",
2904 "duplicate_request",
2905 "rnr_nak_retry_err",
2906 "packet_seq_err",
2907 "implied_nak_seq_err",
2908 "local_ack_timeout_err",
2909 };
2910
2911 static const size_t stats_offsets[] = {
2912 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2913 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2914 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2915 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2916 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2917 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2918 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2919 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2920 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2921 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2922 };
2923
2924 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2925 u8 port_num)
2926 {
2927 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2928
2929 /* We support only per port stats */
2930 if (port_num == 0)
2931 return NULL;
2932
2933 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2934 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2935 }
2936
2937 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2938 struct rdma_hw_stats *stats,
2939 u8 port, int index)
2940 {
2941 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2942 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2943 void *out;
2944 __be32 val;
2945 int ret;
2946 int i;
2947
2948 if (!port || !stats)
2949 return -ENOSYS;
2950
2951 out = mlx5_vzalloc(outlen);
2952 if (!out)
2953 return -ENOMEM;
2954
2955 ret = mlx5_core_query_q_counter(dev->mdev,
2956 dev->port[port - 1].q_cnt_id, 0,
2957 out, outlen);
2958 if (ret)
2959 goto free;
2960
2961 for (i = 0; i < ARRAY_SIZE(names); i++) {
2962 val = *(__be32 *)(out + stats_offsets[i]);
2963 stats->value[i] = (u64)be32_to_cpu(val);
2964 }
2965 free:
2966 kvfree(out);
2967 return ARRAY_SIZE(names);
2968 }
2969
2970 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2971 {
2972 struct mlx5_ib_dev *dev;
2973 enum rdma_link_layer ll;
2974 int port_type_cap;
2975 const char *name;
2976 int err;
2977 int i;
2978
2979 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2980 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2981
2982 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2983 return NULL;
2984
2985 printk_once(KERN_INFO "%s", mlx5_version);
2986
2987 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2988 if (!dev)
2989 return NULL;
2990
2991 dev->mdev = mdev;
2992
2993 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2994 GFP_KERNEL);
2995 if (!dev->port)
2996 goto err_dealloc;
2997
2998 rwlock_init(&dev->roce.netdev_lock);
2999 err = get_port_caps(dev);
3000 if (err)
3001 goto err_free_port;
3002
3003 if (mlx5_use_mad_ifc(dev))
3004 get_ext_port_caps(dev);
3005
3006 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
3007
3008 if (!mlx5_lag_is_active(mdev))
3009 name = "mlx5_%d";
3010 else
3011 name = "mlx5_bond_%d";
3012
3013 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3014 dev->ib_dev.owner = THIS_MODULE;
3015 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3016 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3017 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3018 dev->ib_dev.phys_port_cnt = dev->num_ports;
3019 dev->ib_dev.num_comp_vectors =
3020 dev->mdev->priv.eq_table.num_comp_vectors;
3021 dev->ib_dev.dma_device = &mdev->pdev->dev;
3022
3023 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3024 dev->ib_dev.uverbs_cmd_mask =
3025 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3026 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3027 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3028 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3029 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3030 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3031 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3032 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3033 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3034 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3035 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3036 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3037 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3038 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3039 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3040 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3041 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3042 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3043 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3044 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3045 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3046 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3047 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3048 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3049 dev->ib_dev.uverbs_ex_cmd_mask =
3050 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3051 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3052 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3053
3054 dev->ib_dev.query_device = mlx5_ib_query_device;
3055 dev->ib_dev.query_port = mlx5_ib_query_port;
3056 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3057 if (ll == IB_LINK_LAYER_ETHERNET)
3058 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3059 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3060 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3061 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3062 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3063 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3064 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3065 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3066 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3067 dev->ib_dev.mmap = mlx5_ib_mmap;
3068 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3069 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3070 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3071 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3072 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3073 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3074 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3075 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3076 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3077 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3078 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3079 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3080 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3081 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3082 dev->ib_dev.post_send = mlx5_ib_post_send;
3083 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3084 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3085 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3086 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3087 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3088 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3089 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3090 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3091 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3092 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3093 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3094 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3095 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3096 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3097 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3098 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3099 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3100 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3101 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3102 if (mlx5_core_is_pf(mdev)) {
3103 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3104 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3105 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3106 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3107 }
3108
3109 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3110
3111 mlx5_ib_internal_fill_odp_caps(dev);
3112
3113 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3114
3115 if (MLX5_CAP_GEN(mdev, imaicl)) {
3116 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3117 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3118 dev->ib_dev.uverbs_cmd_mask |=
3119 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3120 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3121 }
3122
3123 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3124 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3125 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3126 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3127 }
3128
3129 if (MLX5_CAP_GEN(mdev, xrc)) {
3130 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3131 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3132 dev->ib_dev.uverbs_cmd_mask |=
3133 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3134 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3135 }
3136
3137 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3138 IB_LINK_LAYER_ETHERNET) {
3139 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3140 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3141 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3142 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3143 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3144 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3145 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3146 dev->ib_dev.uverbs_ex_cmd_mask |=
3147 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3148 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3149 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3150 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3151 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3152 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3153 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3154 }
3155 err = init_node_data(dev);
3156 if (err)
3157 goto err_free_port;
3158
3159 mutex_init(&dev->flow_db.lock);
3160 mutex_init(&dev->cap_mask_mutex);
3161 INIT_LIST_HEAD(&dev->qp_list);
3162 spin_lock_init(&dev->reset_flow_resource_lock);
3163
3164 if (ll == IB_LINK_LAYER_ETHERNET) {
3165 err = mlx5_enable_roce(dev);
3166 if (err)
3167 goto err_free_port;
3168 }
3169
3170 err = create_dev_resources(&dev->devr);
3171 if (err)
3172 goto err_disable_roce;
3173
3174 err = mlx5_ib_odp_init_one(dev);
3175 if (err)
3176 goto err_rsrc;
3177
3178 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3179 err = mlx5_ib_alloc_q_counters(dev);
3180 if (err)
3181 goto err_odp;
3182 }
3183
3184 err = ib_register_device(&dev->ib_dev, NULL);
3185 if (err)
3186 goto err_q_cnt;
3187
3188 err = create_umr_res(dev);
3189 if (err)
3190 goto err_dev;
3191
3192 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3193 err = device_create_file(&dev->ib_dev.dev,
3194 mlx5_class_attributes[i]);
3195 if (err)
3196 goto err_umrc;
3197 }
3198
3199 dev->ib_active = true;
3200
3201 return dev;
3202
3203 err_umrc:
3204 destroy_umrc_res(dev);
3205
3206 err_dev:
3207 ib_unregister_device(&dev->ib_dev);
3208
3209 err_q_cnt:
3210 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3211 mlx5_ib_dealloc_q_counters(dev);
3212
3213 err_odp:
3214 mlx5_ib_odp_remove_one(dev);
3215
3216 err_rsrc:
3217 destroy_dev_resources(&dev->devr);
3218
3219 err_disable_roce:
3220 if (ll == IB_LINK_LAYER_ETHERNET) {
3221 mlx5_disable_roce(dev);
3222 mlx5_remove_roce_notifier(dev);
3223 }
3224
3225 err_free_port:
3226 kfree(dev->port);
3227
3228 err_dealloc:
3229 ib_dealloc_device((struct ib_device *)dev);
3230
3231 return NULL;
3232 }
3233
3234 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3235 {
3236 struct mlx5_ib_dev *dev = context;
3237 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3238
3239 mlx5_remove_roce_notifier(dev);
3240 ib_unregister_device(&dev->ib_dev);
3241 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3242 mlx5_ib_dealloc_q_counters(dev);
3243 destroy_umrc_res(dev);
3244 mlx5_ib_odp_remove_one(dev);
3245 destroy_dev_resources(&dev->devr);
3246 if (ll == IB_LINK_LAYER_ETHERNET)
3247 mlx5_disable_roce(dev);
3248 kfree(dev->port);
3249 ib_dealloc_device(&dev->ib_dev);
3250 }
3251
3252 static struct mlx5_interface mlx5_ib_interface = {
3253 .add = mlx5_ib_add,
3254 .remove = mlx5_ib_remove,
3255 .event = mlx5_ib_event,
3256 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3257 };
3258
3259 static int __init mlx5_ib_init(void)
3260 {
3261 int err;
3262
3263 if (deprecated_prof_sel != 2)
3264 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3265
3266 err = mlx5_ib_odp_init();
3267 if (err)
3268 return err;
3269
3270 err = mlx5_register_interface(&mlx5_ib_interface);
3271 if (err)
3272 goto clean_odp;
3273
3274 return err;
3275
3276 clean_odp:
3277 mlx5_ib_odp_cleanup();
3278 return err;
3279 }
3280
3281 static void __exit mlx5_ib_cleanup(void)
3282 {
3283 mlx5_unregister_interface(&mlx5_ib_interface);
3284 mlx5_ib_odp_cleanup();
3285 }
3286
3287 module_init(mlx5_ib_init);
3288 module_exit(mlx5_ib_cleanup);
Linux with added FPC-III support