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Revert "ALSA: hda: Flush interrupts on disabling"
[linux/fpc-iii.git] / sound / pci / hda / hda_intel.c
blobf2f1d9fd848c84f90b553c650e0314eb53232fba
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #include <asm/cpufeature.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <sound/hdaudio.h>
62 #include <sound/hda_i915.h>
63 #include <linux/vgaarb.h>
64 #include <linux/vga_switcheroo.h>
65 #include <linux/firmware.h>
66 #include "hda_codec.h"
67 #include "hda_controller.h"
68 #include "hda_intel.h"
69
70 #define CREATE_TRACE_POINTS
71 #include "hda_intel_trace.h"
72
73 /* position fix mode */
74 enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
80 };
81
82 /* Defines for ATI HD Audio support in SB450 south bridge */
83 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
84 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
85
86 /* Defines for Nvidia HDA support */
87 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
88 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
89 #define NVIDIA_HDA_ISTRM_COH 0x4d
90 #define NVIDIA_HDA_OSTRM_COH 0x4c
91 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
92
93 /* Defines for Intel SCH HDA snoop control */
94 #define INTEL_HDA_CGCTL 0x48
95 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
96 #define INTEL_SCH_HDA_DEVC 0x78
97 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
98
99 /* Define IN stream 0 FIFO size offset in VIA controller */
100 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
101 /* Define VIA HD Audio Device ID*/
102 #define VIA_HDAC_DEVICE_ID 0x3288
103
104 /* max number of SDs */
105 /* ICH, ATI and VIA have 4 playback and 4 capture */
106 #define ICH6_NUM_CAPTURE 4
107 #define ICH6_NUM_PLAYBACK 4
108
109 /* ULI has 6 playback and 5 capture */
110 #define ULI_NUM_CAPTURE 5
111 #define ULI_NUM_PLAYBACK 6
112
113 /* ATI HDMI may have up to 8 playbacks and 0 capture */
114 #define ATIHDMI_NUM_CAPTURE 0
115 #define ATIHDMI_NUM_PLAYBACK 8
116
117 /* TERA has 4 playback and 3 capture */
118 #define TERA_NUM_CAPTURE 3
119 #define TERA_NUM_PLAYBACK 4
120
121
122 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
123 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
124 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
125 static char *model[SNDRV_CARDS];
126 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
127 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
129 static int probe_only[SNDRV_CARDS];
130 static int jackpoll_ms[SNDRV_CARDS];
131 static bool single_cmd;
132 static int enable_msi = -1;
133 #ifdef CONFIG_SND_HDA_PATCH_LOADER
134 static char *patch[SNDRV_CARDS];
135 #endif
136 #ifdef CONFIG_SND_HDA_INPUT_BEEP
137 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
138 CONFIG_SND_HDA_INPUT_BEEP_MODE};
139 #endif
140
141 module_param_array(index, int, NULL, 0444);
142 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
143 module_param_array(id, charp, NULL, 0444);
144 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
145 module_param_array(enable, bool, NULL, 0444);
146 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
147 module_param_array(model, charp, NULL, 0444);
148 MODULE_PARM_DESC(model, "Use the given board model.");
149 module_param_array(position_fix, int, NULL, 0444);
150 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
151 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
152 module_param_array(bdl_pos_adj, int, NULL, 0644);
153 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
154 module_param_array(probe_mask, int, NULL, 0444);
155 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
156 module_param_array(probe_only, int, NULL, 0444);
157 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
158 module_param_array(jackpoll_ms, int, NULL, 0444);
159 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
160 module_param(single_cmd, bool, 0444);
161 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
162 "(for debugging only).");
163 module_param(enable_msi, bint, 0444);
164 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
165 #ifdef CONFIG_SND_HDA_PATCH_LOADER
166 module_param_array(patch, charp, NULL, 0444);
167 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
168 #endif
169 #ifdef CONFIG_SND_HDA_INPUT_BEEP
170 module_param_array(beep_mode, bool, NULL, 0444);
171 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
172 "(0=off, 1=on) (default=1).");
173 #endif
174
175 #ifdef CONFIG_PM
176 static int param_set_xint(const char *val, const struct kernel_param *kp);
177 static const struct kernel_param_ops param_ops_xint = {
178 .set = param_set_xint,
179 .get = param_get_int,
180 };
181 #define param_check_xint param_check_int
182
183 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
184 module_param(power_save, xint, 0644);
185 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
186 "(in second, 0 = disable).");
187
188 static bool pm_blacklist = true;
189 module_param(pm_blacklist, bool, 0644);
190 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
191
192 /* reset the HD-audio controller in power save mode.
193 * this may give more power-saving, but will take longer time to
194 * wake up.
195 */
196 static bool power_save_controller = 1;
197 module_param(power_save_controller, bool, 0644);
198 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
199 #else
200 #define power_save 0
201 #endif /* CONFIG_PM */
202
203 static int align_buffer_size = -1;
204 module_param(align_buffer_size, bint, 0644);
205 MODULE_PARM_DESC(align_buffer_size,
206 "Force buffer and period sizes to be multiple of 128 bytes.");
207
208 #ifdef CONFIG_X86
209 static int hda_snoop = -1;
210 module_param_named(snoop, hda_snoop, bint, 0444);
211 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
212 #else
213 #define hda_snoop true
214 #endif
215
216
217 MODULE_LICENSE("GPL");
218 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
219 "{Intel, ICH6M},"
220 "{Intel, ICH7},"
221 "{Intel, ESB2},"
222 "{Intel, ICH8},"
223 "{Intel, ICH9},"
224 "{Intel, ICH10},"
225 "{Intel, PCH},"
226 "{Intel, CPT},"
227 "{Intel, PPT},"
228 "{Intel, LPT},"
229 "{Intel, LPT_LP},"
230 "{Intel, WPT_LP},"
231 "{Intel, SPT},"
232 "{Intel, SPT_LP},"
233 "{Intel, HPT},"
234 "{Intel, PBG},"
235 "{Intel, SCH},"
236 "{ATI, SB450},"
237 "{ATI, SB600},"
238 "{ATI, RS600},"
239 "{ATI, RS690},"
240 "{ATI, RS780},"
241 "{ATI, R600},"
242 "{ATI, RV630},"
243 "{ATI, RV610},"
244 "{ATI, RV670},"
245 "{ATI, RV635},"
246 "{ATI, RV620},"
247 "{ATI, RV770},"
248 "{VIA, VT8251},"
249 "{VIA, VT8237A},"
250 "{SiS, SIS966},"
251 "{ULI, M5461}}");
252 MODULE_DESCRIPTION("Intel HDA driver");
253
254 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
255 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
256 #define SUPPORT_VGA_SWITCHEROO
257 #endif
258 #endif
259
260
261 /*
262 */
263
264 /* driver types */
265 enum {
266 AZX_DRIVER_ICH,
267 AZX_DRIVER_PCH,
268 AZX_DRIVER_SCH,
269 AZX_DRIVER_HDMI,
270 AZX_DRIVER_ATI,
271 AZX_DRIVER_ATIHDMI,
272 AZX_DRIVER_ATIHDMI_NS,
273 AZX_DRIVER_VIA,
274 AZX_DRIVER_SIS,
275 AZX_DRIVER_ULI,
276 AZX_DRIVER_NVIDIA,
277 AZX_DRIVER_TERA,
278 AZX_DRIVER_CTX,
279 AZX_DRIVER_CTHDA,
280 AZX_DRIVER_CMEDIA,
281 AZX_DRIVER_GENERIC,
282 AZX_NUM_DRIVERS, /* keep this as last entry */
283 };
284
285 #define azx_get_snoop_type(chip) \
286 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
287 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
288
289 /* quirks for old Intel chipsets */
290 #define AZX_DCAPS_INTEL_ICH \
291 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
292
293 /* quirks for Intel PCH */
294 #define AZX_DCAPS_INTEL_PCH_BASE \
295 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
296 AZX_DCAPS_SNOOP_TYPE(SCH))
297
298 /* PCH up to IVB; no runtime PM */
299 #define AZX_DCAPS_INTEL_PCH_NOPM \
300 (AZX_DCAPS_INTEL_PCH_BASE)
301
302 /* PCH for HSW/BDW; with runtime PM */
303 #define AZX_DCAPS_INTEL_PCH \
304 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
305
306 /* HSW HDMI */
307 #define AZX_DCAPS_INTEL_HASWELL \
308 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
309 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
310 AZX_DCAPS_SNOOP_TYPE(SCH))
311
312 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
313 #define AZX_DCAPS_INTEL_BROADWELL \
314 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
315 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
316 AZX_DCAPS_SNOOP_TYPE(SCH))
317
318 #define AZX_DCAPS_INTEL_BAYTRAIL \
319 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
320
321 #define AZX_DCAPS_INTEL_BRASWELL \
322 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
323
324 #define AZX_DCAPS_INTEL_SKYLAKE \
325 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
326 AZX_DCAPS_I915_POWERWELL)
327
328 #define AZX_DCAPS_INTEL_BROXTON \
329 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
330 AZX_DCAPS_I915_POWERWELL)
331
332 /* quirks for ATI SB / AMD Hudson */
333 #define AZX_DCAPS_PRESET_ATI_SB \
334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
335 AZX_DCAPS_SNOOP_TYPE(ATI))
336
337 /* quirks for ATI/AMD HDMI */
338 #define AZX_DCAPS_PRESET_ATI_HDMI \
339 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
340 AZX_DCAPS_NO_MSI64)
341
342 /* quirks for ATI HDMI with snoop off */
343 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
344 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
345
346 /* quirks for Nvidia */
347 #define AZX_DCAPS_PRESET_NVIDIA \
348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
349 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
350
351 #define AZX_DCAPS_PRESET_CTHDA \
352 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
353 AZX_DCAPS_NO_64BIT |\
354 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
355
356 /*
357 * vga_switcheroo support
358 */
359 #ifdef SUPPORT_VGA_SWITCHEROO
360 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
361 #else
362 #define use_vga_switcheroo(chip) 0
363 #endif
364
365 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
366 ((pci)->device == 0x0c0c) || \
367 ((pci)->device == 0x0d0c) || \
368 ((pci)->device == 0x160c))
369
370 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
371 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
372 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
373 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
374 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
375 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
376 #define IS_GLK(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x3198)
377 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
378 IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci) || \
379 IS_GLK(pci)
380
381 static char *driver_short_names[] = {
382 [AZX_DRIVER_ICH] = "HDA Intel",
383 [AZX_DRIVER_PCH] = "HDA Intel PCH",
384 [AZX_DRIVER_SCH] = "HDA Intel MID",
385 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
386 [AZX_DRIVER_ATI] = "HDA ATI SB",
387 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
388 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
389 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
390 [AZX_DRIVER_SIS] = "HDA SIS966",
391 [AZX_DRIVER_ULI] = "HDA ULI M5461",
392 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
393 [AZX_DRIVER_TERA] = "HDA Teradici",
394 [AZX_DRIVER_CTX] = "HDA Creative",
395 [AZX_DRIVER_CTHDA] = "HDA Creative",
396 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
397 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
398 };
399
400 #ifdef CONFIG_X86
401 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
402 {
403 int pages;
404
405 if (azx_snoop(chip))
406 return;
407 if (!dmab || !dmab->area || !dmab->bytes)
408 return;
409
410 #ifdef CONFIG_SND_DMA_SGBUF
411 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
412 struct snd_sg_buf *sgbuf = dmab->private_data;
413 if (!chip->uc_buffer)
414 return; /* deal with only CORB/RIRB buffers */
415 if (on)
416 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
417 else
418 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
419 return;
420 }
421 #endif
422
423 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
424 if (on)
425 set_memory_wc((unsigned long)dmab->area, pages);
426 else
427 set_memory_wb((unsigned long)dmab->area, pages);
428 }
429
430 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
431 bool on)
432 {
433 __mark_pages_wc(chip, buf, on);
434 }
435 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
436 struct snd_pcm_substream *substream, bool on)
437 {
438 if (azx_dev->wc_marked != on) {
439 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
440 azx_dev->wc_marked = on;
441 }
442 }
443 #else
444 /* NOP for other archs */
445 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
446 bool on)
447 {
448 }
449 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
450 struct snd_pcm_substream *substream, bool on)
451 {
452 }
453 #endif
454
455 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
456
457 /*
458 * initialize the PCI registers
459 */
460 /* update bits in a PCI register byte */
461 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
462 unsigned char mask, unsigned char val)
463 {
464 unsigned char data;
465
466 pci_read_config_byte(pci, reg, &data);
467 data &= ~mask;
468 data |= (val & mask);
469 pci_write_config_byte(pci, reg, data);
470 }
471
472 static void azx_init_pci(struct azx *chip)
473 {
474 int snoop_type = azx_get_snoop_type(chip);
475
476 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
477 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
478 * Ensuring these bits are 0 clears playback static on some HD Audio
479 * codecs.
480 * The PCI register TCSEL is defined in the Intel manuals.
481 */
482 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
483 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
484 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
485 }
486
487 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
488 * we need to enable snoop.
489 */
490 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
491 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
492 azx_snoop(chip));
493 update_pci_byte(chip->pci,
494 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
495 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
496 }
497
498 /* For NVIDIA HDA, enable snoop */
499 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
500 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
501 azx_snoop(chip));
502 update_pci_byte(chip->pci,
503 NVIDIA_HDA_TRANSREG_ADDR,
504 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
505 update_pci_byte(chip->pci,
506 NVIDIA_HDA_ISTRM_COH,
507 0x01, NVIDIA_HDA_ENABLE_COHBIT);
508 update_pci_byte(chip->pci,
509 NVIDIA_HDA_OSTRM_COH,
510 0x01, NVIDIA_HDA_ENABLE_COHBIT);
511 }
512
513 /* Enable SCH/PCH snoop if needed */
514 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
515 unsigned short snoop;
516 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
517 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
518 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
519 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
520 if (!azx_snoop(chip))
521 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
522 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
523 pci_read_config_word(chip->pci,
524 INTEL_SCH_HDA_DEVC, &snoop);
525 }
526 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
527 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
528 "Disabled" : "Enabled");
529 }
530 }
531
532 /*
533 * In BXT-P A0, HD-Audio DMA requests is later than expected,
534 * and makes an audio stream sensitive to system latencies when
535 * 24/32 bits are playing.
536 * Adjusting threshold of DMA fifo to force the DMA request
537 * sooner to improve latency tolerance at the expense of power.
538 */
539 static void bxt_reduce_dma_latency(struct azx *chip)
540 {
541 u32 val;
542
543 val = azx_readl(chip, SKL_EM4L);
544 val &= (0x3 << 20);
545 azx_writel(chip, SKL_EM4L, val);
546 }
547
548 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
549 {
550 struct hdac_bus *bus = azx_bus(chip);
551 struct pci_dev *pci = chip->pci;
552 u32 val;
553
554 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
555 snd_hdac_set_codec_wakeup(bus, true);
556 if (IS_SKL_PLUS(pci)) {
557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
558 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
560 }
561 azx_init_chip(chip, full_reset);
562 if (IS_SKL_PLUS(pci)) {
563 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
564 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
565 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
566 }
567 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
568 snd_hdac_set_codec_wakeup(bus, false);
569
570 /* reduce dma latency to avoid noise */
571 if (IS_BXT(pci))
572 bxt_reduce_dma_latency(chip);
573 }
574
575 /* calculate runtime delay from LPIB */
576 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
577 unsigned int pos)
578 {
579 struct snd_pcm_substream *substream = azx_dev->core.substream;
580 int stream = substream->stream;
581 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
582 int delay;
583
584 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
585 delay = pos - lpib_pos;
586 else
587 delay = lpib_pos - pos;
588 if (delay < 0) {
589 if (delay >= azx_dev->core.delay_negative_threshold)
590 delay = 0;
591 else
592 delay += azx_dev->core.bufsize;
593 }
594
595 if (delay >= azx_dev->core.period_bytes) {
596 dev_info(chip->card->dev,
597 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
598 delay, azx_dev->core.period_bytes);
599 delay = 0;
600 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
601 chip->get_delay[stream] = NULL;
602 }
603
604 return bytes_to_frames(substream->runtime, delay);
605 }
606
607 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
608
609 /* called from IRQ */
610 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
611 {
612 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
613 int ok;
614
615 ok = azx_position_ok(chip, azx_dev);
616 if (ok == 1) {
617 azx_dev->irq_pending = 0;
618 return ok;
619 } else if (ok == 0) {
620 /* bogus IRQ, process it later */
621 azx_dev->irq_pending = 1;
622 schedule_work(&hda->irq_pending_work);
623 }
624 return 0;
625 }
626
627 /* Enable/disable i915 display power for the link */
628 static int azx_intel_link_power(struct azx *chip, bool enable)
629 {
630 struct hdac_bus *bus = azx_bus(chip);
631
632 return snd_hdac_display_power(bus, enable);
633 }
634
635 /*
636 * Check whether the current DMA position is acceptable for updating
637 * periods. Returns non-zero if it's OK.
638 *
639 * Many HD-audio controllers appear pretty inaccurate about
640 * the update-IRQ timing. The IRQ is issued before actually the
641 * data is processed. So, we need to process it afterwords in a
642 * workqueue.
643 */
644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
645 {
646 struct snd_pcm_substream *substream = azx_dev->core.substream;
647 int stream = substream->stream;
648 u32 wallclk;
649 unsigned int pos;
650
651 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
652 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
653 return -1; /* bogus (too early) interrupt */
654
655 if (chip->get_position[stream])
656 pos = chip->get_position[stream](chip, azx_dev);
657 else { /* use the position buffer as default */
658 pos = azx_get_pos_posbuf(chip, azx_dev);
659 if (!pos || pos == (u32)-1) {
660 dev_info(chip->card->dev,
661 "Invalid position buffer, using LPIB read method instead.\n");
662 chip->get_position[stream] = azx_get_pos_lpib;
663 if (chip->get_position[0] == azx_get_pos_lpib &&
664 chip->get_position[1] == azx_get_pos_lpib)
665 azx_bus(chip)->use_posbuf = false;
666 pos = azx_get_pos_lpib(chip, azx_dev);
667 chip->get_delay[stream] = NULL;
668 } else {
669 chip->get_position[stream] = azx_get_pos_posbuf;
670 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
671 chip->get_delay[stream] = azx_get_delay_from_lpib;
672 }
673 }
674
675 if (pos >= azx_dev->core.bufsize)
676 pos = 0;
677
678 if (WARN_ONCE(!azx_dev->core.period_bytes,
679 "hda-intel: zero azx_dev->period_bytes"))
680 return -1; /* this shouldn't happen! */
681 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
682 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
683 /* NG - it's below the first next period boundary */
684 return chip->bdl_pos_adj ? 0 : -1;
685 azx_dev->core.start_wallclk += wallclk;
686 return 1; /* OK, it's fine */
687 }
688
689 /*
690 * The work for pending PCM period updates.
691 */
692 static void azx_irq_pending_work(struct work_struct *work)
693 {
694 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
695 struct azx *chip = &hda->chip;
696 struct hdac_bus *bus = azx_bus(chip);
697 struct hdac_stream *s;
698 int pending, ok;
699
700 if (!hda->irq_pending_warned) {
701 dev_info(chip->card->dev,
702 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
703 chip->card->number);
704 hda->irq_pending_warned = 1;
705 }
706
707 for (;;) {
708 pending = 0;
709 spin_lock_irq(&bus->reg_lock);
710 list_for_each_entry(s, &bus->stream_list, list) {
711 struct azx_dev *azx_dev = stream_to_azx_dev(s);
712 if (!azx_dev->irq_pending ||
713 !s->substream ||
714 !s->running)
715 continue;
716 ok = azx_position_ok(chip, azx_dev);
717 if (ok > 0) {
718 azx_dev->irq_pending = 0;
719 spin_unlock(&bus->reg_lock);
720 snd_pcm_period_elapsed(s->substream);
721 spin_lock(&bus->reg_lock);
722 } else if (ok < 0) {
723 pending = 0; /* too early */
724 } else
725 pending++;
726 }
727 spin_unlock_irq(&bus->reg_lock);
728 if (!pending)
729 return;
730 msleep(1);
731 }
732 }
733
734 /* clear irq_pending flags and assure no on-going workq */
735 static void azx_clear_irq_pending(struct azx *chip)
736 {
737 struct hdac_bus *bus = azx_bus(chip);
738 struct hdac_stream *s;
739
740 spin_lock_irq(&bus->reg_lock);
741 list_for_each_entry(s, &bus->stream_list, list) {
742 struct azx_dev *azx_dev = stream_to_azx_dev(s);
743 azx_dev->irq_pending = 0;
744 }
745 spin_unlock_irq(&bus->reg_lock);
746 }
747
748 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
749 {
750 struct hdac_bus *bus = azx_bus(chip);
751
752 if (request_irq(chip->pci->irq, azx_interrupt,
753 chip->msi ? 0 : IRQF_SHARED,
754 chip->card->irq_descr, chip)) {
755 dev_err(chip->card->dev,
756 "unable to grab IRQ %d, disabling device\n",
757 chip->pci->irq);
758 if (do_disconnect)
759 snd_card_disconnect(chip->card);
760 return -1;
761 }
762 bus->irq = chip->pci->irq;
763 pci_intx(chip->pci, !chip->msi);
764 return 0;
765 }
766
767 /* get the current DMA position with correction on VIA chips */
768 static unsigned int azx_via_get_position(struct azx *chip,
769 struct azx_dev *azx_dev)
770 {
771 unsigned int link_pos, mini_pos, bound_pos;
772 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
773 unsigned int fifo_size;
774
775 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
776 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
777 /* Playback, no problem using link position */
778 return link_pos;
779 }
780
781 /* Capture */
782 /* For new chipset,
783 * use mod to get the DMA position just like old chipset
784 */
785 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
786 mod_dma_pos %= azx_dev->core.period_bytes;
787
788 /* azx_dev->fifo_size can't get FIFO size of in stream.
789 * Get from base address + offset.
790 */
791 fifo_size = readw(azx_bus(chip)->remap_addr +
792 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
793
794 if (azx_dev->insufficient) {
795 /* Link position never gather than FIFO size */
796 if (link_pos <= fifo_size)
797 return 0;
798
799 azx_dev->insufficient = 0;
800 }
801
802 if (link_pos <= fifo_size)
803 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
804 else
805 mini_pos = link_pos - fifo_size;
806
807 /* Find nearest previous boudary */
808 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
809 mod_link_pos = link_pos % azx_dev->core.period_bytes;
810 if (mod_link_pos >= fifo_size)
811 bound_pos = link_pos - mod_link_pos;
812 else if (mod_dma_pos >= mod_mini_pos)
813 bound_pos = mini_pos - mod_mini_pos;
814 else {
815 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
816 if (bound_pos >= azx_dev->core.bufsize)
817 bound_pos = 0;
818 }
819
820 /* Calculate real DMA position we want */
821 return bound_pos + mod_dma_pos;
822 }
823
824 #ifdef CONFIG_PM
825 static DEFINE_MUTEX(card_list_lock);
826 static LIST_HEAD(card_list);
827
828 static void azx_add_card_list(struct azx *chip)
829 {
830 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
831 mutex_lock(&card_list_lock);
832 list_add(&hda->list, &card_list);
833 mutex_unlock(&card_list_lock);
834 }
835
836 static void azx_del_card_list(struct azx *chip)
837 {
838 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
839 mutex_lock(&card_list_lock);
840 list_del_init(&hda->list);
841 mutex_unlock(&card_list_lock);
842 }
843
844 /* trigger power-save check at writing parameter */
845 static int param_set_xint(const char *val, const struct kernel_param *kp)
846 {
847 struct hda_intel *hda;
848 struct azx *chip;
849 int prev = power_save;
850 int ret = param_set_int(val, kp);
851
852 if (ret || prev == power_save)
853 return ret;
854
855 mutex_lock(&card_list_lock);
856 list_for_each_entry(hda, &card_list, list) {
857 chip = &hda->chip;
858 if (!hda->probe_continued || chip->disabled)
859 continue;
860 snd_hda_set_power_save(&chip->bus, power_save * 1000);
861 }
862 mutex_unlock(&card_list_lock);
863 return 0;
864 }
865 #else
866 #define azx_add_card_list(chip) /* NOP */
867 #define azx_del_card_list(chip) /* NOP */
868 #endif /* CONFIG_PM */
869
870 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
871 /*
872 * power management
873 */
874 static int azx_suspend(struct device *dev)
875 {
876 struct snd_card *card = dev_get_drvdata(dev);
877 struct azx *chip;
878 struct hda_intel *hda;
879 struct hdac_bus *bus;
880
881 if (!card)
882 return 0;
883
884 chip = card->private_data;
885 hda = container_of(chip, struct hda_intel, chip);
886 if (chip->disabled || hda->init_failed || !chip->running)
887 return 0;
888
889 bus = azx_bus(chip);
890 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
891 azx_clear_irq_pending(chip);
892 azx_stop_chip(chip);
893 azx_enter_link_reset(chip);
894 if (bus->irq >= 0) {
895 free_irq(bus->irq, chip);
896 bus->irq = -1;
897 }
898
899 if (chip->msi)
900 pci_disable_msi(chip->pci);
901 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
902 && hda->need_i915_power)
903 snd_hdac_display_power(bus, false);
904
905 trace_azx_suspend(chip);
906 return 0;
907 }
908
909 static int azx_resume(struct device *dev)
910 {
911 struct pci_dev *pci = to_pci_dev(dev);
912 struct snd_card *card = dev_get_drvdata(dev);
913 struct azx *chip;
914 struct hda_intel *hda;
915 struct hdac_bus *bus;
916
917 if (!card)
918 return 0;
919
920 chip = card->private_data;
921 hda = container_of(chip, struct hda_intel, chip);
922 bus = azx_bus(chip);
923 if (chip->disabled || hda->init_failed || !chip->running)
924 return 0;
925
926 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
927 snd_hdac_display_power(bus, true);
928 if (hda->need_i915_power)
929 snd_hdac_i915_set_bclk(bus);
930 }
931
932 if (chip->msi)
933 if (pci_enable_msi(pci) < 0)
934 chip->msi = 0;
935 if (azx_acquire_irq(chip, 1) < 0)
936 return -EIO;
937 azx_init_pci(chip);
938
939 hda_intel_init_chip(chip, true);
940
941 /* power down again for link-controlled chips */
942 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
943 !hda->need_i915_power)
944 snd_hdac_display_power(bus, false);
945
946 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
947
948 trace_azx_resume(chip);
949 return 0;
950 }
951 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
952
953 #ifdef CONFIG_PM_SLEEP
954 /* put codec down to D3 at hibernation for Intel SKL+;
955 * otherwise BIOS may still access the codec and screw up the driver
956 */
957 static int azx_freeze_noirq(struct device *dev)
958 {
959 struct pci_dev *pci = to_pci_dev(dev);
960
961 if (IS_SKL_PLUS(pci))
962 pci_set_power_state(pci, PCI_D3hot);
963
964 return 0;
965 }
966
967 static int azx_thaw_noirq(struct device *dev)
968 {
969 struct pci_dev *pci = to_pci_dev(dev);
970
971 if (IS_SKL_PLUS(pci))
972 pci_set_power_state(pci, PCI_D0);
973
974 return 0;
975 }
976 #endif /* CONFIG_PM_SLEEP */
977
978 #ifdef CONFIG_PM
979 static int azx_runtime_suspend(struct device *dev)
980 {
981 struct snd_card *card = dev_get_drvdata(dev);
982 struct azx *chip;
983 struct hda_intel *hda;
984
985 if (!card)
986 return 0;
987
988 chip = card->private_data;
989 hda = container_of(chip, struct hda_intel, chip);
990 if (chip->disabled || hda->init_failed)
991 return 0;
992
993 if (!azx_has_pm_runtime(chip))
994 return 0;
995
996 /* enable controller wake up event */
997 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
998 STATESTS_INT_MASK);
999
1000 azx_stop_chip(chip);
1001 azx_enter_link_reset(chip);
1002 azx_clear_irq_pending(chip);
1003 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1004 && hda->need_i915_power)
1005 snd_hdac_display_power(azx_bus(chip), false);
1006
1007 trace_azx_runtime_suspend(chip);
1008 return 0;
1009 }
1010
1011 static int azx_runtime_resume(struct device *dev)
1012 {
1013 struct snd_card *card = dev_get_drvdata(dev);
1014 struct azx *chip;
1015 struct hda_intel *hda;
1016 struct hdac_bus *bus;
1017 struct hda_codec *codec;
1018 int status;
1019
1020 if (!card)
1021 return 0;
1022
1023 chip = card->private_data;
1024 hda = container_of(chip, struct hda_intel, chip);
1025 bus = azx_bus(chip);
1026 if (chip->disabled || hda->init_failed)
1027 return 0;
1028
1029 if (!azx_has_pm_runtime(chip))
1030 return 0;
1031
1032 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1033 snd_hdac_display_power(bus, true);
1034 if (hda->need_i915_power)
1035 snd_hdac_i915_set_bclk(bus);
1036 }
1037
1038 /* Read STATESTS before controller reset */
1039 status = azx_readw(chip, STATESTS);
1040
1041 azx_init_pci(chip);
1042 hda_intel_init_chip(chip, true);
1043
1044 if (status) {
1045 list_for_each_codec(codec, &chip->bus)
1046 if (status & (1 << codec->addr))
1047 schedule_delayed_work(&codec->jackpoll_work,
1048 codec->jackpoll_interval);
1049 }
1050
1051 /* disable controller Wake Up event*/
1052 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1053 ~STATESTS_INT_MASK);
1054
1055 /* power down again for link-controlled chips */
1056 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1057 !hda->need_i915_power)
1058 snd_hdac_display_power(bus, false);
1059
1060 trace_azx_runtime_resume(chip);
1061 return 0;
1062 }
1063
1064 static int azx_runtime_idle(struct device *dev)
1065 {
1066 struct snd_card *card = dev_get_drvdata(dev);
1067 struct azx *chip;
1068 struct hda_intel *hda;
1069
1070 if (!card)
1071 return 0;
1072
1073 chip = card->private_data;
1074 hda = container_of(chip, struct hda_intel, chip);
1075 if (chip->disabled || hda->init_failed)
1076 return 0;
1077
1078 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1079 azx_bus(chip)->codec_powered || !chip->running)
1080 return -EBUSY;
1081
1082 return 0;
1083 }
1084
1085 static const struct dev_pm_ops azx_pm = {
1086 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1087 #ifdef CONFIG_PM_SLEEP
1088 .freeze_noirq = azx_freeze_noirq,
1089 .thaw_noirq = azx_thaw_noirq,
1090 #endif
1091 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1092 };
1093
1094 #define AZX_PM_OPS &azx_pm
1095 #else
1096 #define AZX_PM_OPS NULL
1097 #endif /* CONFIG_PM */
1098
1099
1100 static int azx_probe_continue(struct azx *chip);
1101
1102 #ifdef SUPPORT_VGA_SWITCHEROO
1103 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1104
1105 static void azx_vs_set_state(struct pci_dev *pci,
1106 enum vga_switcheroo_state state)
1107 {
1108 struct snd_card *card = pci_get_drvdata(pci);
1109 struct azx *chip = card->private_data;
1110 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1111 bool disabled;
1112
1113 wait_for_completion(&hda->probe_wait);
1114 if (hda->init_failed)
1115 return;
1116
1117 disabled = (state == VGA_SWITCHEROO_OFF);
1118 if (chip->disabled == disabled)
1119 return;
1120
1121 if (!hda->probe_continued) {
1122 chip->disabled = disabled;
1123 if (!disabled) {
1124 dev_info(chip->card->dev,
1125 "Start delayed initialization\n");
1126 if (azx_probe_continue(chip) < 0) {
1127 dev_err(chip->card->dev, "initialization error\n");
1128 hda->init_failed = true;
1129 }
1130 }
1131 } else {
1132 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1133 disabled ? "Disabling" : "Enabling");
1134 if (disabled) {
1135 pm_runtime_put_sync_suspend(card->dev);
1136 azx_suspend(card->dev);
1137 /* when we get suspended by vga_switcheroo we end up in D3cold,
1138 * however we have no ACPI handle, so pci/acpi can't put us there,
1139 * put ourselves there */
1140 pci->current_state = PCI_D3cold;
1141 chip->disabled = true;
1142 if (snd_hda_lock_devices(&chip->bus))
1143 dev_warn(chip->card->dev,
1144 "Cannot lock devices!\n");
1145 } else {
1146 snd_hda_unlock_devices(&chip->bus);
1147 pm_runtime_get_noresume(card->dev);
1148 chip->disabled = false;
1149 azx_resume(card->dev);
1150 }
1151 }
1152 }
1153
1154 static bool azx_vs_can_switch(struct pci_dev *pci)
1155 {
1156 struct snd_card *card = pci_get_drvdata(pci);
1157 struct azx *chip = card->private_data;
1158 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1159
1160 wait_for_completion(&hda->probe_wait);
1161 if (hda->init_failed)
1162 return false;
1163 if (chip->disabled || !hda->probe_continued)
1164 return true;
1165 if (snd_hda_lock_devices(&chip->bus))
1166 return false;
1167 snd_hda_unlock_devices(&chip->bus);
1168 return true;
1169 }
1170
1171 static void init_vga_switcheroo(struct azx *chip)
1172 {
1173 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1174 struct pci_dev *p = get_bound_vga(chip->pci);
1175 if (p) {
1176 dev_info(chip->card->dev,
1177 "Handle vga_switcheroo audio client\n");
1178 hda->use_vga_switcheroo = 1;
1179 pci_dev_put(p);
1180 }
1181 }
1182
1183 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1184 .set_gpu_state = azx_vs_set_state,
1185 .can_switch = azx_vs_can_switch,
1186 };
1187
1188 static int register_vga_switcheroo(struct azx *chip)
1189 {
1190 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1191 int err;
1192
1193 if (!hda->use_vga_switcheroo)
1194 return 0;
1195 /* FIXME: currently only handling DIS controller
1196 * is there any machine with two switchable HDMI audio controllers?
1197 */
1198 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1199 VGA_SWITCHEROO_DIS);
1200 if (err < 0)
1201 return err;
1202 hda->vga_switcheroo_registered = 1;
1203
1204 /* register as an optimus hdmi audio power domain */
1205 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1206 &hda->hdmi_pm_domain);
1207 return 0;
1208 }
1209 #else
1210 #define init_vga_switcheroo(chip) /* NOP */
1211 #define register_vga_switcheroo(chip) 0
1212 #define check_hdmi_disabled(pci) false
1213 #endif /* SUPPORT_VGA_SWITCHER */
1214
1215 /*
1216 * destructor
1217 */
1218 static int azx_free(struct azx *chip)
1219 {
1220 struct pci_dev *pci = chip->pci;
1221 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1222 struct hdac_bus *bus = azx_bus(chip);
1223
1224 if (azx_has_pm_runtime(chip) && chip->running)
1225 pm_runtime_get_noresume(&pci->dev);
1226
1227 azx_del_card_list(chip);
1228
1229 hda->init_failed = 1; /* to be sure */
1230 complete_all(&hda->probe_wait);
1231
1232 if (use_vga_switcheroo(hda)) {
1233 if (chip->disabled && hda->probe_continued)
1234 snd_hda_unlock_devices(&chip->bus);
1235 if (hda->vga_switcheroo_registered) {
1236 vga_switcheroo_unregister_client(chip->pci);
1237 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1238 }
1239 }
1240
1241 if (bus->chip_init) {
1242 azx_clear_irq_pending(chip);
1243 azx_stop_all_streams(chip);
1244 azx_stop_chip(chip);
1245 }
1246
1247 if (bus->irq >= 0)
1248 free_irq(bus->irq, (void*)chip);
1249 if (chip->msi)
1250 pci_disable_msi(chip->pci);
1251 iounmap(bus->remap_addr);
1252
1253 azx_free_stream_pages(chip);
1254 azx_free_streams(chip);
1255 snd_hdac_bus_exit(bus);
1256
1257 if (chip->region_requested)
1258 pci_release_regions(chip->pci);
1259
1260 pci_disable_device(chip->pci);
1261 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1262 release_firmware(chip->fw);
1263 #endif
1264
1265 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1266 if (hda->need_i915_power)
1267 snd_hdac_display_power(bus, false);
1268 snd_hdac_i915_exit(bus);
1269 }
1270 kfree(hda);
1271
1272 return 0;
1273 }
1274
1275 static int azx_dev_disconnect(struct snd_device *device)
1276 {
1277 struct azx *chip = device->device_data;
1278
1279 chip->bus.shutdown = 1;
1280 return 0;
1281 }
1282
1283 static int azx_dev_free(struct snd_device *device)
1284 {
1285 return azx_free(device->device_data);
1286 }
1287
1288 #ifdef SUPPORT_VGA_SWITCHEROO
1289 /*
1290 * Check of disabled HDMI controller by vga_switcheroo
1291 */
1292 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1293 {
1294 struct pci_dev *p;
1295
1296 /* check only discrete GPU */
1297 switch (pci->vendor) {
1298 case PCI_VENDOR_ID_ATI:
1299 case PCI_VENDOR_ID_AMD:
1300 case PCI_VENDOR_ID_NVIDIA:
1301 if (pci->devfn == 1) {
1302 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1303 pci->bus->number, 0);
1304 if (p) {
1305 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1306 return p;
1307 pci_dev_put(p);
1308 }
1309 }
1310 break;
1311 }
1312 return NULL;
1313 }
1314
1315 static bool check_hdmi_disabled(struct pci_dev *pci)
1316 {
1317 bool vga_inactive = false;
1318 struct pci_dev *p = get_bound_vga(pci);
1319
1320 if (p) {
1321 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1322 vga_inactive = true;
1323 pci_dev_put(p);
1324 }
1325 return vga_inactive;
1326 }
1327 #endif /* SUPPORT_VGA_SWITCHEROO */
1328
1329 /*
1330 * white/black-listing for position_fix
1331 */
1332 static struct snd_pci_quirk position_fix_list[] = {
1333 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1334 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1335 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1336 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1337 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1338 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1339 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1340 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1341 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1342 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1343 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1344 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1345 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1346 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1347 {}
1348 };
1349
1350 static int check_position_fix(struct azx *chip, int fix)
1351 {
1352 const struct snd_pci_quirk *q;
1353
1354 switch (fix) {
1355 case POS_FIX_AUTO:
1356 case POS_FIX_LPIB:
1357 case POS_FIX_POSBUF:
1358 case POS_FIX_VIACOMBO:
1359 case POS_FIX_COMBO:
1360 return fix;
1361 }
1362
1363 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1364 if (q) {
1365 dev_info(chip->card->dev,
1366 "position_fix set to %d for device %04x:%04x\n",
1367 q->value, q->subvendor, q->subdevice);
1368 return q->value;
1369 }
1370
1371 /* Check VIA/ATI HD Audio Controller exist */
1372 if (chip->driver_type == AZX_DRIVER_VIA) {
1373 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1374 return POS_FIX_VIACOMBO;
1375 }
1376 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1377 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1378 return POS_FIX_LPIB;
1379 }
1380 return POS_FIX_AUTO;
1381 }
1382
1383 static void assign_position_fix(struct azx *chip, int fix)
1384 {
1385 static azx_get_pos_callback_t callbacks[] = {
1386 [POS_FIX_AUTO] = NULL,
1387 [POS_FIX_LPIB] = azx_get_pos_lpib,
1388 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1389 [POS_FIX_VIACOMBO] = azx_via_get_position,
1390 [POS_FIX_COMBO] = azx_get_pos_lpib,
1391 };
1392
1393 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1394
1395 /* combo mode uses LPIB only for playback */
1396 if (fix == POS_FIX_COMBO)
1397 chip->get_position[1] = NULL;
1398
1399 if (fix == POS_FIX_POSBUF &&
1400 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1401 chip->get_delay[0] = chip->get_delay[1] =
1402 azx_get_delay_from_lpib;
1403 }
1404
1405 }
1406
1407 /*
1408 * black-lists for probe_mask
1409 */
1410 static struct snd_pci_quirk probe_mask_list[] = {
1411 /* Thinkpad often breaks the controller communication when accessing
1412 * to the non-working (or non-existing) modem codec slot.
1413 */
1414 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1415 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1416 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1417 /* broken BIOS */
1418 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1419 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1420 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1421 /* forced codec slots */
1422 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1423 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1424 /* WinFast VP200 H (Teradici) user reported broken communication */
1425 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1426 {}
1427 };
1428
1429 #define AZX_FORCE_CODEC_MASK 0x100
1430
1431 static void check_probe_mask(struct azx *chip, int dev)
1432 {
1433 const struct snd_pci_quirk *q;
1434
1435 chip->codec_probe_mask = probe_mask[dev];
1436 if (chip->codec_probe_mask == -1) {
1437 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1438 if (q) {
1439 dev_info(chip->card->dev,
1440 "probe_mask set to 0x%x for device %04x:%04x\n",
1441 q->value, q->subvendor, q->subdevice);
1442 chip->codec_probe_mask = q->value;
1443 }
1444 }
1445
1446 /* check forced option */
1447 if (chip->codec_probe_mask != -1 &&
1448 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1449 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1450 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1451 (int)azx_bus(chip)->codec_mask);
1452 }
1453 }
1454
1455 /*
1456 * white/black-list for enable_msi
1457 */
1458 static struct snd_pci_quirk msi_black_list[] = {
1459 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1460 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1461 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1462 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1463 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1464 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1465 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1466 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1467 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1468 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1469 {}
1470 };
1471
1472 static void check_msi(struct azx *chip)
1473 {
1474 const struct snd_pci_quirk *q;
1475
1476 if (enable_msi >= 0) {
1477 chip->msi = !!enable_msi;
1478 return;
1479 }
1480 chip->msi = 1; /* enable MSI as default */
1481 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1482 if (q) {
1483 dev_info(chip->card->dev,
1484 "msi for device %04x:%04x set to %d\n",
1485 q->subvendor, q->subdevice, q->value);
1486 chip->msi = q->value;
1487 return;
1488 }
1489
1490 /* NVidia chipsets seem to cause troubles with MSI */
1491 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1492 dev_info(chip->card->dev, "Disabling MSI\n");
1493 chip->msi = 0;
1494 }
1495 }
1496
1497 /* check the snoop mode availability */
1498 static void azx_check_snoop_available(struct azx *chip)
1499 {
1500 int snoop = hda_snoop;
1501
1502 if (snoop >= 0) {
1503 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1504 snoop ? "snoop" : "non-snoop");
1505 chip->snoop = snoop;
1506 chip->uc_buffer = !snoop;
1507 return;
1508 }
1509
1510 snoop = true;
1511 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1512 chip->driver_type == AZX_DRIVER_VIA) {
1513 /* force to non-snoop mode for a new VIA controller
1514 * when BIOS is set
1515 */
1516 u8 val;
1517 pci_read_config_byte(chip->pci, 0x42, &val);
1518 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1519 chip->pci->revision == 0x20))
1520 snoop = false;
1521 }
1522
1523 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1524 snoop = false;
1525
1526 chip->snoop = snoop;
1527 if (!snoop) {
1528 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1529 /* C-Media requires non-cached pages only for CORB/RIRB */
1530 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1531 chip->uc_buffer = true;
1532 }
1533 }
1534
1535 static void azx_probe_work(struct work_struct *work)
1536 {
1537 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1538 azx_probe_continue(&hda->chip);
1539 }
1540
1541 static int default_bdl_pos_adj(struct azx *chip)
1542 {
1543 /* some exceptions: Atoms seem problematic with value 1 */
1544 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1545 switch (chip->pci->device) {
1546 case 0x0f04: /* Baytrail */
1547 case 0x2284: /* Braswell */
1548 return 32;
1549 }
1550 }
1551
1552 switch (chip->driver_type) {
1553 case AZX_DRIVER_ICH:
1554 case AZX_DRIVER_PCH:
1555 return 1;
1556 default:
1557 return 32;
1558 }
1559 }
1560
1561 /*
1562 * constructor
1563 */
1564 static const struct hdac_io_ops pci_hda_io_ops;
1565 static const struct hda_controller_ops pci_hda_ops;
1566
1567 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1568 int dev, unsigned int driver_caps,
1569 struct azx **rchip)
1570 {
1571 static struct snd_device_ops ops = {
1572 .dev_disconnect = azx_dev_disconnect,
1573 .dev_free = azx_dev_free,
1574 };
1575 struct hda_intel *hda;
1576 struct azx *chip;
1577 int err;
1578
1579 *rchip = NULL;
1580
1581 err = pci_enable_device(pci);
1582 if (err < 0)
1583 return err;
1584
1585 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1586 if (!hda) {
1587 pci_disable_device(pci);
1588 return -ENOMEM;
1589 }
1590
1591 chip = &hda->chip;
1592 mutex_init(&chip->open_mutex);
1593 chip->card = card;
1594 chip->pci = pci;
1595 chip->ops = &pci_hda_ops;
1596 chip->driver_caps = driver_caps;
1597 chip->driver_type = driver_caps & 0xff;
1598 check_msi(chip);
1599 chip->dev_index = dev;
1600 chip->jackpoll_ms = jackpoll_ms;
1601 INIT_LIST_HEAD(&chip->pcm_list);
1602 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1603 INIT_LIST_HEAD(&hda->list);
1604 init_vga_switcheroo(chip);
1605 init_completion(&hda->probe_wait);
1606
1607 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1608
1609 check_probe_mask(chip, dev);
1610
1611 chip->single_cmd = single_cmd;
1612 azx_check_snoop_available(chip);
1613
1614 if (bdl_pos_adj[dev] < 0)
1615 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1616 else
1617 chip->bdl_pos_adj = bdl_pos_adj[dev];
1618
1619 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1620 if (err < 0) {
1621 kfree(hda);
1622 pci_disable_device(pci);
1623 return err;
1624 }
1625
1626 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1627 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1628 chip->bus.needs_damn_long_delay = 1;
1629 }
1630
1631 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1632 if (err < 0) {
1633 dev_err(card->dev, "Error creating device [card]!\n");
1634 azx_free(chip);
1635 return err;
1636 }
1637
1638 /* continue probing in work context as may trigger request module */
1639 INIT_WORK(&hda->probe_work, azx_probe_work);
1640
1641 *rchip = chip;
1642
1643 return 0;
1644 }
1645
1646 static int azx_first_init(struct azx *chip)
1647 {
1648 int dev = chip->dev_index;
1649 struct pci_dev *pci = chip->pci;
1650 struct snd_card *card = chip->card;
1651 struct hdac_bus *bus = azx_bus(chip);
1652 int err;
1653 unsigned short gcap;
1654 unsigned int dma_bits = 64;
1655
1656 #if BITS_PER_LONG != 64
1657 /* Fix up base address on ULI M5461 */
1658 if (chip->driver_type == AZX_DRIVER_ULI) {
1659 u16 tmp3;
1660 pci_read_config_word(pci, 0x40, &tmp3);
1661 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1662 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1663 }
1664 #endif
1665
1666 err = pci_request_regions(pci, "ICH HD audio");
1667 if (err < 0)
1668 return err;
1669 chip->region_requested = 1;
1670
1671 bus->addr = pci_resource_start(pci, 0);
1672 bus->remap_addr = pci_ioremap_bar(pci, 0);
1673 if (bus->remap_addr == NULL) {
1674 dev_err(card->dev, "ioremap error\n");
1675 return -ENXIO;
1676 }
1677
1678 if (IS_SKL_PLUS(pci))
1679 snd_hdac_bus_parse_capabilities(bus);
1680
1681 /*
1682 * Some Intel CPUs has always running timer (ART) feature and
1683 * controller may have Global time sync reporting capability, so
1684 * check both of these before declaring synchronized time reporting
1685 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1686 */
1687 chip->gts_present = false;
1688
1689 #ifdef CONFIG_X86
1690 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1691 chip->gts_present = true;
1692 #endif
1693
1694 if (chip->msi) {
1695 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1696 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1697 pci->no_64bit_msi = true;
1698 }
1699 if (pci_enable_msi(pci) < 0)
1700 chip->msi = 0;
1701 }
1702
1703 pci_set_master(pci);
1704 synchronize_irq(bus->irq);
1705
1706 gcap = azx_readw(chip, GCAP);
1707 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1708
1709 /* AMD devices support 40 or 48bit DMA, take the safe one */
1710 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1711 dma_bits = 40;
1712
1713 /* disable SB600 64bit support for safety */
1714 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1715 struct pci_dev *p_smbus;
1716 dma_bits = 40;
1717 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1718 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1719 NULL);
1720 if (p_smbus) {
1721 if (p_smbus->revision < 0x30)
1722 gcap &= ~AZX_GCAP_64OK;
1723 pci_dev_put(p_smbus);
1724 }
1725 }
1726
1727 /* NVidia hardware normally only supports up to 40 bits of DMA */
1728 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1729 dma_bits = 40;
1730
1731 /* disable 64bit DMA address on some devices */
1732 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1733 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1734 gcap &= ~AZX_GCAP_64OK;
1735 }
1736
1737 /* disable buffer size rounding to 128-byte multiples if supported */
1738 if (align_buffer_size >= 0)
1739 chip->align_buffer_size = !!align_buffer_size;
1740 else {
1741 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1742 chip->align_buffer_size = 0;
1743 else
1744 chip->align_buffer_size = 1;
1745 }
1746
1747 /* allow 64bit DMA address if supported by H/W */
1748 if (!(gcap & AZX_GCAP_64OK))
1749 dma_bits = 32;
1750 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1751 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1752 } else {
1753 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1754 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1755 }
1756
1757 /* read number of streams from GCAP register instead of using
1758 * hardcoded value
1759 */
1760 chip->capture_streams = (gcap >> 8) & 0x0f;
1761 chip->playback_streams = (gcap >> 12) & 0x0f;
1762 if (!chip->playback_streams && !chip->capture_streams) {
1763 /* gcap didn't give any info, switching to old method */
1764
1765 switch (chip->driver_type) {
1766 case AZX_DRIVER_ULI:
1767 chip->playback_streams = ULI_NUM_PLAYBACK;
1768 chip->capture_streams = ULI_NUM_CAPTURE;
1769 break;
1770 case AZX_DRIVER_ATIHDMI:
1771 case AZX_DRIVER_ATIHDMI_NS:
1772 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1773 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1774 break;
1775 case AZX_DRIVER_GENERIC:
1776 default:
1777 chip->playback_streams = ICH6_NUM_PLAYBACK;
1778 chip->capture_streams = ICH6_NUM_CAPTURE;
1779 break;
1780 }
1781 }
1782 chip->capture_index_offset = 0;
1783 chip->playback_index_offset = chip->capture_streams;
1784 chip->num_streams = chip->playback_streams + chip->capture_streams;
1785
1786 /* initialize streams */
1787 err = azx_init_streams(chip);
1788 if (err < 0)
1789 return err;
1790
1791 err = azx_alloc_stream_pages(chip);
1792 if (err < 0)
1793 return err;
1794
1795 /* initialize chip */
1796 azx_init_pci(chip);
1797
1798 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1799 snd_hdac_i915_set_bclk(bus);
1800
1801 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1802
1803 /* codec detection */
1804 if (!azx_bus(chip)->codec_mask) {
1805 dev_err(card->dev, "no codecs found!\n");
1806 return -ENODEV;
1807 }
1808
1809 if (azx_acquire_irq(chip, 0) < 0)
1810 return -EBUSY;
1811
1812 strcpy(card->driver, "HDA-Intel");
1813 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1814 sizeof(card->shortname));
1815 snprintf(card->longname, sizeof(card->longname),
1816 "%s at 0x%lx irq %i",
1817 card->shortname, bus->addr, bus->irq);
1818
1819 return 0;
1820 }
1821
1822 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1823 /* callback from request_firmware_nowait() */
1824 static void azx_firmware_cb(const struct firmware *fw, void *context)
1825 {
1826 struct snd_card *card = context;
1827 struct azx *chip = card->private_data;
1828 struct pci_dev *pci = chip->pci;
1829
1830 if (!fw) {
1831 dev_err(card->dev, "Cannot load firmware, aborting\n");
1832 goto error;
1833 }
1834
1835 chip->fw = fw;
1836 if (!chip->disabled) {
1837 /* continue probing */
1838 if (azx_probe_continue(chip))
1839 goto error;
1840 }
1841 return; /* OK */
1842
1843 error:
1844 snd_card_free(card);
1845 pci_set_drvdata(pci, NULL);
1846 }
1847 #endif
1848
1849 /*
1850 * HDA controller ops.
1851 */
1852
1853 /* PCI register access. */
1854 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1855 {
1856 writel(value, addr);
1857 }
1858
1859 static u32 pci_azx_readl(u32 __iomem *addr)
1860 {
1861 return readl(addr);
1862 }
1863
1864 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1865 {
1866 writew(value, addr);
1867 }
1868
1869 static u16 pci_azx_readw(u16 __iomem *addr)
1870 {
1871 return readw(addr);
1872 }
1873
1874 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1875 {
1876 writeb(value, addr);
1877 }
1878
1879 static u8 pci_azx_readb(u8 __iomem *addr)
1880 {
1881 return readb(addr);
1882 }
1883
1884 static int disable_msi_reset_irq(struct azx *chip)
1885 {
1886 struct hdac_bus *bus = azx_bus(chip);
1887 int err;
1888
1889 free_irq(bus->irq, chip);
1890 bus->irq = -1;
1891 pci_disable_msi(chip->pci);
1892 chip->msi = 0;
1893 err = azx_acquire_irq(chip, 1);
1894 if (err < 0)
1895 return err;
1896
1897 return 0;
1898 }
1899
1900 /* DMA page allocation helpers. */
1901 static int dma_alloc_pages(struct hdac_bus *bus,
1902 int type,
1903 size_t size,
1904 struct snd_dma_buffer *buf)
1905 {
1906 struct azx *chip = bus_to_azx(bus);
1907 int err;
1908
1909 err = snd_dma_alloc_pages(type,
1910 bus->dev,
1911 size, buf);
1912 if (err < 0)
1913 return err;
1914 mark_pages_wc(chip, buf, true);
1915 return 0;
1916 }
1917
1918 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1919 {
1920 struct azx *chip = bus_to_azx(bus);
1921
1922 mark_pages_wc(chip, buf, false);
1923 snd_dma_free_pages(buf);
1924 }
1925
1926 static int substream_alloc_pages(struct azx *chip,
1927 struct snd_pcm_substream *substream,
1928 size_t size)
1929 {
1930 struct azx_dev *azx_dev = get_azx_dev(substream);
1931 int ret;
1932
1933 mark_runtime_wc(chip, azx_dev, substream, false);
1934 ret = snd_pcm_lib_malloc_pages(substream, size);
1935 if (ret < 0)
1936 return ret;
1937 mark_runtime_wc(chip, azx_dev, substream, true);
1938 return 0;
1939 }
1940
1941 static int substream_free_pages(struct azx *chip,
1942 struct snd_pcm_substream *substream)
1943 {
1944 struct azx_dev *azx_dev = get_azx_dev(substream);
1945 mark_runtime_wc(chip, azx_dev, substream, false);
1946 return snd_pcm_lib_free_pages(substream);
1947 }
1948
1949 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1950 struct vm_area_struct *area)
1951 {
1952 #ifdef CONFIG_X86
1953 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1954 struct azx *chip = apcm->chip;
1955 if (chip->uc_buffer)
1956 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1957 #endif
1958 }
1959
1960 static const struct hdac_io_ops pci_hda_io_ops = {
1961 .reg_writel = pci_azx_writel,
1962 .reg_readl = pci_azx_readl,
1963 .reg_writew = pci_azx_writew,
1964 .reg_readw = pci_azx_readw,
1965 .reg_writeb = pci_azx_writeb,
1966 .reg_readb = pci_azx_readb,
1967 .dma_alloc_pages = dma_alloc_pages,
1968 .dma_free_pages = dma_free_pages,
1969 };
1970
1971 static const struct hda_controller_ops pci_hda_ops = {
1972 .disable_msi_reset_irq = disable_msi_reset_irq,
1973 .substream_alloc_pages = substream_alloc_pages,
1974 .substream_free_pages = substream_free_pages,
1975 .pcm_mmap_prepare = pcm_mmap_prepare,
1976 .position_check = azx_position_check,
1977 .link_power = azx_intel_link_power,
1978 };
1979
1980 static int azx_probe(struct pci_dev *pci,
1981 const struct pci_device_id *pci_id)
1982 {
1983 static int dev;
1984 struct snd_card *card;
1985 struct hda_intel *hda;
1986 struct azx *chip;
1987 bool schedule_probe;
1988 int err;
1989
1990 if (dev >= SNDRV_CARDS)
1991 return -ENODEV;
1992 if (!enable[dev]) {
1993 dev++;
1994 return -ENOENT;
1995 }
1996
1997 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1998 0, &card);
1999 if (err < 0) {
2000 dev_err(&pci->dev, "Error creating card!\n");
2001 return err;
2002 }
2003
2004 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2005 if (err < 0)
2006 goto out_free;
2007 card->private_data = chip;
2008 hda = container_of(chip, struct hda_intel, chip);
2009
2010 pci_set_drvdata(pci, card);
2011
2012 err = register_vga_switcheroo(chip);
2013 if (err < 0) {
2014 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2015 goto out_free;
2016 }
2017
2018 if (check_hdmi_disabled(pci)) {
2019 dev_info(card->dev, "VGA controller is disabled\n");
2020 dev_info(card->dev, "Delaying initialization\n");
2021 chip->disabled = true;
2022 }
2023
2024 schedule_probe = !chip->disabled;
2025
2026 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2027 if (patch[dev] && *patch[dev]) {
2028 dev_info(card->dev, "Applying patch firmware '%s'\n",
2029 patch[dev]);
2030 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2031 &pci->dev, GFP_KERNEL, card,
2032 azx_firmware_cb);
2033 if (err < 0)
2034 goto out_free;
2035 schedule_probe = false; /* continued in azx_firmware_cb() */
2036 }
2037 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2038
2039 #ifndef CONFIG_SND_HDA_I915
2040 if (CONTROLLER_IN_GPU(pci))
2041 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2042 #endif
2043
2044 if (schedule_probe)
2045 schedule_work(&hda->probe_work);
2046
2047 dev++;
2048 if (chip->disabled)
2049 complete_all(&hda->probe_wait);
2050 return 0;
2051
2052 out_free:
2053 snd_card_free(card);
2054 return err;
2055 }
2056
2057 #ifdef CONFIG_PM
2058 /* On some boards setting power_save to a non 0 value leads to clicking /
2059 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2060 * figure out how to avoid these sounds, but that is not always feasible.
2061 * So we keep a list of devices where we disable powersaving as its known
2062 * to causes problems on these devices.
2063 */
2064 static struct snd_pci_quirk power_save_blacklist[] = {
2065 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2066 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2067 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2068 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2069 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2070 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2071 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2072 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2073 {}
2074 };
2075 #endif /* CONFIG_PM */
2076
2077 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2078 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2079 [AZX_DRIVER_NVIDIA] = 8,
2080 [AZX_DRIVER_TERA] = 1,
2081 };
2082
2083 static int azx_probe_continue(struct azx *chip)
2084 {
2085 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2086 struct hdac_bus *bus = azx_bus(chip);
2087 struct pci_dev *pci = chip->pci;
2088 int dev = chip->dev_index;
2089 int val;
2090 int err;
2091
2092 to_hda_bus(bus)->bus_probing = 1;
2093 hda->probe_continued = 1;
2094
2095 /* Request display power well for the HDA controller or codec. For
2096 * Haswell/Broadwell, both the display HDA controller and codec need
2097 * this power. For other platforms, like Baytrail/Braswell, only the
2098 * display codec needs the power and it can be released after probe.
2099 */
2100 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2101 /* HSW/BDW controllers need this power */
2102 if (CONTROLLER_IN_GPU(pci))
2103 hda->need_i915_power = 1;
2104
2105 err = snd_hdac_i915_init(bus);
2106 if (err < 0) {
2107 /* if the controller is bound only with HDMI/DP
2108 * (for HSW and BDW), we need to abort the probe;
2109 * for other chips, still continue probing as other
2110 * codecs can be on the same link.
2111 */
2112 if (CONTROLLER_IN_GPU(pci)) {
2113 dev_err(chip->card->dev,
2114 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2115 goto out_free;
2116 } else
2117 goto skip_i915;
2118 }
2119
2120 err = snd_hdac_display_power(bus, true);
2121 if (err < 0) {
2122 dev_err(chip->card->dev,
2123 "Cannot turn on display power on i915\n");
2124 goto i915_power_fail;
2125 }
2126 }
2127
2128 skip_i915:
2129 err = azx_first_init(chip);
2130 if (err < 0)
2131 goto out_free;
2132
2133 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2134 chip->beep_mode = beep_mode[dev];
2135 #endif
2136
2137 /* create codec instances */
2138 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2139 if (err < 0)
2140 goto out_free;
2141
2142 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2143 if (chip->fw) {
2144 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2145 chip->fw->data);
2146 if (err < 0)
2147 goto out_free;
2148 #ifndef CONFIG_PM
2149 release_firmware(chip->fw); /* no longer needed */
2150 chip->fw = NULL;
2151 #endif
2152 }
2153 #endif
2154 if ((probe_only[dev] & 1) == 0) {
2155 err = azx_codec_configure(chip);
2156 if (err < 0)
2157 goto out_free;
2158 }
2159
2160 err = snd_card_register(chip->card);
2161 if (err < 0)
2162 goto out_free;
2163
2164 chip->running = 1;
2165 azx_add_card_list(chip);
2166
2167 val = power_save;
2168 #ifdef CONFIG_PM
2169 if (pm_blacklist) {
2170 const struct snd_pci_quirk *q;
2171
2172 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2173 if (q && val) {
2174 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2175 q->subvendor, q->subdevice);
2176 val = 0;
2177 }
2178 }
2179 #endif /* CONFIG_PM */
2180 snd_hda_set_power_save(&chip->bus, val * 1000);
2181 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2182 pm_runtime_put_autosuspend(&pci->dev);
2183
2184 out_free:
2185 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2186 && !hda->need_i915_power)
2187 snd_hdac_display_power(bus, false);
2188
2189 i915_power_fail:
2190 if (err < 0)
2191 hda->init_failed = 1;
2192 complete_all(&hda->probe_wait);
2193 to_hda_bus(bus)->bus_probing = 0;
2194 return err;
2195 }
2196
2197 static void azx_remove(struct pci_dev *pci)
2198 {
2199 struct snd_card *card = pci_get_drvdata(pci);
2200 struct azx *chip;
2201 struct hda_intel *hda;
2202
2203 if (card) {
2204 /* cancel the pending probing work */
2205 chip = card->private_data;
2206 hda = container_of(chip, struct hda_intel, chip);
2207 /* FIXME: below is an ugly workaround.
2208 * Both device_release_driver() and driver_probe_device()
2209 * take *both* the device's and its parent's lock before
2210 * calling the remove() and probe() callbacks. The codec
2211 * probe takes the locks of both the codec itself and its
2212 * parent, i.e. the PCI controller dev. Meanwhile, when
2213 * the PCI controller is unbound, it takes its lock, too
2214 * ==> ouch, a deadlock!
2215 * As a workaround, we unlock temporarily here the controller
2216 * device during cancel_work_sync() call.
2217 */
2218 device_unlock(&pci->dev);
2219 cancel_work_sync(&hda->probe_work);
2220 device_lock(&pci->dev);
2221
2222 snd_card_free(card);
2223 }
2224 }
2225
2226 static void azx_shutdown(struct pci_dev *pci)
2227 {
2228 struct snd_card *card = pci_get_drvdata(pci);
2229 struct azx *chip;
2230
2231 if (!card)
2232 return;
2233 chip = card->private_data;
2234 if (chip && chip->running)
2235 azx_stop_chip(chip);
2236 }
2237
2238 /* PCI IDs */
2239 static const struct pci_device_id azx_ids[] = {
2240 /* CPT */
2241 { PCI_DEVICE(0x8086, 0x1c20),
2242 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2243 /* PBG */
2244 { PCI_DEVICE(0x8086, 0x1d20),
2245 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2246 /* Panther Point */
2247 { PCI_DEVICE(0x8086, 0x1e20),
2248 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2249 /* Lynx Point */
2250 { PCI_DEVICE(0x8086, 0x8c20),
2251 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2252 /* 9 Series */
2253 { PCI_DEVICE(0x8086, 0x8ca0),
2254 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2255 /* Wellsburg */
2256 { PCI_DEVICE(0x8086, 0x8d20),
2257 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2258 { PCI_DEVICE(0x8086, 0x8d21),
2259 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2260 /* Lewisburg */
2261 { PCI_DEVICE(0x8086, 0xa1f0),
2262 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2263 { PCI_DEVICE(0x8086, 0xa270),
2264 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2265 /* Lynx Point-LP */
2266 { PCI_DEVICE(0x8086, 0x9c20),
2267 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2268 /* Lynx Point-LP */
2269 { PCI_DEVICE(0x8086, 0x9c21),
2270 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2271 /* Wildcat Point-LP */
2272 { PCI_DEVICE(0x8086, 0x9ca0),
2273 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2274 /* Sunrise Point */
2275 { PCI_DEVICE(0x8086, 0xa170),
2276 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2277 /* Sunrise Point-LP */
2278 { PCI_DEVICE(0x8086, 0x9d70),
2279 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2280 /* Kabylake */
2281 { PCI_DEVICE(0x8086, 0xa171),
2282 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2283 /* Kabylake-LP */
2284 { PCI_DEVICE(0x8086, 0x9d71),
2285 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2286 /* Kabylake-H */
2287 { PCI_DEVICE(0x8086, 0xa2f0),
2288 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2289 /* Broxton-P(Apollolake) */
2290 { PCI_DEVICE(0x8086, 0x5a98),
2291 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2292 /* Broxton-T */
2293 { PCI_DEVICE(0x8086, 0x1a98),
2294 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2295 /* Haswell */
2296 { PCI_DEVICE(0x8086, 0x0a0c),
2297 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2298 { PCI_DEVICE(0x8086, 0x0c0c),
2299 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2300 { PCI_DEVICE(0x8086, 0x0d0c),
2301 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2302 /* Broadwell */
2303 { PCI_DEVICE(0x8086, 0x160c),
2304 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2305 /* 5 Series/3400 */
2306 { PCI_DEVICE(0x8086, 0x3b56),
2307 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2308 /* Poulsbo */
2309 { PCI_DEVICE(0x8086, 0x811b),
2310 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2311 /* Oaktrail */
2312 { PCI_DEVICE(0x8086, 0x080a),
2313 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2314 /* BayTrail */
2315 { PCI_DEVICE(0x8086, 0x0f04),
2316 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2317 /* Braswell */
2318 { PCI_DEVICE(0x8086, 0x2284),
2319 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2320 /* ICH6 */
2321 { PCI_DEVICE(0x8086, 0x2668),
2322 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2323 /* ICH7 */
2324 { PCI_DEVICE(0x8086, 0x27d8),
2325 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2326 /* ESB2 */
2327 { PCI_DEVICE(0x8086, 0x269a),
2328 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2329 /* ICH8 */
2330 { PCI_DEVICE(0x8086, 0x284b),
2331 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2332 /* ICH9 */
2333 { PCI_DEVICE(0x8086, 0x293e),
2334 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2335 /* ICH9 */
2336 { PCI_DEVICE(0x8086, 0x293f),
2337 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2338 /* ICH10 */
2339 { PCI_DEVICE(0x8086, 0x3a3e),
2340 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2341 /* ICH10 */
2342 { PCI_DEVICE(0x8086, 0x3a6e),
2343 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2344 /* Generic Intel */
2345 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2346 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2347 .class_mask = 0xffffff,
2348 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2349 /* ATI SB 450/600/700/800/900 */
2350 { PCI_DEVICE(0x1002, 0x437b),
2351 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2352 { PCI_DEVICE(0x1002, 0x4383),
2353 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2354 /* AMD Hudson */
2355 { PCI_DEVICE(0x1022, 0x780d),
2356 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2357 /* AMD Stoney */
2358 { PCI_DEVICE(0x1022, 0x157a),
2359 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2360 AZX_DCAPS_PM_RUNTIME },
2361 /* AMD Raven */
2362 { PCI_DEVICE(0x1022, 0x15e3),
2363 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2364 AZX_DCAPS_PM_RUNTIME },
2365 /* ATI HDMI */
2366 { PCI_DEVICE(0x1002, 0x0002),
2367 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2368 { PCI_DEVICE(0x1002, 0x1308),
2369 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2370 { PCI_DEVICE(0x1002, 0x157a),
2371 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2372 { PCI_DEVICE(0x1002, 0x15b3),
2373 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2374 { PCI_DEVICE(0x1002, 0x793b),
2375 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2376 { PCI_DEVICE(0x1002, 0x7919),
2377 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2378 { PCI_DEVICE(0x1002, 0x960f),
2379 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2380 { PCI_DEVICE(0x1002, 0x970f),
2381 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2382 { PCI_DEVICE(0x1002, 0x9840),
2383 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2384 { PCI_DEVICE(0x1002, 0xaa00),
2385 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2386 { PCI_DEVICE(0x1002, 0xaa08),
2387 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2388 { PCI_DEVICE(0x1002, 0xaa10),
2389 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2390 { PCI_DEVICE(0x1002, 0xaa18),
2391 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2392 { PCI_DEVICE(0x1002, 0xaa20),
2393 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2394 { PCI_DEVICE(0x1002, 0xaa28),
2395 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2396 { PCI_DEVICE(0x1002, 0xaa30),
2397 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2398 { PCI_DEVICE(0x1002, 0xaa38),
2399 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2400 { PCI_DEVICE(0x1002, 0xaa40),
2401 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2402 { PCI_DEVICE(0x1002, 0xaa48),
2403 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2404 { PCI_DEVICE(0x1002, 0xaa50),
2405 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2406 { PCI_DEVICE(0x1002, 0xaa58),
2407 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2408 { PCI_DEVICE(0x1002, 0xaa60),
2409 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2410 { PCI_DEVICE(0x1002, 0xaa68),
2411 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2412 { PCI_DEVICE(0x1002, 0xaa80),
2413 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2414 { PCI_DEVICE(0x1002, 0xaa88),
2415 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2416 { PCI_DEVICE(0x1002, 0xaa90),
2417 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2418 { PCI_DEVICE(0x1002, 0xaa98),
2419 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2420 { PCI_DEVICE(0x1002, 0x9902),
2421 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2422 { PCI_DEVICE(0x1002, 0xaaa0),
2423 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2424 { PCI_DEVICE(0x1002, 0xaaa8),
2425 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2426 { PCI_DEVICE(0x1002, 0xaab0),
2427 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2428 { PCI_DEVICE(0x1002, 0xaac0),
2429 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2430 { PCI_DEVICE(0x1002, 0xaac8),
2431 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2432 { PCI_DEVICE(0x1002, 0xaad8),
2433 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2434 { PCI_DEVICE(0x1002, 0xaae8),
2435 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2436 { PCI_DEVICE(0x1002, 0xaae0),
2437 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2438 { PCI_DEVICE(0x1002, 0xaaf0),
2439 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2440 /* VIA VT8251/VT8237A */
2441 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2442 /* VIA GFX VT7122/VX900 */
2443 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2444 /* VIA GFX VT6122/VX11 */
2445 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2446 /* SIS966 */
2447 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2448 /* ULI M5461 */
2449 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2450 /* NVIDIA MCP */
2451 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2452 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2453 .class_mask = 0xffffff,
2454 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2455 /* Teradici */
2456 { PCI_DEVICE(0x6549, 0x1200),
2457 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2458 { PCI_DEVICE(0x6549, 0x2200),
2459 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2460 /* Creative X-Fi (CA0110-IBG) */
2461 /* CTHDA chips */
2462 { PCI_DEVICE(0x1102, 0x0010),
2463 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2464 { PCI_DEVICE(0x1102, 0x0012),
2465 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2466 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2467 /* the following entry conflicts with snd-ctxfi driver,
2468 * as ctxfi driver mutates from HD-audio to native mode with
2469 * a special command sequence.
2470 */
2471 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2472 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2473 .class_mask = 0xffffff,
2474 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2475 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2476 #else
2477 /* this entry seems still valid -- i.e. without emu20kx chip */
2478 { PCI_DEVICE(0x1102, 0x0009),
2479 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2480 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2481 #endif
2482 /* CM8888 */
2483 { PCI_DEVICE(0x13f6, 0x5011),
2484 .driver_data = AZX_DRIVER_CMEDIA |
2485 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2486 /* Vortex86MX */
2487 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2488 /* VMware HDAudio */
2489 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2490 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2491 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2492 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2493 .class_mask = 0xffffff,
2494 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2495 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2496 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2497 .class_mask = 0xffffff,
2498 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2499 { 0, }
2500 };
2501 MODULE_DEVICE_TABLE(pci, azx_ids);
2502
2503 /* pci_driver definition */
2504 static struct pci_driver azx_driver = {
2505 .name = KBUILD_MODNAME,
2506 .id_table = azx_ids,
2507 .probe = azx_probe,
2508 .remove = azx_remove,
2509 .shutdown = azx_shutdown,
2510 .driver = {
2511 .pm = AZX_PM_OPS,
2512 },
2513 };
2514
2515 module_pci_driver(azx_driver);
Linux with added FPC-III support