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Revert "ALSA: hda: Flush interrupts on disabling"
[linux/fpc-iii.git] / sound / pci / hda / patch_ca0132.c
blob2809999612260767dc6da6398923f548e426945e
1 /*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <sound/core.h>
31 #include "hda_codec.h"
32 #include "hda_local.h"
33 #include "hda_auto_parser.h"
34 #include "hda_jack.h"
35
36 #include "ca0132_regs.h"
37
38 /* Enable this to see controls for tuning purpose. */
39 /*#define ENABLE_TUNING_CONTROLS*/
40
41 #ifdef ENABLE_TUNING_CONTROLS
42 #include <sound/tlv.h>
43 #endif
44
45 #define FLOAT_ZERO 0x00000000
46 #define FLOAT_ONE 0x3f800000
47 #define FLOAT_TWO 0x40000000
48 #define FLOAT_MINUS_5 0xc0a00000
49
50 #define UNSOL_TAG_DSP 0x16
51
52 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
53 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
54
55 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
56 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
57 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
58
59 #define MASTERCONTROL 0x80
60 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
61 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
62
63 #define WIDGET_CHIP_CTRL 0x15
64 #define WIDGET_DSP_CTRL 0x16
65
66 #define MEM_CONNID_MICIN1 3
67 #define MEM_CONNID_MICIN2 5
68 #define MEM_CONNID_MICOUT1 12
69 #define MEM_CONNID_MICOUT2 14
70 #define MEM_CONNID_WUH 10
71 #define MEM_CONNID_DSP 16
72 #define MEM_CONNID_DMIC 100
73
74 #define SCP_SET 0
75 #define SCP_GET 1
76
77 #define EFX_FILE "ctefx.bin"
78
79 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
80 MODULE_FIRMWARE(EFX_FILE);
81 #endif
82
83 static char *dirstr[2] = { "Playback", "Capture" };
84
85 enum {
86 SPEAKER_OUT,
87 HEADPHONE_OUT
88 };
89
90 enum {
91 DIGITAL_MIC,
92 LINE_MIC_IN
93 };
94
95 enum {
96 #define VNODE_START_NID 0x80
97 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
98 VNID_MIC,
99 VNID_HP_SEL,
100 VNID_AMIC1_SEL,
101 VNID_HP_ASEL,
102 VNID_AMIC1_ASEL,
103 VNODE_END_NID,
104 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
105
106 #define EFFECT_START_NID 0x90
107 #define OUT_EFFECT_START_NID EFFECT_START_NID
108 SURROUND = OUT_EFFECT_START_NID,
109 CRYSTALIZER,
110 DIALOG_PLUS,
111 SMART_VOLUME,
112 X_BASS,
113 EQUALIZER,
114 OUT_EFFECT_END_NID,
115 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
116
117 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
118 ECHO_CANCELLATION = IN_EFFECT_START_NID,
119 VOICE_FOCUS,
120 MIC_SVM,
121 NOISE_REDUCTION,
122 IN_EFFECT_END_NID,
123 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
124
125 VOICEFX = IN_EFFECT_END_NID,
126 PLAY_ENHANCEMENT,
127 CRYSTAL_VOICE,
128 EFFECT_END_NID
129 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
130 };
131
132 /* Effects values size*/
133 #define EFFECT_VALS_MAX_COUNT 12
134
135 /* Latency introduced by DSP blocks in milliseconds. */
136 #define DSP_CAPTURE_INIT_LATENCY 0
137 #define DSP_CRYSTAL_VOICE_LATENCY 124
138 #define DSP_PLAYBACK_INIT_LATENCY 13
139 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
140 #define DSP_SPEAKER_OUT_LATENCY 7
141
142 struct ct_effect {
143 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
144 hda_nid_t nid;
145 int mid; /*effect module ID*/
146 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
147 int direct; /* 0:output; 1:input*/
148 int params; /* number of default non-on/off params */
149 /*effect default values, 1st is on/off. */
150 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
151 };
152
153 #define EFX_DIR_OUT 0
154 #define EFX_DIR_IN 1
155
156 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
157 { .name = "Surround",
158 .nid = SURROUND,
159 .mid = 0x96,
160 .reqs = {0, 1},
161 .direct = EFX_DIR_OUT,
162 .params = 1,
163 .def_vals = {0x3F800000, 0x3F2B851F}
164 },
165 { .name = "Crystalizer",
166 .nid = CRYSTALIZER,
167 .mid = 0x96,
168 .reqs = {7, 8},
169 .direct = EFX_DIR_OUT,
170 .params = 1,
171 .def_vals = {0x3F800000, 0x3F266666}
172 },
173 { .name = "Dialog Plus",
174 .nid = DIALOG_PLUS,
175 .mid = 0x96,
176 .reqs = {2, 3},
177 .direct = EFX_DIR_OUT,
178 .params = 1,
179 .def_vals = {0x00000000, 0x3F000000}
180 },
181 { .name = "Smart Volume",
182 .nid = SMART_VOLUME,
183 .mid = 0x96,
184 .reqs = {4, 5, 6},
185 .direct = EFX_DIR_OUT,
186 .params = 2,
187 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
188 },
189 { .name = "X-Bass",
190 .nid = X_BASS,
191 .mid = 0x96,
192 .reqs = {24, 23, 25},
193 .direct = EFX_DIR_OUT,
194 .params = 2,
195 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
196 },
197 { .name = "Equalizer",
198 .nid = EQUALIZER,
199 .mid = 0x96,
200 .reqs = {9, 10, 11, 12, 13, 14,
201 15, 16, 17, 18, 19, 20},
202 .direct = EFX_DIR_OUT,
203 .params = 11,
204 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
205 0x00000000, 0x00000000, 0x00000000, 0x00000000,
206 0x00000000, 0x00000000, 0x00000000, 0x00000000}
207 },
208 { .name = "Echo Cancellation",
209 .nid = ECHO_CANCELLATION,
210 .mid = 0x95,
211 .reqs = {0, 1, 2, 3},
212 .direct = EFX_DIR_IN,
213 .params = 3,
214 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
215 },
216 { .name = "Voice Focus",
217 .nid = VOICE_FOCUS,
218 .mid = 0x95,
219 .reqs = {6, 7, 8, 9},
220 .direct = EFX_DIR_IN,
221 .params = 3,
222 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
223 },
224 { .name = "Mic SVM",
225 .nid = MIC_SVM,
226 .mid = 0x95,
227 .reqs = {44, 45},
228 .direct = EFX_DIR_IN,
229 .params = 1,
230 .def_vals = {0x00000000, 0x3F3D70A4}
231 },
232 { .name = "Noise Reduction",
233 .nid = NOISE_REDUCTION,
234 .mid = 0x95,
235 .reqs = {4, 5},
236 .direct = EFX_DIR_IN,
237 .params = 1,
238 .def_vals = {0x3F800000, 0x3F000000}
239 },
240 { .name = "VoiceFX",
241 .nid = VOICEFX,
242 .mid = 0x95,
243 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
244 .direct = EFX_DIR_IN,
245 .params = 8,
246 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
247 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
248 0x00000000}
249 }
250 };
251
252 /* Tuning controls */
253 #ifdef ENABLE_TUNING_CONTROLS
254
255 enum {
256 #define TUNING_CTL_START_NID 0xC0
257 WEDGE_ANGLE = TUNING_CTL_START_NID,
258 SVM_LEVEL,
259 EQUALIZER_BAND_0,
260 EQUALIZER_BAND_1,
261 EQUALIZER_BAND_2,
262 EQUALIZER_BAND_3,
263 EQUALIZER_BAND_4,
264 EQUALIZER_BAND_5,
265 EQUALIZER_BAND_6,
266 EQUALIZER_BAND_7,
267 EQUALIZER_BAND_8,
268 EQUALIZER_BAND_9,
269 TUNING_CTL_END_NID
270 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
271 };
272
273 struct ct_tuning_ctl {
274 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
275 hda_nid_t parent_nid;
276 hda_nid_t nid;
277 int mid; /*effect module ID*/
278 int req; /*effect module request*/
279 int direct; /* 0:output; 1:input*/
280 unsigned int def_val;/*effect default values*/
281 };
282
283 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
284 { .name = "Wedge Angle",
285 .parent_nid = VOICE_FOCUS,
286 .nid = WEDGE_ANGLE,
287 .mid = 0x95,
288 .req = 8,
289 .direct = EFX_DIR_IN,
290 .def_val = 0x41F00000
291 },
292 { .name = "SVM Level",
293 .parent_nid = MIC_SVM,
294 .nid = SVM_LEVEL,
295 .mid = 0x95,
296 .req = 45,
297 .direct = EFX_DIR_IN,
298 .def_val = 0x3F3D70A4
299 },
300 { .name = "EQ Band0",
301 .parent_nid = EQUALIZER,
302 .nid = EQUALIZER_BAND_0,
303 .mid = 0x96,
304 .req = 11,
305 .direct = EFX_DIR_OUT,
306 .def_val = 0x00000000
307 },
308 { .name = "EQ Band1",
309 .parent_nid = EQUALIZER,
310 .nid = EQUALIZER_BAND_1,
311 .mid = 0x96,
312 .req = 12,
313 .direct = EFX_DIR_OUT,
314 .def_val = 0x00000000
315 },
316 { .name = "EQ Band2",
317 .parent_nid = EQUALIZER,
318 .nid = EQUALIZER_BAND_2,
319 .mid = 0x96,
320 .req = 13,
321 .direct = EFX_DIR_OUT,
322 .def_val = 0x00000000
323 },
324 { .name = "EQ Band3",
325 .parent_nid = EQUALIZER,
326 .nid = EQUALIZER_BAND_3,
327 .mid = 0x96,
328 .req = 14,
329 .direct = EFX_DIR_OUT,
330 .def_val = 0x00000000
331 },
332 { .name = "EQ Band4",
333 .parent_nid = EQUALIZER,
334 .nid = EQUALIZER_BAND_4,
335 .mid = 0x96,
336 .req = 15,
337 .direct = EFX_DIR_OUT,
338 .def_val = 0x00000000
339 },
340 { .name = "EQ Band5",
341 .parent_nid = EQUALIZER,
342 .nid = EQUALIZER_BAND_5,
343 .mid = 0x96,
344 .req = 16,
345 .direct = EFX_DIR_OUT,
346 .def_val = 0x00000000
347 },
348 { .name = "EQ Band6",
349 .parent_nid = EQUALIZER,
350 .nid = EQUALIZER_BAND_6,
351 .mid = 0x96,
352 .req = 17,
353 .direct = EFX_DIR_OUT,
354 .def_val = 0x00000000
355 },
356 { .name = "EQ Band7",
357 .parent_nid = EQUALIZER,
358 .nid = EQUALIZER_BAND_7,
359 .mid = 0x96,
360 .req = 18,
361 .direct = EFX_DIR_OUT,
362 .def_val = 0x00000000
363 },
364 { .name = "EQ Band8",
365 .parent_nid = EQUALIZER,
366 .nid = EQUALIZER_BAND_8,
367 .mid = 0x96,
368 .req = 19,
369 .direct = EFX_DIR_OUT,
370 .def_val = 0x00000000
371 },
372 { .name = "EQ Band9",
373 .parent_nid = EQUALIZER,
374 .nid = EQUALIZER_BAND_9,
375 .mid = 0x96,
376 .req = 20,
377 .direct = EFX_DIR_OUT,
378 .def_val = 0x00000000
379 }
380 };
381 #endif
382
383 /* Voice FX Presets */
384 #define VOICEFX_MAX_PARAM_COUNT 9
385
386 struct ct_voicefx {
387 char *name;
388 hda_nid_t nid;
389 int mid;
390 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
391 };
392
393 struct ct_voicefx_preset {
394 char *name; /*preset name*/
395 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
396 };
397
398 static struct ct_voicefx ca0132_voicefx = {
399 .name = "VoiceFX Capture Switch",
400 .nid = VOICEFX,
401 .mid = 0x95,
402 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
403 };
404
405 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
406 { .name = "Neutral",
407 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
408 0x44FA0000, 0x3F800000, 0x3F800000,
409 0x3F800000, 0x00000000, 0x00000000 }
410 },
411 { .name = "Female2Male",
412 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
413 0x44FA0000, 0x3F19999A, 0x3F866666,
414 0x3F800000, 0x00000000, 0x00000000 }
415 },
416 { .name = "Male2Female",
417 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
418 0x450AC000, 0x4017AE14, 0x3F6B851F,
419 0x3F800000, 0x00000000, 0x00000000 }
420 },
421 { .name = "ScrappyKid",
422 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
423 0x44FA0000, 0x40400000, 0x3F28F5C3,
424 0x3F800000, 0x00000000, 0x00000000 }
425 },
426 { .name = "Elderly",
427 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
428 0x44E10000, 0x3FB33333, 0x3FB9999A,
429 0x3F800000, 0x3E3A2E43, 0x00000000 }
430 },
431 { .name = "Orc",
432 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
433 0x45098000, 0x3F266666, 0x3FC00000,
434 0x3F800000, 0x00000000, 0x00000000 }
435 },
436 { .name = "Elf",
437 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
438 0x45193000, 0x3F8E147B, 0x3F75C28F,
439 0x3F800000, 0x00000000, 0x00000000 }
440 },
441 { .name = "Dwarf",
442 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
443 0x45007000, 0x3F451EB8, 0x3F7851EC,
444 0x3F800000, 0x00000000, 0x00000000 }
445 },
446 { .name = "AlienBrute",
447 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
448 0x451F6000, 0x3F266666, 0x3FA7D945,
449 0x3F800000, 0x3CF5C28F, 0x00000000 }
450 },
451 { .name = "Robot",
452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
453 0x44FA0000, 0x3FB2718B, 0x3F800000,
454 0xBC07010E, 0x00000000, 0x00000000 }
455 },
456 { .name = "Marine",
457 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
458 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
459 0x3F0A3D71, 0x00000000, 0x00000000 }
460 },
461 { .name = "Emo",
462 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
463 0x44FA0000, 0x3F800000, 0x3F800000,
464 0x3E4CCCCD, 0x00000000, 0x00000000 }
465 },
466 { .name = "DeepVoice",
467 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
468 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
469 0x3F800000, 0x00000000, 0x00000000 }
470 },
471 { .name = "Munchkin",
472 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
473 0x44FA0000, 0x3F800000, 0x3F1A043C,
474 0x3F800000, 0x00000000, 0x00000000 }
475 }
476 };
477
478 enum hda_cmd_vendor_io {
479 /* for DspIO node */
480 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
481 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
482
483 VENDOR_DSPIO_STATUS = 0xF01,
484 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
485 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
486 VENDOR_DSPIO_DSP_INIT = 0x703,
487 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
488 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
489
490 /* for ChipIO node */
491 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
492 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
493 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
494 VENDOR_CHIPIO_DATA_LOW = 0x300,
495 VENDOR_CHIPIO_DATA_HIGH = 0x400,
496
497 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
498 VENDOR_CHIPIO_STATUS = 0xF01,
499 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
500 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
501
502 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
503 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
504
505 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
506 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
507
508 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
509 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
510 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
511 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
512 VENDOR_CHIPIO_FLAG_SET = 0x70F,
513 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
514 VENDOR_CHIPIO_PARAM_SET = 0x710,
515 VENDOR_CHIPIO_PARAM_GET = 0xF10,
516
517 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
518 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
519 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
520 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
521
522 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
523 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
524 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
525 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
526
527 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
528 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
529 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
530 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
531 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
532 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
533
534 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
535 };
536
537 /*
538 * Control flag IDs
539 */
540 enum control_flag_id {
541 /* Connection manager stream setup is bypassed/enabled */
542 CONTROL_FLAG_C_MGR = 0,
543 /* DSP DMA is bypassed/enabled */
544 CONTROL_FLAG_DMA = 1,
545 /* 8051 'idle' mode is disabled/enabled */
546 CONTROL_FLAG_IDLE_ENABLE = 2,
547 /* Tracker for the SPDIF-in path is bypassed/enabled */
548 CONTROL_FLAG_TRACKER = 3,
549 /* DigitalOut to Spdif2Out connection is disabled/enabled */
550 CONTROL_FLAG_SPDIF2OUT = 4,
551 /* Digital Microphone is disabled/enabled */
552 CONTROL_FLAG_DMIC = 5,
553 /* ADC_B rate is 48 kHz/96 kHz */
554 CONTROL_FLAG_ADC_B_96KHZ = 6,
555 /* ADC_C rate is 48 kHz/96 kHz */
556 CONTROL_FLAG_ADC_C_96KHZ = 7,
557 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
558 CONTROL_FLAG_DAC_96KHZ = 8,
559 /* DSP rate is 48 kHz/96 kHz */
560 CONTROL_FLAG_DSP_96KHZ = 9,
561 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
562 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
563 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
564 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
565 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
566 CONTROL_FLAG_DECODE_LOOP = 12,
567 /* De-emphasis filter on DAC-1 disabled/enabled */
568 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
569 /* De-emphasis filter on DAC-2 disabled/enabled */
570 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
571 /* De-emphasis filter on DAC-3 disabled/enabled */
572 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
573 /* High-pass filter on ADC_B disabled/enabled */
574 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
575 /* High-pass filter on ADC_C disabled/enabled */
576 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
577 /* Common mode on Port_A disabled/enabled */
578 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
579 /* Common mode on Port_D disabled/enabled */
580 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
581 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
582 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
583 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
584 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
585 /* ASI rate is 48kHz/96kHz */
586 CONTROL_FLAG_ASI_96KHZ = 22,
587 /* DAC power settings able to control attached ports no/yes */
588 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
589 /* Clock Stop OK reporting is disabled/enabled */
590 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
591 /* Number of control flags */
592 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
593 };
594
595 /*
596 * Control parameter IDs
597 */
598 enum control_param_id {
599 /* 0: None, 1: Mic1In*/
600 CONTROL_PARAM_VIP_SOURCE = 1,
601 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
602 CONTROL_PARAM_SPDIF1_SOURCE = 2,
603 /* Port A output stage gain setting to use when 16 Ohm output
604 * impedance is selected*/
605 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
606 /* Port D output stage gain setting to use when 16 Ohm output
607 * impedance is selected*/
608 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
609
610 /* Stream Control */
611
612 /* Select stream with the given ID */
613 CONTROL_PARAM_STREAM_ID = 24,
614 /* Source connection point for the selected stream */
615 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
616 /* Destination connection point for the selected stream */
617 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
618 /* Number of audio channels in the selected stream */
619 CONTROL_PARAM_STREAMS_CHANNELS = 27,
620 /*Enable control for the selected stream */
621 CONTROL_PARAM_STREAM_CONTROL = 28,
622
623 /* Connection Point Control */
624
625 /* Select connection point with the given ID */
626 CONTROL_PARAM_CONN_POINT_ID = 29,
627 /* Connection point sample rate */
628 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
629
630 /* Node Control */
631
632 /* Select HDA node with the given ID */
633 CONTROL_PARAM_NODE_ID = 31
634 };
635
636 /*
637 * Dsp Io Status codes
638 */
639 enum hda_vendor_status_dspio {
640 /* Success */
641 VENDOR_STATUS_DSPIO_OK = 0x00,
642 /* Busy, unable to accept new command, the host must retry */
643 VENDOR_STATUS_DSPIO_BUSY = 0x01,
644 /* SCP command queue is full */
645 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
646 /* SCP response queue is empty */
647 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
648 };
649
650 /*
651 * Chip Io Status codes
652 */
653 enum hda_vendor_status_chipio {
654 /* Success */
655 VENDOR_STATUS_CHIPIO_OK = 0x00,
656 /* Busy, unable to accept new command, the host must retry */
657 VENDOR_STATUS_CHIPIO_BUSY = 0x01
658 };
659
660 /*
661 * CA0132 sample rate
662 */
663 enum ca0132_sample_rate {
664 SR_6_000 = 0x00,
665 SR_8_000 = 0x01,
666 SR_9_600 = 0x02,
667 SR_11_025 = 0x03,
668 SR_16_000 = 0x04,
669 SR_22_050 = 0x05,
670 SR_24_000 = 0x06,
671 SR_32_000 = 0x07,
672 SR_44_100 = 0x08,
673 SR_48_000 = 0x09,
674 SR_88_200 = 0x0A,
675 SR_96_000 = 0x0B,
676 SR_144_000 = 0x0C,
677 SR_176_400 = 0x0D,
678 SR_192_000 = 0x0E,
679 SR_384_000 = 0x0F,
680
681 SR_COUNT = 0x10,
682
683 SR_RATE_UNKNOWN = 0x1F
684 };
685
686 enum dsp_download_state {
687 DSP_DOWNLOAD_FAILED = -1,
688 DSP_DOWNLOAD_INIT = 0,
689 DSP_DOWNLOADING = 1,
690 DSP_DOWNLOADED = 2
691 };
692
693 /* retrieve parameters from hda format */
694 #define get_hdafmt_chs(fmt) (fmt & 0xf)
695 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
696 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
697 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
698
699 /*
700 * CA0132 specific
701 */
702
703 struct ca0132_spec {
704 struct snd_kcontrol_new *mixers[5];
705 unsigned int num_mixers;
706 const struct hda_verb *base_init_verbs;
707 const struct hda_verb *base_exit_verbs;
708 const struct hda_verb *chip_init_verbs;
709 struct hda_verb *spec_init_verbs;
710 struct auto_pin_cfg autocfg;
711
712 /* Nodes configurations */
713 struct hda_multi_out multiout;
714 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
715 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
716 unsigned int num_outputs;
717 hda_nid_t input_pins[AUTO_PIN_LAST];
718 hda_nid_t adcs[AUTO_PIN_LAST];
719 hda_nid_t dig_out;
720 hda_nid_t dig_in;
721 unsigned int num_inputs;
722 hda_nid_t shared_mic_nid;
723 hda_nid_t shared_out_nid;
724 hda_nid_t unsol_tag_hp;
725 hda_nid_t unsol_tag_amic1;
726
727 /* chip access */
728 struct mutex chipio_mutex; /* chip access mutex */
729 u32 curr_chip_addx;
730
731 /* DSP download related */
732 enum dsp_download_state dsp_state;
733 unsigned int dsp_stream_id;
734 unsigned int wait_scp;
735 unsigned int wait_scp_header;
736 unsigned int wait_num_data;
737 unsigned int scp_resp_header;
738 unsigned int scp_resp_data[4];
739 unsigned int scp_resp_count;
740
741 /* mixer and effects related */
742 unsigned char dmic_ctl;
743 int cur_out_type;
744 int cur_mic_type;
745 long vnode_lvol[VNODES_COUNT];
746 long vnode_rvol[VNODES_COUNT];
747 long vnode_lswitch[VNODES_COUNT];
748 long vnode_rswitch[VNODES_COUNT];
749 long effects_switch[EFFECTS_COUNT];
750 long voicefx_val;
751 long cur_mic_boost;
752
753 struct hda_codec *codec;
754 struct delayed_work unsol_hp_work;
755 int quirk;
756
757 #ifdef ENABLE_TUNING_CONTROLS
758 long cur_ctl_vals[TUNING_CTLS_COUNT];
759 #endif
760 };
761
762 /*
763 * CA0132 quirks table
764 */
765 enum {
766 QUIRK_NONE,
767 QUIRK_ALIENWARE,
768 };
769
770 static const struct hda_pintbl alienware_pincfgs[] = {
771 { 0x0b, 0x90170110 }, /* Builtin Speaker */
772 { 0x0c, 0x411111f0 }, /* N/A */
773 { 0x0d, 0x411111f0 }, /* N/A */
774 { 0x0e, 0x411111f0 }, /* N/A */
775 { 0x0f, 0x0321101f }, /* HP */
776 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
777 { 0x11, 0x03a11021 }, /* Mic */
778 { 0x12, 0xd5a30140 }, /* Builtin Mic */
779 { 0x13, 0x411111f0 }, /* N/A */
780 { 0x18, 0x411111f0 }, /* N/A */
781 {}
782 };
783
784 static const struct snd_pci_quirk ca0132_quirks[] = {
785 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
786 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
787 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
788 {}
789 };
790
791 /*
792 * CA0132 codec access
793 */
794 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
795 unsigned int verb, unsigned int parm, unsigned int *res)
796 {
797 unsigned int response;
798 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
799 *res = response;
800
801 return ((response == -1) ? -1 : 0);
802 }
803
804 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
805 unsigned short converter_format, unsigned int *res)
806 {
807 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
808 converter_format & 0xffff, res);
809 }
810
811 static int codec_set_converter_stream_channel(struct hda_codec *codec,
812 hda_nid_t nid, unsigned char stream,
813 unsigned char channel, unsigned int *res)
814 {
815 unsigned char converter_stream_channel = 0;
816
817 converter_stream_channel = (stream << 4) | (channel & 0x0f);
818 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
819 converter_stream_channel, res);
820 }
821
822 /* Chip access helper function */
823 static int chipio_send(struct hda_codec *codec,
824 unsigned int reg,
825 unsigned int data)
826 {
827 unsigned int res;
828 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
829
830 /* send bits of data specified by reg */
831 do {
832 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
833 reg, data);
834 if (res == VENDOR_STATUS_CHIPIO_OK)
835 return 0;
836 msleep(20);
837 } while (time_before(jiffies, timeout));
838
839 return -EIO;
840 }
841
842 /*
843 * Write chip address through the vendor widget -- NOT protected by the Mutex!
844 */
845 static int chipio_write_address(struct hda_codec *codec,
846 unsigned int chip_addx)
847 {
848 struct ca0132_spec *spec = codec->spec;
849 int res;
850
851 if (spec->curr_chip_addx == chip_addx)
852 return 0;
853
854 /* send low 16 bits of the address */
855 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
856 chip_addx & 0xffff);
857
858 if (res != -EIO) {
859 /* send high 16 bits of the address */
860 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
861 chip_addx >> 16);
862 }
863
864 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
865
866 return res;
867 }
868
869 /*
870 * Write data through the vendor widget -- NOT protected by the Mutex!
871 */
872 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
873 {
874 struct ca0132_spec *spec = codec->spec;
875 int res;
876
877 /* send low 16 bits of the data */
878 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
879
880 if (res != -EIO) {
881 /* send high 16 bits of the data */
882 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
883 data >> 16);
884 }
885
886 /*If no error encountered, automatically increment the address
887 as per chip behaviour*/
888 spec->curr_chip_addx = (res != -EIO) ?
889 (spec->curr_chip_addx + 4) : ~0UL;
890 return res;
891 }
892
893 /*
894 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
895 */
896 static int chipio_write_data_multiple(struct hda_codec *codec,
897 const u32 *data,
898 unsigned int count)
899 {
900 int status = 0;
901
902 if (data == NULL) {
903 codec_dbg(codec, "chipio_write_data null ptr\n");
904 return -EINVAL;
905 }
906
907 while ((count-- != 0) && (status == 0))
908 status = chipio_write_data(codec, *data++);
909
910 return status;
911 }
912
913
914 /*
915 * Read data through the vendor widget -- NOT protected by the Mutex!
916 */
917 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
918 {
919 struct ca0132_spec *spec = codec->spec;
920 int res;
921
922 /* post read */
923 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
924
925 if (res != -EIO) {
926 /* read status */
927 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
928 }
929
930 if (res != -EIO) {
931 /* read data */
932 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
933 VENDOR_CHIPIO_HIC_READ_DATA,
934 0);
935 }
936
937 /*If no error encountered, automatically increment the address
938 as per chip behaviour*/
939 spec->curr_chip_addx = (res != -EIO) ?
940 (spec->curr_chip_addx + 4) : ~0UL;
941 return res;
942 }
943
944 /*
945 * Write given value to the given address through the chip I/O widget.
946 * protected by the Mutex
947 */
948 static int chipio_write(struct hda_codec *codec,
949 unsigned int chip_addx, const unsigned int data)
950 {
951 struct ca0132_spec *spec = codec->spec;
952 int err;
953
954 mutex_lock(&spec->chipio_mutex);
955
956 /* write the address, and if successful proceed to write data */
957 err = chipio_write_address(codec, chip_addx);
958 if (err < 0)
959 goto exit;
960
961 err = chipio_write_data(codec, data);
962 if (err < 0)
963 goto exit;
964
965 exit:
966 mutex_unlock(&spec->chipio_mutex);
967 return err;
968 }
969
970 /*
971 * Write multiple values to the given address through the chip I/O widget.
972 * protected by the Mutex
973 */
974 static int chipio_write_multiple(struct hda_codec *codec,
975 u32 chip_addx,
976 const u32 *data,
977 unsigned int count)
978 {
979 struct ca0132_spec *spec = codec->spec;
980 int status;
981
982 mutex_lock(&spec->chipio_mutex);
983 status = chipio_write_address(codec, chip_addx);
984 if (status < 0)
985 goto error;
986
987 status = chipio_write_data_multiple(codec, data, count);
988 error:
989 mutex_unlock(&spec->chipio_mutex);
990
991 return status;
992 }
993
994 /*
995 * Read the given address through the chip I/O widget
996 * protected by the Mutex
997 */
998 static int chipio_read(struct hda_codec *codec,
999 unsigned int chip_addx, unsigned int *data)
1000 {
1001 struct ca0132_spec *spec = codec->spec;
1002 int err;
1003
1004 mutex_lock(&spec->chipio_mutex);
1005
1006 /* write the address, and if successful proceed to write data */
1007 err = chipio_write_address(codec, chip_addx);
1008 if (err < 0)
1009 goto exit;
1010
1011 err = chipio_read_data(codec, data);
1012 if (err < 0)
1013 goto exit;
1014
1015 exit:
1016 mutex_unlock(&spec->chipio_mutex);
1017 return err;
1018 }
1019
1020 /*
1021 * Set chip control flags through the chip I/O widget.
1022 */
1023 static void chipio_set_control_flag(struct hda_codec *codec,
1024 enum control_flag_id flag_id,
1025 bool flag_state)
1026 {
1027 unsigned int val;
1028 unsigned int flag_bit;
1029
1030 flag_bit = (flag_state ? 1 : 0);
1031 val = (flag_bit << 7) | (flag_id);
1032 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1033 VENDOR_CHIPIO_FLAG_SET, val);
1034 }
1035
1036 /*
1037 * Set chip parameters through the chip I/O widget.
1038 */
1039 static void chipio_set_control_param(struct hda_codec *codec,
1040 enum control_param_id param_id, int param_val)
1041 {
1042 struct ca0132_spec *spec = codec->spec;
1043 int val;
1044
1045 if ((param_id < 32) && (param_val < 8)) {
1046 val = (param_val << 5) | (param_id);
1047 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1048 VENDOR_CHIPIO_PARAM_SET, val);
1049 } else {
1050 mutex_lock(&spec->chipio_mutex);
1051 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1052 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1053 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1054 param_id);
1055 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1056 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1057 param_val);
1058 }
1059 mutex_unlock(&spec->chipio_mutex);
1060 }
1061 }
1062
1063 /*
1064 * Set sampling rate of the connection point.
1065 */
1066 static void chipio_set_conn_rate(struct hda_codec *codec,
1067 int connid, enum ca0132_sample_rate rate)
1068 {
1069 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1070 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1071 rate);
1072 }
1073
1074 /*
1075 * Enable clocks.
1076 */
1077 static void chipio_enable_clocks(struct hda_codec *codec)
1078 {
1079 struct ca0132_spec *spec = codec->spec;
1080
1081 mutex_lock(&spec->chipio_mutex);
1082 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1083 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1084 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1085 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1087 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1089 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1090 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1091 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1092 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1093 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1094 mutex_unlock(&spec->chipio_mutex);
1095 }
1096
1097 /*
1098 * CA0132 DSP IO stuffs
1099 */
1100 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1101 unsigned int data)
1102 {
1103 int res;
1104 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1105
1106 /* send bits of data specified by reg to dsp */
1107 do {
1108 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1109 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1110 return res;
1111 msleep(20);
1112 } while (time_before(jiffies, timeout));
1113
1114 return -EIO;
1115 }
1116
1117 /*
1118 * Wait for DSP to be ready for commands
1119 */
1120 static void dspio_write_wait(struct hda_codec *codec)
1121 {
1122 int status;
1123 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1124
1125 do {
1126 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1127 VENDOR_DSPIO_STATUS, 0);
1128 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1129 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1130 break;
1131 msleep(1);
1132 } while (time_before(jiffies, timeout));
1133 }
1134
1135 /*
1136 * Write SCP data to DSP
1137 */
1138 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1139 {
1140 struct ca0132_spec *spec = codec->spec;
1141 int status;
1142
1143 dspio_write_wait(codec);
1144
1145 mutex_lock(&spec->chipio_mutex);
1146 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1147 scp_data & 0xffff);
1148 if (status < 0)
1149 goto error;
1150
1151 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1152 scp_data >> 16);
1153 if (status < 0)
1154 goto error;
1155
1156 /* OK, now check if the write itself has executed*/
1157 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1158 VENDOR_DSPIO_STATUS, 0);
1159 error:
1160 mutex_unlock(&spec->chipio_mutex);
1161
1162 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1163 -EIO : 0;
1164 }
1165
1166 /*
1167 * Write multiple SCP data to DSP
1168 */
1169 static int dspio_write_multiple(struct hda_codec *codec,
1170 unsigned int *buffer, unsigned int size)
1171 {
1172 int status = 0;
1173 unsigned int count;
1174
1175 if ((buffer == NULL))
1176 return -EINVAL;
1177
1178 count = 0;
1179 while (count < size) {
1180 status = dspio_write(codec, *buffer++);
1181 if (status != 0)
1182 break;
1183 count++;
1184 }
1185
1186 return status;
1187 }
1188
1189 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1190 {
1191 int status;
1192
1193 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1194 if (status == -EIO)
1195 return status;
1196
1197 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1198 if (status == -EIO ||
1199 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1200 return -EIO;
1201
1202 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1203 VENDOR_DSPIO_SCP_READ_DATA, 0);
1204
1205 return 0;
1206 }
1207
1208 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1209 unsigned int *buf_size, unsigned int size_count)
1210 {
1211 int status = 0;
1212 unsigned int size = *buf_size;
1213 unsigned int count;
1214 unsigned int skip_count;
1215 unsigned int dummy;
1216
1217 if ((buffer == NULL))
1218 return -1;
1219
1220 count = 0;
1221 while (count < size && count < size_count) {
1222 status = dspio_read(codec, buffer++);
1223 if (status != 0)
1224 break;
1225 count++;
1226 }
1227
1228 skip_count = count;
1229 if (status == 0) {
1230 while (skip_count < size) {
1231 status = dspio_read(codec, &dummy);
1232 if (status != 0)
1233 break;
1234 skip_count++;
1235 }
1236 }
1237 *buf_size = count;
1238
1239 return status;
1240 }
1241
1242 /*
1243 * Construct the SCP header using corresponding fields
1244 */
1245 static inline unsigned int
1246 make_scp_header(unsigned int target_id, unsigned int source_id,
1247 unsigned int get_flag, unsigned int req,
1248 unsigned int device_flag, unsigned int resp_flag,
1249 unsigned int error_flag, unsigned int data_size)
1250 {
1251 unsigned int header = 0;
1252
1253 header = (data_size & 0x1f) << 27;
1254 header |= (error_flag & 0x01) << 26;
1255 header |= (resp_flag & 0x01) << 25;
1256 header |= (device_flag & 0x01) << 24;
1257 header |= (req & 0x7f) << 17;
1258 header |= (get_flag & 0x01) << 16;
1259 header |= (source_id & 0xff) << 8;
1260 header |= target_id & 0xff;
1261
1262 return header;
1263 }
1264
1265 /*
1266 * Extract corresponding fields from SCP header
1267 */
1268 static inline void
1269 extract_scp_header(unsigned int header,
1270 unsigned int *target_id, unsigned int *source_id,
1271 unsigned int *get_flag, unsigned int *req,
1272 unsigned int *device_flag, unsigned int *resp_flag,
1273 unsigned int *error_flag, unsigned int *data_size)
1274 {
1275 if (data_size)
1276 *data_size = (header >> 27) & 0x1f;
1277 if (error_flag)
1278 *error_flag = (header >> 26) & 0x01;
1279 if (resp_flag)
1280 *resp_flag = (header >> 25) & 0x01;
1281 if (device_flag)
1282 *device_flag = (header >> 24) & 0x01;
1283 if (req)
1284 *req = (header >> 17) & 0x7f;
1285 if (get_flag)
1286 *get_flag = (header >> 16) & 0x01;
1287 if (source_id)
1288 *source_id = (header >> 8) & 0xff;
1289 if (target_id)
1290 *target_id = header & 0xff;
1291 }
1292
1293 #define SCP_MAX_DATA_WORDS (16)
1294
1295 /* Structure to contain any SCP message */
1296 struct scp_msg {
1297 unsigned int hdr;
1298 unsigned int data[SCP_MAX_DATA_WORDS];
1299 };
1300
1301 static void dspio_clear_response_queue(struct hda_codec *codec)
1302 {
1303 unsigned int dummy = 0;
1304 int status = -1;
1305
1306 /* clear all from the response queue */
1307 do {
1308 status = dspio_read(codec, &dummy);
1309 } while (status == 0);
1310 }
1311
1312 static int dspio_get_response_data(struct hda_codec *codec)
1313 {
1314 struct ca0132_spec *spec = codec->spec;
1315 unsigned int data = 0;
1316 unsigned int count;
1317
1318 if (dspio_read(codec, &data) < 0)
1319 return -EIO;
1320
1321 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1322 spec->scp_resp_header = data;
1323 spec->scp_resp_count = data >> 27;
1324 count = spec->wait_num_data;
1325 dspio_read_multiple(codec, spec->scp_resp_data,
1326 &spec->scp_resp_count, count);
1327 return 0;
1328 }
1329
1330 return -EIO;
1331 }
1332
1333 /*
1334 * Send SCP message to DSP
1335 */
1336 static int dspio_send_scp_message(struct hda_codec *codec,
1337 unsigned char *send_buf,
1338 unsigned int send_buf_size,
1339 unsigned char *return_buf,
1340 unsigned int return_buf_size,
1341 unsigned int *bytes_returned)
1342 {
1343 struct ca0132_spec *spec = codec->spec;
1344 int status = -1;
1345 unsigned int scp_send_size = 0;
1346 unsigned int total_size;
1347 bool waiting_for_resp = false;
1348 unsigned int header;
1349 struct scp_msg *ret_msg;
1350 unsigned int resp_src_id, resp_target_id;
1351 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1352
1353 if (bytes_returned)
1354 *bytes_returned = 0;
1355
1356 /* get scp header from buffer */
1357 header = *((unsigned int *)send_buf);
1358 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1359 &device_flag, NULL, NULL, &data_size);
1360 scp_send_size = data_size + 1;
1361 total_size = (scp_send_size * 4);
1362
1363 if (send_buf_size < total_size)
1364 return -EINVAL;
1365
1366 if (get_flag || device_flag) {
1367 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1368 return -EINVAL;
1369
1370 spec->wait_scp_header = *((unsigned int *)send_buf);
1371
1372 /* swap source id with target id */
1373 resp_target_id = src_id;
1374 resp_src_id = target_id;
1375 spec->wait_scp_header &= 0xffff0000;
1376 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1377 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1378 spec->wait_scp = 1;
1379 waiting_for_resp = true;
1380 }
1381
1382 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1383 scp_send_size);
1384 if (status < 0) {
1385 spec->wait_scp = 0;
1386 return status;
1387 }
1388
1389 if (waiting_for_resp) {
1390 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1391 memset(return_buf, 0, return_buf_size);
1392 do {
1393 msleep(20);
1394 } while (spec->wait_scp && time_before(jiffies, timeout));
1395 waiting_for_resp = false;
1396 if (!spec->wait_scp) {
1397 ret_msg = (struct scp_msg *)return_buf;
1398 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1399 memcpy(&ret_msg->data, spec->scp_resp_data,
1400 spec->wait_num_data);
1401 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1402 status = 0;
1403 } else {
1404 status = -EIO;
1405 }
1406 spec->wait_scp = 0;
1407 }
1408
1409 return status;
1410 }
1411
1412 /**
1413 * Prepare and send the SCP message to DSP
1414 * @codec: the HDA codec
1415 * @mod_id: ID of the DSP module to send the command
1416 * @req: ID of request to send to the DSP module
1417 * @dir: SET or GET
1418 * @data: pointer to the data to send with the request, request specific
1419 * @len: length of the data, in bytes
1420 * @reply: point to the buffer to hold data returned for a reply
1421 * @reply_len: length of the reply buffer returned from GET
1422 *
1423 * Returns zero or a negative error code.
1424 */
1425 static int dspio_scp(struct hda_codec *codec,
1426 int mod_id, int req, int dir, void *data, unsigned int len,
1427 void *reply, unsigned int *reply_len)
1428 {
1429 int status = 0;
1430 struct scp_msg scp_send, scp_reply;
1431 unsigned int ret_bytes, send_size, ret_size;
1432 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1433 unsigned int reply_data_size;
1434
1435 memset(&scp_send, 0, sizeof(scp_send));
1436 memset(&scp_reply, 0, sizeof(scp_reply));
1437
1438 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1439 return -EINVAL;
1440
1441 if (dir == SCP_GET && reply == NULL) {
1442 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1443 return -EINVAL;
1444 }
1445
1446 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1447 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1448 return -EINVAL;
1449 }
1450
1451 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1452 0, 0, 0, len/sizeof(unsigned int));
1453 if (data != NULL && len > 0) {
1454 len = min((unsigned int)(sizeof(scp_send.data)), len);
1455 memcpy(scp_send.data, data, len);
1456 }
1457
1458 ret_bytes = 0;
1459 send_size = sizeof(unsigned int) + len;
1460 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1461 send_size, (unsigned char *)&scp_reply,
1462 sizeof(scp_reply), &ret_bytes);
1463
1464 if (status < 0) {
1465 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1466 return status;
1467 }
1468
1469 /* extract send and reply headers members */
1470 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1471 NULL, NULL, NULL, NULL, NULL);
1472 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1473 &reply_resp_flag, &reply_error_flag,
1474 &reply_data_size);
1475
1476 if (!send_get_flag)
1477 return 0;
1478
1479 if (reply_resp_flag && !reply_error_flag) {
1480 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1481 / sizeof(unsigned int);
1482
1483 if (*reply_len < ret_size*sizeof(unsigned int)) {
1484 codec_dbg(codec, "reply too long for buf\n");
1485 return -EINVAL;
1486 } else if (ret_size != reply_data_size) {
1487 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1488 return -EINVAL;
1489 } else if (!reply) {
1490 codec_dbg(codec, "NULL reply\n");
1491 return -EINVAL;
1492 } else {
1493 *reply_len = ret_size*sizeof(unsigned int);
1494 memcpy(reply, scp_reply.data, *reply_len);
1495 }
1496 } else {
1497 codec_dbg(codec, "reply ill-formed or errflag set\n");
1498 return -EIO;
1499 }
1500
1501 return status;
1502 }
1503
1504 /*
1505 * Set DSP parameters
1506 */
1507 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1508 int req, void *data, unsigned int len)
1509 {
1510 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1511 }
1512
1513 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1514 int req, unsigned int data)
1515 {
1516 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1517 }
1518
1519 /*
1520 * Allocate a DSP DMA channel via an SCP message
1521 */
1522 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1523 {
1524 int status = 0;
1525 unsigned int size = sizeof(dma_chan);
1526
1527 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
1528 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1529 SCP_GET, NULL, 0, dma_chan, &size);
1530
1531 if (status < 0) {
1532 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1533 return status;
1534 }
1535
1536 if ((*dma_chan + 1) == 0) {
1537 codec_dbg(codec, "no free dma channels to allocate\n");
1538 return -EBUSY;
1539 }
1540
1541 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1542 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
1543
1544 return status;
1545 }
1546
1547 /*
1548 * Free a DSP DMA via an SCP message
1549 */
1550 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1551 {
1552 int status = 0;
1553 unsigned int dummy = 0;
1554
1555 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1556 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1557
1558 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1559 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1560
1561 if (status < 0) {
1562 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1563 return status;
1564 }
1565
1566 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
1567
1568 return status;
1569 }
1570
1571 /*
1572 * (Re)start the DSP
1573 */
1574 static int dsp_set_run_state(struct hda_codec *codec)
1575 {
1576 unsigned int dbg_ctrl_reg;
1577 unsigned int halt_state;
1578 int err;
1579
1580 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1581 if (err < 0)
1582 return err;
1583
1584 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1585 DSP_DBGCNTL_STATE_LOBIT;
1586
1587 if (halt_state != 0) {
1588 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1589 DSP_DBGCNTL_SS_MASK);
1590 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1591 dbg_ctrl_reg);
1592 if (err < 0)
1593 return err;
1594
1595 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1596 DSP_DBGCNTL_EXEC_MASK;
1597 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1598 dbg_ctrl_reg);
1599 if (err < 0)
1600 return err;
1601 }
1602
1603 return 0;
1604 }
1605
1606 /*
1607 * Reset the DSP
1608 */
1609 static int dsp_reset(struct hda_codec *codec)
1610 {
1611 unsigned int res;
1612 int retry = 20;
1613
1614 codec_dbg(codec, "dsp_reset\n");
1615 do {
1616 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1617 retry--;
1618 } while (res == -EIO && retry);
1619
1620 if (!retry) {
1621 codec_dbg(codec, "dsp_reset timeout\n");
1622 return -EIO;
1623 }
1624
1625 return 0;
1626 }
1627
1628 /*
1629 * Convert chip address to DSP address
1630 */
1631 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1632 bool *code, bool *yram)
1633 {
1634 *code = *yram = false;
1635
1636 if (UC_RANGE(chip_addx, 1)) {
1637 *code = true;
1638 return UC_OFF(chip_addx);
1639 } else if (X_RANGE_ALL(chip_addx, 1)) {
1640 return X_OFF(chip_addx);
1641 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1642 *yram = true;
1643 return Y_OFF(chip_addx);
1644 }
1645
1646 return INVALID_CHIP_ADDRESS;
1647 }
1648
1649 /*
1650 * Check if the DSP DMA is active
1651 */
1652 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1653 {
1654 unsigned int dma_chnlstart_reg;
1655
1656 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1657
1658 return ((dma_chnlstart_reg & (1 <<
1659 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1660 }
1661
1662 static int dsp_dma_setup_common(struct hda_codec *codec,
1663 unsigned int chip_addx,
1664 unsigned int dma_chan,
1665 unsigned int port_map_mask,
1666 bool ovly)
1667 {
1668 int status = 0;
1669 unsigned int chnl_prop;
1670 unsigned int dsp_addx;
1671 unsigned int active;
1672 bool code, yram;
1673
1674 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
1675
1676 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1677 codec_dbg(codec, "dma chan num invalid\n");
1678 return -EINVAL;
1679 }
1680
1681 if (dsp_is_dma_active(codec, dma_chan)) {
1682 codec_dbg(codec, "dma already active\n");
1683 return -EBUSY;
1684 }
1685
1686 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1687
1688 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1689 codec_dbg(codec, "invalid chip addr\n");
1690 return -ENXIO;
1691 }
1692
1693 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1694 active = 0;
1695
1696 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
1697
1698 if (ovly) {
1699 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1700 &chnl_prop);
1701
1702 if (status < 0) {
1703 codec_dbg(codec, "read CHNLPROP Reg fail\n");
1704 return status;
1705 }
1706 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
1707 }
1708
1709 if (!code)
1710 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1711 else
1712 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1713
1714 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1715
1716 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1717 if (status < 0) {
1718 codec_dbg(codec, "write CHNLPROP Reg fail\n");
1719 return status;
1720 }
1721 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
1722
1723 if (ovly) {
1724 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1725 &active);
1726
1727 if (status < 0) {
1728 codec_dbg(codec, "read ACTIVE Reg fail\n");
1729 return status;
1730 }
1731 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
1732 }
1733
1734 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1735 DSPDMAC_ACTIVE_AAR_MASK;
1736
1737 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1738 if (status < 0) {
1739 codec_dbg(codec, "write ACTIVE Reg fail\n");
1740 return status;
1741 }
1742
1743 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
1744
1745 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1746 port_map_mask);
1747 if (status < 0) {
1748 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
1749 return status;
1750 }
1751 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
1752
1753 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1754 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1755 if (status < 0) {
1756 codec_dbg(codec, "write IRQCNT Reg fail\n");
1757 return status;
1758 }
1759 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
1760
1761 codec_dbg(codec,
1762 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1763 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1764 chip_addx, dsp_addx, dma_chan,
1765 port_map_mask, chnl_prop, active);
1766
1767 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
1768
1769 return 0;
1770 }
1771
1772 /*
1773 * Setup the DSP DMA per-transfer-specific registers
1774 */
1775 static int dsp_dma_setup(struct hda_codec *codec,
1776 unsigned int chip_addx,
1777 unsigned int count,
1778 unsigned int dma_chan)
1779 {
1780 int status = 0;
1781 bool code, yram;
1782 unsigned int dsp_addx;
1783 unsigned int addr_field;
1784 unsigned int incr_field;
1785 unsigned int base_cnt;
1786 unsigned int cur_cnt;
1787 unsigned int dma_cfg = 0;
1788 unsigned int adr_ofs = 0;
1789 unsigned int xfr_cnt = 0;
1790 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1791 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1792
1793 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
1794
1795 if (count > max_dma_count) {
1796 codec_dbg(codec, "count too big\n");
1797 return -EINVAL;
1798 }
1799
1800 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1801 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1802 codec_dbg(codec, "invalid chip addr\n");
1803 return -ENXIO;
1804 }
1805
1806 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
1807
1808 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1809 incr_field = 0;
1810
1811 if (!code) {
1812 addr_field <<= 1;
1813 if (yram)
1814 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1815
1816 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1817 }
1818
1819 dma_cfg = addr_field + incr_field;
1820 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1821 dma_cfg);
1822 if (status < 0) {
1823 codec_dbg(codec, "write DMACFG Reg fail\n");
1824 return status;
1825 }
1826 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
1827
1828 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1829 (code ? 0 : 1));
1830
1831 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1832 adr_ofs);
1833 if (status < 0) {
1834 codec_dbg(codec, "write DSPADROFS Reg fail\n");
1835 return status;
1836 }
1837 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
1838
1839 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1840
1841 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1842
1843 xfr_cnt = base_cnt | cur_cnt;
1844
1845 status = chipio_write(codec,
1846 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1847 if (status < 0) {
1848 codec_dbg(codec, "write XFRCNT Reg fail\n");
1849 return status;
1850 }
1851 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
1852
1853 codec_dbg(codec,
1854 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1855 "ADROFS=0x%x, XFRCNT=0x%x\n",
1856 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1857
1858 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
1859
1860 return 0;
1861 }
1862
1863 /*
1864 * Start the DSP DMA
1865 */
1866 static int dsp_dma_start(struct hda_codec *codec,
1867 unsigned int dma_chan, bool ovly)
1868 {
1869 unsigned int reg = 0;
1870 int status = 0;
1871
1872 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
1873
1874 if (ovly) {
1875 status = chipio_read(codec,
1876 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1877
1878 if (status < 0) {
1879 codec_dbg(codec, "read CHNLSTART reg fail\n");
1880 return status;
1881 }
1882 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
1883
1884 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1885 DSPDMAC_CHNLSTART_DIS_MASK);
1886 }
1887
1888 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1889 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1890 if (status < 0) {
1891 codec_dbg(codec, "write CHNLSTART reg fail\n");
1892 return status;
1893 }
1894 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
1895
1896 return status;
1897 }
1898
1899 /*
1900 * Stop the DSP DMA
1901 */
1902 static int dsp_dma_stop(struct hda_codec *codec,
1903 unsigned int dma_chan, bool ovly)
1904 {
1905 unsigned int reg = 0;
1906 int status = 0;
1907
1908 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
1909
1910 if (ovly) {
1911 status = chipio_read(codec,
1912 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1913
1914 if (status < 0) {
1915 codec_dbg(codec, "read CHNLSTART reg fail\n");
1916 return status;
1917 }
1918 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
1919 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1920 DSPDMAC_CHNLSTART_DIS_MASK);
1921 }
1922
1923 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1924 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1925 if (status < 0) {
1926 codec_dbg(codec, "write CHNLSTART reg fail\n");
1927 return status;
1928 }
1929 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
1930
1931 return status;
1932 }
1933
1934 /**
1935 * Allocate router ports
1936 *
1937 * @codec: the HDA codec
1938 * @num_chans: number of channels in the stream
1939 * @ports_per_channel: number of ports per channel
1940 * @start_device: start device
1941 * @port_map: pointer to the port list to hold the allocated ports
1942 *
1943 * Returns zero or a negative error code.
1944 */
1945 static int dsp_allocate_router_ports(struct hda_codec *codec,
1946 unsigned int num_chans,
1947 unsigned int ports_per_channel,
1948 unsigned int start_device,
1949 unsigned int *port_map)
1950 {
1951 int status = 0;
1952 int res;
1953 u8 val;
1954
1955 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1956 if (status < 0)
1957 return status;
1958
1959 val = start_device << 6;
1960 val |= (ports_per_channel - 1) << 4;
1961 val |= num_chans - 1;
1962
1963 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1964 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1965 val);
1966
1967 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1968 VENDOR_CHIPIO_PORT_ALLOC_SET,
1969 MEM_CONNID_DSP);
1970
1971 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1972 if (status < 0)
1973 return status;
1974
1975 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1976 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1977
1978 *port_map = res;
1979
1980 return (res < 0) ? res : 0;
1981 }
1982
1983 /*
1984 * Free router ports
1985 */
1986 static int dsp_free_router_ports(struct hda_codec *codec)
1987 {
1988 int status = 0;
1989
1990 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1991 if (status < 0)
1992 return status;
1993
1994 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1995 VENDOR_CHIPIO_PORT_FREE_SET,
1996 MEM_CONNID_DSP);
1997
1998 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1999
2000 return status;
2001 }
2002
2003 /*
2004 * Allocate DSP ports for the download stream
2005 */
2006 static int dsp_allocate_ports(struct hda_codec *codec,
2007 unsigned int num_chans,
2008 unsigned int rate_multi, unsigned int *port_map)
2009 {
2010 int status;
2011
2012 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2013
2014 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2015 codec_dbg(codec, "bad rate multiple\n");
2016 return -EINVAL;
2017 }
2018
2019 status = dsp_allocate_router_ports(codec, num_chans,
2020 rate_multi, 0, port_map);
2021
2022 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2023
2024 return status;
2025 }
2026
2027 static int dsp_allocate_ports_format(struct hda_codec *codec,
2028 const unsigned short fmt,
2029 unsigned int *port_map)
2030 {
2031 int status;
2032 unsigned int num_chans;
2033
2034 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2035 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2036 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2037
2038 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2039 codec_dbg(codec, "bad rate multiple\n");
2040 return -EINVAL;
2041 }
2042
2043 num_chans = get_hdafmt_chs(fmt) + 1;
2044
2045 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2046
2047 return status;
2048 }
2049
2050 /*
2051 * free DSP ports
2052 */
2053 static int dsp_free_ports(struct hda_codec *codec)
2054 {
2055 int status;
2056
2057 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2058
2059 status = dsp_free_router_ports(codec);
2060 if (status < 0) {
2061 codec_dbg(codec, "free router ports fail\n");
2062 return status;
2063 }
2064 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2065
2066 return status;
2067 }
2068
2069 /*
2070 * HDA DMA engine stuffs for DSP code download
2071 */
2072 struct dma_engine {
2073 struct hda_codec *codec;
2074 unsigned short m_converter_format;
2075 struct snd_dma_buffer *dmab;
2076 unsigned int buf_size;
2077 };
2078
2079
2080 enum dma_state {
2081 DMA_STATE_STOP = 0,
2082 DMA_STATE_RUN = 1
2083 };
2084
2085 static int dma_convert_to_hda_format(struct hda_codec *codec,
2086 unsigned int sample_rate,
2087 unsigned short channels,
2088 unsigned short *hda_format)
2089 {
2090 unsigned int format_val;
2091
2092 format_val = snd_hdac_calc_stream_format(sample_rate,
2093 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2094
2095 if (hda_format)
2096 *hda_format = (unsigned short)format_val;
2097
2098 return 0;
2099 }
2100
2101 /*
2102 * Reset DMA for DSP download
2103 */
2104 static int dma_reset(struct dma_engine *dma)
2105 {
2106 struct hda_codec *codec = dma->codec;
2107 struct ca0132_spec *spec = codec->spec;
2108 int status;
2109
2110 if (dma->dmab->area)
2111 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2112
2113 status = snd_hda_codec_load_dsp_prepare(codec,
2114 dma->m_converter_format,
2115 dma->buf_size,
2116 dma->dmab);
2117 if (status < 0)
2118 return status;
2119 spec->dsp_stream_id = status;
2120 return 0;
2121 }
2122
2123 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2124 {
2125 bool cmd;
2126
2127 switch (state) {
2128 case DMA_STATE_STOP:
2129 cmd = false;
2130 break;
2131 case DMA_STATE_RUN:
2132 cmd = true;
2133 break;
2134 default:
2135 return 0;
2136 }
2137
2138 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2139 return 0;
2140 }
2141
2142 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2143 {
2144 return dma->dmab->bytes;
2145 }
2146
2147 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2148 {
2149 return dma->dmab->area;
2150 }
2151
2152 static int dma_xfer(struct dma_engine *dma,
2153 const unsigned int *data,
2154 unsigned int count)
2155 {
2156 memcpy(dma->dmab->area, data, count);
2157 return 0;
2158 }
2159
2160 static void dma_get_converter_format(
2161 struct dma_engine *dma,
2162 unsigned short *format)
2163 {
2164 if (format)
2165 *format = dma->m_converter_format;
2166 }
2167
2168 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2169 {
2170 struct ca0132_spec *spec = dma->codec->spec;
2171
2172 return spec->dsp_stream_id;
2173 }
2174
2175 struct dsp_image_seg {
2176 u32 magic;
2177 u32 chip_addr;
2178 u32 count;
2179 u32 data[0];
2180 };
2181
2182 static const u32 g_magic_value = 0x4c46584d;
2183 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2184
2185 static bool is_valid(const struct dsp_image_seg *p)
2186 {
2187 return p->magic == g_magic_value;
2188 }
2189
2190 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2191 {
2192 return g_chip_addr_magic_value == p->chip_addr;
2193 }
2194
2195 static bool is_last(const struct dsp_image_seg *p)
2196 {
2197 return p->count == 0;
2198 }
2199
2200 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2201 {
2202 return sizeof(*p) + p->count*sizeof(u32);
2203 }
2204
2205 static const struct dsp_image_seg *get_next_seg_ptr(
2206 const struct dsp_image_seg *p)
2207 {
2208 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2209 }
2210
2211 /*
2212 * CA0132 chip DSP transfer stuffs. For DSP download.
2213 */
2214 #define INVALID_DMA_CHANNEL (~0U)
2215
2216 /*
2217 * Program a list of address/data pairs via the ChipIO widget.
2218 * The segment data is in the format of successive pairs of words.
2219 * These are repeated as indicated by the segment's count field.
2220 */
2221 static int dspxfr_hci_write(struct hda_codec *codec,
2222 const struct dsp_image_seg *fls)
2223 {
2224 int status;
2225 const u32 *data;
2226 unsigned int count;
2227
2228 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2229 codec_dbg(codec, "hci_write invalid params\n");
2230 return -EINVAL;
2231 }
2232
2233 count = fls->count;
2234 data = (u32 *)(fls->data);
2235 while (count >= 2) {
2236 status = chipio_write(codec, data[0], data[1]);
2237 if (status < 0) {
2238 codec_dbg(codec, "hci_write chipio failed\n");
2239 return status;
2240 }
2241 count -= 2;
2242 data += 2;
2243 }
2244 return 0;
2245 }
2246
2247 /**
2248 * Write a block of data into DSP code or data RAM using pre-allocated
2249 * DMA engine.
2250 *
2251 * @codec: the HDA codec
2252 * @fls: pointer to a fast load image
2253 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2254 * no relocation
2255 * @dma_engine: pointer to DMA engine to be used for DSP download
2256 * @dma_chan: The number of DMA channels used for DSP download
2257 * @port_map_mask: port mapping
2258 * @ovly: TRUE if overlay format is required
2259 *
2260 * Returns zero or a negative error code.
2261 */
2262 static int dspxfr_one_seg(struct hda_codec *codec,
2263 const struct dsp_image_seg *fls,
2264 unsigned int reloc,
2265 struct dma_engine *dma_engine,
2266 unsigned int dma_chan,
2267 unsigned int port_map_mask,
2268 bool ovly)
2269 {
2270 int status = 0;
2271 bool comm_dma_setup_done = false;
2272 const unsigned int *data;
2273 unsigned int chip_addx;
2274 unsigned int words_to_write;
2275 unsigned int buffer_size_words;
2276 unsigned char *buffer_addx;
2277 unsigned short hda_format;
2278 unsigned int sample_rate_div;
2279 unsigned int sample_rate_mul;
2280 unsigned int num_chans;
2281 unsigned int hda_frame_size_words;
2282 unsigned int remainder_words;
2283 const u32 *data_remainder;
2284 u32 chip_addx_remainder;
2285 unsigned int run_size_words;
2286 const struct dsp_image_seg *hci_write = NULL;
2287 unsigned long timeout;
2288 bool dma_active;
2289
2290 if (fls == NULL)
2291 return -EINVAL;
2292 if (is_hci_prog_list_seg(fls)) {
2293 hci_write = fls;
2294 fls = get_next_seg_ptr(fls);
2295 }
2296
2297 if (hci_write && (!fls || is_last(fls))) {
2298 codec_dbg(codec, "hci_write\n");
2299 return dspxfr_hci_write(codec, hci_write);
2300 }
2301
2302 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2303 codec_dbg(codec, "Invalid Params\n");
2304 return -EINVAL;
2305 }
2306
2307 data = fls->data;
2308 chip_addx = fls->chip_addr,
2309 words_to_write = fls->count;
2310
2311 if (!words_to_write)
2312 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2313 if (reloc)
2314 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2315
2316 if (!UC_RANGE(chip_addx, words_to_write) &&
2317 !X_RANGE_ALL(chip_addx, words_to_write) &&
2318 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2319 codec_dbg(codec, "Invalid chip_addx Params\n");
2320 return -EINVAL;
2321 }
2322
2323 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2324 sizeof(u32);
2325
2326 buffer_addx = dma_get_buffer_addr(dma_engine);
2327
2328 if (buffer_addx == NULL) {
2329 codec_dbg(codec, "dma_engine buffer NULL\n");
2330 return -EINVAL;
2331 }
2332
2333 dma_get_converter_format(dma_engine, &hda_format);
2334 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2335 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2336 num_chans = get_hdafmt_chs(hda_format) + 1;
2337
2338 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2339 (num_chans * sample_rate_mul / sample_rate_div));
2340
2341 if (hda_frame_size_words == 0) {
2342 codec_dbg(codec, "frmsz zero\n");
2343 return -EINVAL;
2344 }
2345
2346 buffer_size_words = min(buffer_size_words,
2347 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2348 65536 : 32768));
2349 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2350 codec_dbg(codec,
2351 "chpadr=0x%08x frmsz=%u nchan=%u "
2352 "rate_mul=%u div=%u bufsz=%u\n",
2353 chip_addx, hda_frame_size_words, num_chans,
2354 sample_rate_mul, sample_rate_div, buffer_size_words);
2355
2356 if (buffer_size_words < hda_frame_size_words) {
2357 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2358 return -EINVAL;
2359 }
2360
2361 remainder_words = words_to_write % hda_frame_size_words;
2362 data_remainder = data;
2363 chip_addx_remainder = chip_addx;
2364
2365 data += remainder_words;
2366 chip_addx += remainder_words*sizeof(u32);
2367 words_to_write -= remainder_words;
2368
2369 while (words_to_write != 0) {
2370 run_size_words = min(buffer_size_words, words_to_write);
2371 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2372 words_to_write, run_size_words, remainder_words);
2373 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2374 if (!comm_dma_setup_done) {
2375 status = dsp_dma_stop(codec, dma_chan, ovly);
2376 if (status < 0)
2377 return status;
2378 status = dsp_dma_setup_common(codec, chip_addx,
2379 dma_chan, port_map_mask, ovly);
2380 if (status < 0)
2381 return status;
2382 comm_dma_setup_done = true;
2383 }
2384
2385 status = dsp_dma_setup(codec, chip_addx,
2386 run_size_words, dma_chan);
2387 if (status < 0)
2388 return status;
2389 status = dsp_dma_start(codec, dma_chan, ovly);
2390 if (status < 0)
2391 return status;
2392 if (!dsp_is_dma_active(codec, dma_chan)) {
2393 codec_dbg(codec, "dspxfr:DMA did not start\n");
2394 return -EIO;
2395 }
2396 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2397 if (status < 0)
2398 return status;
2399 if (remainder_words != 0) {
2400 status = chipio_write_multiple(codec,
2401 chip_addx_remainder,
2402 data_remainder,
2403 remainder_words);
2404 if (status < 0)
2405 return status;
2406 remainder_words = 0;
2407 }
2408 if (hci_write) {
2409 status = dspxfr_hci_write(codec, hci_write);
2410 if (status < 0)
2411 return status;
2412 hci_write = NULL;
2413 }
2414
2415 timeout = jiffies + msecs_to_jiffies(2000);
2416 do {
2417 dma_active = dsp_is_dma_active(codec, dma_chan);
2418 if (!dma_active)
2419 break;
2420 msleep(20);
2421 } while (time_before(jiffies, timeout));
2422 if (dma_active)
2423 break;
2424
2425 codec_dbg(codec, "+++++ DMA complete\n");
2426 dma_set_state(dma_engine, DMA_STATE_STOP);
2427 status = dma_reset(dma_engine);
2428
2429 if (status < 0)
2430 return status;
2431
2432 data += run_size_words;
2433 chip_addx += run_size_words*sizeof(u32);
2434 words_to_write -= run_size_words;
2435 }
2436
2437 if (remainder_words != 0) {
2438 status = chipio_write_multiple(codec, chip_addx_remainder,
2439 data_remainder, remainder_words);
2440 }
2441
2442 return status;
2443 }
2444
2445 /**
2446 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2447 *
2448 * @codec: the HDA codec
2449 * @fls_data: pointer to a fast load image
2450 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2451 * no relocation
2452 * @sample_rate: sampling rate of the stream used for DSP download
2453 * @channels: channels of the stream used for DSP download
2454 * @ovly: TRUE if overlay format is required
2455 *
2456 * Returns zero or a negative error code.
2457 */
2458 static int dspxfr_image(struct hda_codec *codec,
2459 const struct dsp_image_seg *fls_data,
2460 unsigned int reloc,
2461 unsigned int sample_rate,
2462 unsigned short channels,
2463 bool ovly)
2464 {
2465 struct ca0132_spec *spec = codec->spec;
2466 int status;
2467 unsigned short hda_format = 0;
2468 unsigned int response;
2469 unsigned char stream_id = 0;
2470 struct dma_engine *dma_engine;
2471 unsigned int dma_chan;
2472 unsigned int port_map_mask;
2473
2474 if (fls_data == NULL)
2475 return -EINVAL;
2476
2477 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2478 if (!dma_engine)
2479 return -ENOMEM;
2480
2481 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2482 if (!dma_engine->dmab) {
2483 kfree(dma_engine);
2484 return -ENOMEM;
2485 }
2486
2487 dma_engine->codec = codec;
2488 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2489 dma_engine->m_converter_format = hda_format;
2490 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2491 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2492
2493 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2494
2495 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2496 hda_format, &response);
2497
2498 if (status < 0) {
2499 codec_dbg(codec, "set converter format fail\n");
2500 goto exit;
2501 }
2502
2503 status = snd_hda_codec_load_dsp_prepare(codec,
2504 dma_engine->m_converter_format,
2505 dma_engine->buf_size,
2506 dma_engine->dmab);
2507 if (status < 0)
2508 goto exit;
2509 spec->dsp_stream_id = status;
2510
2511 if (ovly) {
2512 status = dspio_alloc_dma_chan(codec, &dma_chan);
2513 if (status < 0) {
2514 codec_dbg(codec, "alloc dmachan fail\n");
2515 dma_chan = INVALID_DMA_CHANNEL;
2516 goto exit;
2517 }
2518 }
2519
2520 port_map_mask = 0;
2521 status = dsp_allocate_ports_format(codec, hda_format,
2522 &port_map_mask);
2523 if (status < 0) {
2524 codec_dbg(codec, "alloc ports fail\n");
2525 goto exit;
2526 }
2527
2528 stream_id = dma_get_stream_id(dma_engine);
2529 status = codec_set_converter_stream_channel(codec,
2530 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2531 if (status < 0) {
2532 codec_dbg(codec, "set stream chan fail\n");
2533 goto exit;
2534 }
2535
2536 while ((fls_data != NULL) && !is_last(fls_data)) {
2537 if (!is_valid(fls_data)) {
2538 codec_dbg(codec, "FLS check fail\n");
2539 status = -EINVAL;
2540 goto exit;
2541 }
2542 status = dspxfr_one_seg(codec, fls_data, reloc,
2543 dma_engine, dma_chan,
2544 port_map_mask, ovly);
2545 if (status < 0)
2546 break;
2547
2548 if (is_hci_prog_list_seg(fls_data))
2549 fls_data = get_next_seg_ptr(fls_data);
2550
2551 if ((fls_data != NULL) && !is_last(fls_data))
2552 fls_data = get_next_seg_ptr(fls_data);
2553 }
2554
2555 if (port_map_mask != 0)
2556 status = dsp_free_ports(codec);
2557
2558 if (status < 0)
2559 goto exit;
2560
2561 status = codec_set_converter_stream_channel(codec,
2562 WIDGET_CHIP_CTRL, 0, 0, &response);
2563
2564 exit:
2565 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2566 dspio_free_dma_chan(codec, dma_chan);
2567
2568 if (dma_engine->dmab->area)
2569 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2570 kfree(dma_engine->dmab);
2571 kfree(dma_engine);
2572
2573 return status;
2574 }
2575
2576 /*
2577 * CA0132 DSP download stuffs.
2578 */
2579 static void dspload_post_setup(struct hda_codec *codec)
2580 {
2581 codec_dbg(codec, "---- dspload_post_setup ------\n");
2582
2583 /*set DSP speaker to 2.0 configuration*/
2584 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2585 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2586
2587 /*update write pointer*/
2588 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2589 }
2590
2591 /**
2592 * dspload_image - Download DSP from a DSP Image Fast Load structure.
2593 *
2594 * @codec: the HDA codec
2595 * @fls: pointer to a fast load image
2596 * @ovly: TRUE if overlay format is required
2597 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2598 * no relocation
2599 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2600 * @router_chans: number of audio router channels to be allocated (0 means use
2601 * internal defaults; max is 32)
2602 *
2603 * Download DSP from a DSP Image Fast Load structure. This structure is a
2604 * linear, non-constant sized element array of structures, each of which
2605 * contain the count of the data to be loaded, the data itself, and the
2606 * corresponding starting chip address of the starting data location.
2607 * Returns zero or a negative error code.
2608 */
2609 static int dspload_image(struct hda_codec *codec,
2610 const struct dsp_image_seg *fls,
2611 bool ovly,
2612 unsigned int reloc,
2613 bool autostart,
2614 int router_chans)
2615 {
2616 int status = 0;
2617 unsigned int sample_rate;
2618 unsigned short channels;
2619
2620 codec_dbg(codec, "---- dspload_image begin ------\n");
2621 if (router_chans == 0) {
2622 if (!ovly)
2623 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2624 else
2625 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2626 }
2627
2628 sample_rate = 48000;
2629 channels = (unsigned short)router_chans;
2630
2631 while (channels > 16) {
2632 sample_rate *= 2;
2633 channels /= 2;
2634 }
2635
2636 do {
2637 codec_dbg(codec, "Ready to program DMA\n");
2638 if (!ovly)
2639 status = dsp_reset(codec);
2640
2641 if (status < 0)
2642 break;
2643
2644 codec_dbg(codec, "dsp_reset() complete\n");
2645 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2646 ovly);
2647
2648 if (status < 0)
2649 break;
2650
2651 codec_dbg(codec, "dspxfr_image() complete\n");
2652 if (autostart && !ovly) {
2653 dspload_post_setup(codec);
2654 status = dsp_set_run_state(codec);
2655 }
2656
2657 codec_dbg(codec, "LOAD FINISHED\n");
2658 } while (0);
2659
2660 return status;
2661 }
2662
2663 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2664 static bool dspload_is_loaded(struct hda_codec *codec)
2665 {
2666 unsigned int data = 0;
2667 int status = 0;
2668
2669 status = chipio_read(codec, 0x40004, &data);
2670 if ((status < 0) || (data != 1))
2671 return false;
2672
2673 return true;
2674 }
2675 #else
2676 #define dspload_is_loaded(codec) false
2677 #endif
2678
2679 static bool dspload_wait_loaded(struct hda_codec *codec)
2680 {
2681 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2682
2683 do {
2684 if (dspload_is_loaded(codec)) {
2685 codec_info(codec, "ca0132 DSP downloaded and running\n");
2686 return true;
2687 }
2688 msleep(20);
2689 } while (time_before(jiffies, timeout));
2690
2691 codec_err(codec, "ca0132 failed to download DSP\n");
2692 return false;
2693 }
2694
2695 /*
2696 * PCM callbacks
2697 */
2698 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2699 struct hda_codec *codec,
2700 unsigned int stream_tag,
2701 unsigned int format,
2702 struct snd_pcm_substream *substream)
2703 {
2704 struct ca0132_spec *spec = codec->spec;
2705
2706 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2707
2708 return 0;
2709 }
2710
2711 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2712 struct hda_codec *codec,
2713 struct snd_pcm_substream *substream)
2714 {
2715 struct ca0132_spec *spec = codec->spec;
2716
2717 if (spec->dsp_state == DSP_DOWNLOADING)
2718 return 0;
2719
2720 /*If Playback effects are on, allow stream some time to flush
2721 *effects tail*/
2722 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2723 msleep(50);
2724
2725 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2726
2727 return 0;
2728 }
2729
2730 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2731 struct hda_codec *codec,
2732 struct snd_pcm_substream *substream)
2733 {
2734 struct ca0132_spec *spec = codec->spec;
2735 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2736 struct snd_pcm_runtime *runtime = substream->runtime;
2737
2738 if (spec->dsp_state != DSP_DOWNLOADED)
2739 return 0;
2740
2741 /* Add latency if playback enhancement and either effect is enabled. */
2742 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2743 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2744 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2745 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2746 }
2747
2748 /* Applying Speaker EQ adds latency as well. */
2749 if (spec->cur_out_type == SPEAKER_OUT)
2750 latency += DSP_SPEAKER_OUT_LATENCY;
2751
2752 return (latency * runtime->rate) / 1000;
2753 }
2754
2755 /*
2756 * Digital out
2757 */
2758 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2759 struct hda_codec *codec,
2760 struct snd_pcm_substream *substream)
2761 {
2762 struct ca0132_spec *spec = codec->spec;
2763 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2764 }
2765
2766 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2767 struct hda_codec *codec,
2768 unsigned int stream_tag,
2769 unsigned int format,
2770 struct snd_pcm_substream *substream)
2771 {
2772 struct ca0132_spec *spec = codec->spec;
2773 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2774 stream_tag, format, substream);
2775 }
2776
2777 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2778 struct hda_codec *codec,
2779 struct snd_pcm_substream *substream)
2780 {
2781 struct ca0132_spec *spec = codec->spec;
2782 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2783 }
2784
2785 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2786 struct hda_codec *codec,
2787 struct snd_pcm_substream *substream)
2788 {
2789 struct ca0132_spec *spec = codec->spec;
2790 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2791 }
2792
2793 /*
2794 * Analog capture
2795 */
2796 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2797 struct hda_codec *codec,
2798 unsigned int stream_tag,
2799 unsigned int format,
2800 struct snd_pcm_substream *substream)
2801 {
2802 snd_hda_codec_setup_stream(codec, hinfo->nid,
2803 stream_tag, 0, format);
2804
2805 return 0;
2806 }
2807
2808 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2809 struct hda_codec *codec,
2810 struct snd_pcm_substream *substream)
2811 {
2812 struct ca0132_spec *spec = codec->spec;
2813
2814 if (spec->dsp_state == DSP_DOWNLOADING)
2815 return 0;
2816
2817 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2818 return 0;
2819 }
2820
2821 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2822 struct hda_codec *codec,
2823 struct snd_pcm_substream *substream)
2824 {
2825 struct ca0132_spec *spec = codec->spec;
2826 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2827 struct snd_pcm_runtime *runtime = substream->runtime;
2828
2829 if (spec->dsp_state != DSP_DOWNLOADED)
2830 return 0;
2831
2832 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2833 latency += DSP_CRYSTAL_VOICE_LATENCY;
2834
2835 return (latency * runtime->rate) / 1000;
2836 }
2837
2838 /*
2839 * Controls stuffs.
2840 */
2841
2842 /*
2843 * Mixer controls helpers.
2844 */
2845 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2846 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2847 .name = xname, \
2848 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2849 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2850 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2851 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2852 .info = ca0132_volume_info, \
2853 .get = ca0132_volume_get, \
2854 .put = ca0132_volume_put, \
2855 .tlv = { .c = ca0132_volume_tlv }, \
2856 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2857
2858 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2859 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2860 .name = xname, \
2861 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2862 .info = snd_hda_mixer_amp_switch_info, \
2863 .get = ca0132_switch_get, \
2864 .put = ca0132_switch_put, \
2865 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2866
2867 /* stereo */
2868 #define CA0132_CODEC_VOL(xname, nid, dir) \
2869 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2870 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2871 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2872
2873 /* The followings are for tuning of products */
2874 #ifdef ENABLE_TUNING_CONTROLS
2875
2876 static unsigned int voice_focus_vals_lookup[] = {
2877 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2878 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2879 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2880 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2881 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2882 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2883 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2884 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2885 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2886 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2887 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2888 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2889 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2890 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2891 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2892 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2893 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2894 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2895 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2896 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2897 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2898 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2899 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2900 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2901 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2902 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2903 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2904 };
2905
2906 static unsigned int mic_svm_vals_lookup[] = {
2907 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2908 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2909 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2910 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2911 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2912 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2913 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2914 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2915 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2916 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2917 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2918 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2919 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2920 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2921 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2922 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2923 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2924 };
2925
2926 static unsigned int equalizer_vals_lookup[] = {
2927 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2928 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2929 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2930 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2931 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2932 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2933 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2934 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2935 0x41C00000
2936 };
2937
2938 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2939 unsigned int *lookup, int idx)
2940 {
2941 int i = 0;
2942
2943 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2944 if (nid == ca0132_tuning_ctls[i].nid)
2945 break;
2946
2947 snd_hda_power_up(codec);
2948 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2949 ca0132_tuning_ctls[i].req,
2950 &(lookup[idx]), sizeof(unsigned int));
2951 snd_hda_power_down(codec);
2952
2953 return 1;
2954 }
2955
2956 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2957 struct snd_ctl_elem_value *ucontrol)
2958 {
2959 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2960 struct ca0132_spec *spec = codec->spec;
2961 hda_nid_t nid = get_amp_nid(kcontrol);
2962 long *valp = ucontrol->value.integer.value;
2963 int idx = nid - TUNING_CTL_START_NID;
2964
2965 *valp = spec->cur_ctl_vals[idx];
2966 return 0;
2967 }
2968
2969 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2970 struct snd_ctl_elem_info *uinfo)
2971 {
2972 int chs = get_amp_channels(kcontrol);
2973 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2974 uinfo->count = chs == 3 ? 2 : 1;
2975 uinfo->value.integer.min = 20;
2976 uinfo->value.integer.max = 180;
2977 uinfo->value.integer.step = 1;
2978
2979 return 0;
2980 }
2981
2982 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2983 struct snd_ctl_elem_value *ucontrol)
2984 {
2985 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2986 struct ca0132_spec *spec = codec->spec;
2987 hda_nid_t nid = get_amp_nid(kcontrol);
2988 long *valp = ucontrol->value.integer.value;
2989 int idx;
2990
2991 idx = nid - TUNING_CTL_START_NID;
2992 /* any change? */
2993 if (spec->cur_ctl_vals[idx] == *valp)
2994 return 0;
2995
2996 spec->cur_ctl_vals[idx] = *valp;
2997
2998 idx = *valp - 20;
2999 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3000
3001 return 1;
3002 }
3003
3004 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3005 struct snd_ctl_elem_info *uinfo)
3006 {
3007 int chs = get_amp_channels(kcontrol);
3008 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3009 uinfo->count = chs == 3 ? 2 : 1;
3010 uinfo->value.integer.min = 0;
3011 uinfo->value.integer.max = 100;
3012 uinfo->value.integer.step = 1;
3013
3014 return 0;
3015 }
3016
3017 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3018 struct snd_ctl_elem_value *ucontrol)
3019 {
3020 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3021 struct ca0132_spec *spec = codec->spec;
3022 hda_nid_t nid = get_amp_nid(kcontrol);
3023 long *valp = ucontrol->value.integer.value;
3024 int idx;
3025
3026 idx = nid - TUNING_CTL_START_NID;
3027 /* any change? */
3028 if (spec->cur_ctl_vals[idx] == *valp)
3029 return 0;
3030
3031 spec->cur_ctl_vals[idx] = *valp;
3032
3033 idx = *valp;
3034 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3035
3036 return 0;
3037 }
3038
3039 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3040 struct snd_ctl_elem_info *uinfo)
3041 {
3042 int chs = get_amp_channels(kcontrol);
3043 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3044 uinfo->count = chs == 3 ? 2 : 1;
3045 uinfo->value.integer.min = 0;
3046 uinfo->value.integer.max = 48;
3047 uinfo->value.integer.step = 1;
3048
3049 return 0;
3050 }
3051
3052 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3053 struct snd_ctl_elem_value *ucontrol)
3054 {
3055 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3056 struct ca0132_spec *spec = codec->spec;
3057 hda_nid_t nid = get_amp_nid(kcontrol);
3058 long *valp = ucontrol->value.integer.value;
3059 int idx;
3060
3061 idx = nid - TUNING_CTL_START_NID;
3062 /* any change? */
3063 if (spec->cur_ctl_vals[idx] == *valp)
3064 return 0;
3065
3066 spec->cur_ctl_vals[idx] = *valp;
3067
3068 idx = *valp;
3069 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3070
3071 return 1;
3072 }
3073
3074 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3075 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3076
3077 static int add_tuning_control(struct hda_codec *codec,
3078 hda_nid_t pnid, hda_nid_t nid,
3079 const char *name, int dir)
3080 {
3081 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3082 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3083 struct snd_kcontrol_new knew =
3084 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3085
3086 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3087 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3088 knew.tlv.c = 0;
3089 knew.tlv.p = 0;
3090 switch (pnid) {
3091 case VOICE_FOCUS:
3092 knew.info = voice_focus_ctl_info;
3093 knew.get = tuning_ctl_get;
3094 knew.put = voice_focus_ctl_put;
3095 knew.tlv.p = voice_focus_db_scale;
3096 break;
3097 case MIC_SVM:
3098 knew.info = mic_svm_ctl_info;
3099 knew.get = tuning_ctl_get;
3100 knew.put = mic_svm_ctl_put;
3101 break;
3102 case EQUALIZER:
3103 knew.info = equalizer_ctl_info;
3104 knew.get = tuning_ctl_get;
3105 knew.put = equalizer_ctl_put;
3106 knew.tlv.p = eq_db_scale;
3107 break;
3108 default:
3109 return 0;
3110 }
3111 knew.private_value =
3112 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3113 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3114 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3115 }
3116
3117 static int add_tuning_ctls(struct hda_codec *codec)
3118 {
3119 int i;
3120 int err;
3121
3122 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3123 err = add_tuning_control(codec,
3124 ca0132_tuning_ctls[i].parent_nid,
3125 ca0132_tuning_ctls[i].nid,
3126 ca0132_tuning_ctls[i].name,
3127 ca0132_tuning_ctls[i].direct);
3128 if (err < 0)
3129 return err;
3130 }
3131
3132 return 0;
3133 }
3134
3135 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3136 {
3137 struct ca0132_spec *spec = codec->spec;
3138 int i;
3139
3140 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3141 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3142 /* SVM level defaults to 0.74. */
3143 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3144
3145 /* EQ defaults to 0dB. */
3146 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3147 spec->cur_ctl_vals[i] = 24;
3148 }
3149 #endif /*ENABLE_TUNING_CONTROLS*/
3150
3151 /*
3152 * Select the active output.
3153 * If autodetect is enabled, output will be selected based on jack detection.
3154 * If jack inserted, headphone will be selected, else built-in speakers
3155 * If autodetect is disabled, output will be selected based on selection.
3156 */
3157 static int ca0132_select_out(struct hda_codec *codec)
3158 {
3159 struct ca0132_spec *spec = codec->spec;
3160 unsigned int pin_ctl;
3161 int jack_present;
3162 int auto_jack;
3163 unsigned int tmp;
3164 int err;
3165
3166 codec_dbg(codec, "ca0132_select_out\n");
3167
3168 snd_hda_power_up_pm(codec);
3169
3170 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3171
3172 if (auto_jack)
3173 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3174 else
3175 jack_present =
3176 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3177
3178 if (jack_present)
3179 spec->cur_out_type = HEADPHONE_OUT;
3180 else
3181 spec->cur_out_type = SPEAKER_OUT;
3182
3183 if (spec->cur_out_type == SPEAKER_OUT) {
3184 codec_dbg(codec, "ca0132_select_out speaker\n");
3185 /*speaker out config*/
3186 tmp = FLOAT_ONE;
3187 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3188 if (err < 0)
3189 goto exit;
3190 /*enable speaker EQ*/
3191 tmp = FLOAT_ONE;
3192 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3193 if (err < 0)
3194 goto exit;
3195
3196 /* Setup EAPD */
3197 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3198 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3199 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3200 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3201 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3202 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3203 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3204 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3205
3206 /* disable headphone node */
3207 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3208 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3209 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3210 pin_ctl & ~PIN_HP);
3211 /* enable speaker node */
3212 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3213 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3214 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3215 pin_ctl | PIN_OUT);
3216 } else {
3217 codec_dbg(codec, "ca0132_select_out hp\n");
3218 /*headphone out config*/
3219 tmp = FLOAT_ZERO;
3220 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3221 if (err < 0)
3222 goto exit;
3223 /*disable speaker EQ*/
3224 tmp = FLOAT_ZERO;
3225 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3226 if (err < 0)
3227 goto exit;
3228
3229 /* Setup EAPD */
3230 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3231 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3232 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3233 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3234 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3235 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3236 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3237 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3238
3239 /* disable speaker*/
3240 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3241 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3242 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3243 pin_ctl & ~PIN_HP);
3244 /* enable headphone*/
3245 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3246 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3247 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3248 pin_ctl | PIN_HP);
3249 }
3250
3251 exit:
3252 snd_hda_power_down_pm(codec);
3253
3254 return err < 0 ? err : 0;
3255 }
3256
3257 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3258 {
3259 struct ca0132_spec *spec = container_of(
3260 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3261 struct hda_jack_tbl *jack;
3262
3263 ca0132_select_out(spec->codec);
3264 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
3265 if (jack) {
3266 jack->block_report = 0;
3267 snd_hda_jack_report_sync(spec->codec);
3268 }
3269 }
3270
3271 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3272 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3273 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3274
3275 /*
3276 * Select the active VIP source
3277 */
3278 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3279 {
3280 struct ca0132_spec *spec = codec->spec;
3281 unsigned int tmp;
3282
3283 if (spec->dsp_state != DSP_DOWNLOADED)
3284 return 0;
3285
3286 /* if CrystalVoice if off, vipsource should be 0 */
3287 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3288 (val == 0)) {
3289 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3290 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3291 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3292 if (spec->cur_mic_type == DIGITAL_MIC)
3293 tmp = FLOAT_TWO;
3294 else
3295 tmp = FLOAT_ONE;
3296 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3297 tmp = FLOAT_ZERO;
3298 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3299 } else {
3300 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3301 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3302 if (spec->cur_mic_type == DIGITAL_MIC)
3303 tmp = FLOAT_TWO;
3304 else
3305 tmp = FLOAT_ONE;
3306 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3307 tmp = FLOAT_ONE;
3308 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3309 msleep(20);
3310 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3311 }
3312
3313 return 1;
3314 }
3315
3316 /*
3317 * Select the active microphone.
3318 * If autodetect is enabled, mic will be selected based on jack detection.
3319 * If jack inserted, ext.mic will be selected, else built-in mic
3320 * If autodetect is disabled, mic will be selected based on selection.
3321 */
3322 static int ca0132_select_mic(struct hda_codec *codec)
3323 {
3324 struct ca0132_spec *spec = codec->spec;
3325 int jack_present;
3326 int auto_jack;
3327
3328 codec_dbg(codec, "ca0132_select_mic\n");
3329
3330 snd_hda_power_up_pm(codec);
3331
3332 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3333
3334 if (auto_jack)
3335 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
3336 else
3337 jack_present =
3338 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3339
3340 if (jack_present)
3341 spec->cur_mic_type = LINE_MIC_IN;
3342 else
3343 spec->cur_mic_type = DIGITAL_MIC;
3344
3345 if (spec->cur_mic_type == DIGITAL_MIC) {
3346 /* enable digital Mic */
3347 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3348 ca0132_set_dmic(codec, 1);
3349 ca0132_mic_boost_set(codec, 0);
3350 /* set voice focus */
3351 ca0132_effects_set(codec, VOICE_FOCUS,
3352 spec->effects_switch
3353 [VOICE_FOCUS - EFFECT_START_NID]);
3354 } else {
3355 /* disable digital Mic */
3356 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3357 ca0132_set_dmic(codec, 0);
3358 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3359 /* disable voice focus */
3360 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3361 }
3362
3363 snd_hda_power_down_pm(codec);
3364
3365 return 0;
3366 }
3367
3368 /*
3369 * Check if VNODE settings take effect immediately.
3370 */
3371 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3372 hda_nid_t vnid,
3373 hda_nid_t *shared_nid)
3374 {
3375 struct ca0132_spec *spec = codec->spec;
3376 hda_nid_t nid;
3377
3378 switch (vnid) {
3379 case VNID_SPK:
3380 nid = spec->shared_out_nid;
3381 break;
3382 case VNID_MIC:
3383 nid = spec->shared_mic_nid;
3384 break;
3385 default:
3386 return false;
3387 }
3388
3389 if (shared_nid)
3390 *shared_nid = nid;
3391
3392 return true;
3393 }
3394
3395 /*
3396 * The following functions are control change helpers.
3397 * They return 0 if no changed. Return 1 if changed.
3398 */
3399 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3400 {
3401 struct ca0132_spec *spec = codec->spec;
3402 unsigned int tmp;
3403
3404 /* based on CrystalVoice state to enable VoiceFX. */
3405 if (enable) {
3406 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3407 FLOAT_ONE : FLOAT_ZERO;
3408 } else {
3409 tmp = FLOAT_ZERO;
3410 }
3411
3412 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3413 ca0132_voicefx.reqs[0], tmp);
3414
3415 return 1;
3416 }
3417
3418 /*
3419 * Set the effects parameters
3420 */
3421 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3422 {
3423 struct ca0132_spec *spec = codec->spec;
3424 unsigned int on;
3425 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3426 int err = 0;
3427 int idx = nid - EFFECT_START_NID;
3428
3429 if ((idx < 0) || (idx >= num_fx))
3430 return 0; /* no changed */
3431
3432 /* for out effect, qualify with PE */
3433 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3434 /* if PE if off, turn off out effects. */
3435 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3436 val = 0;
3437 }
3438
3439 /* for in effect, qualify with CrystalVoice */
3440 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3441 /* if CrystalVoice if off, turn off in effects. */
3442 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3443 val = 0;
3444
3445 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3446 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3447 val = 0;
3448 }
3449
3450 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3451 nid, val);
3452
3453 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3454 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3455 ca0132_effects[idx].reqs[0], on);
3456
3457 if (err < 0)
3458 return 0; /* no changed */
3459
3460 return 1;
3461 }
3462
3463 /*
3464 * Turn on/off Playback Enhancements
3465 */
3466 static int ca0132_pe_switch_set(struct hda_codec *codec)
3467 {
3468 struct ca0132_spec *spec = codec->spec;
3469 hda_nid_t nid;
3470 int i, ret = 0;
3471
3472 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
3473 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3474
3475 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3476 nid = OUT_EFFECT_START_NID;
3477 /* PE affects all out effects */
3478 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3479 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3480
3481 return ret;
3482 }
3483
3484 /* Check if Mic1 is streaming, if so, stop streaming */
3485 static int stop_mic1(struct hda_codec *codec)
3486 {
3487 struct ca0132_spec *spec = codec->spec;
3488 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3489 AC_VERB_GET_CONV, 0);
3490 if (oldval != 0)
3491 snd_hda_codec_write(codec, spec->adcs[0], 0,
3492 AC_VERB_SET_CHANNEL_STREAMID,
3493 0);
3494 return oldval;
3495 }
3496
3497 /* Resume Mic1 streaming if it was stopped. */
3498 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3499 {
3500 struct ca0132_spec *spec = codec->spec;
3501 /* Restore the previous stream and channel */
3502 if (oldval != 0)
3503 snd_hda_codec_write(codec, spec->adcs[0], 0,
3504 AC_VERB_SET_CHANNEL_STREAMID,
3505 oldval);
3506 }
3507
3508 /*
3509 * Turn on/off CrystalVoice
3510 */
3511 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3512 {
3513 struct ca0132_spec *spec = codec->spec;
3514 hda_nid_t nid;
3515 int i, ret = 0;
3516 unsigned int oldval;
3517
3518 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
3519 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3520
3521 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3522 nid = IN_EFFECT_START_NID;
3523 /* CrystalVoice affects all in effects */
3524 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3525 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3526
3527 /* including VoiceFX */
3528 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3529
3530 /* set correct vipsource */
3531 oldval = stop_mic1(codec);
3532 ret |= ca0132_set_vipsource(codec, 1);
3533 resume_mic1(codec, oldval);
3534 return ret;
3535 }
3536
3537 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3538 {
3539 struct ca0132_spec *spec = codec->spec;
3540 int ret = 0;
3541
3542 if (val) /* on */
3543 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3544 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3545 else /* off */
3546 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3547 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3548
3549 return ret;
3550 }
3551
3552 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3553 struct snd_ctl_elem_value *ucontrol)
3554 {
3555 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3556 hda_nid_t nid = get_amp_nid(kcontrol);
3557 hda_nid_t shared_nid = 0;
3558 bool effective;
3559 int ret = 0;
3560 struct ca0132_spec *spec = codec->spec;
3561 int auto_jack;
3562
3563 if (nid == VNID_HP_SEL) {
3564 auto_jack =
3565 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3566 if (!auto_jack)
3567 ca0132_select_out(codec);
3568 return 1;
3569 }
3570
3571 if (nid == VNID_AMIC1_SEL) {
3572 auto_jack =
3573 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3574 if (!auto_jack)
3575 ca0132_select_mic(codec);
3576 return 1;
3577 }
3578
3579 if (nid == VNID_HP_ASEL) {
3580 ca0132_select_out(codec);
3581 return 1;
3582 }
3583
3584 if (nid == VNID_AMIC1_ASEL) {
3585 ca0132_select_mic(codec);
3586 return 1;
3587 }
3588
3589 /* if effective conditions, then update hw immediately. */
3590 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3591 if (effective) {
3592 int dir = get_amp_direction(kcontrol);
3593 int ch = get_amp_channels(kcontrol);
3594 unsigned long pval;
3595
3596 mutex_lock(&codec->control_mutex);
3597 pval = kcontrol->private_value;
3598 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3599 0, dir);
3600 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3601 kcontrol->private_value = pval;
3602 mutex_unlock(&codec->control_mutex);
3603 }
3604
3605 return ret;
3606 }
3607 /* End of control change helpers. */
3608
3609 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3610 struct snd_ctl_elem_info *uinfo)
3611 {
3612 unsigned int items = sizeof(ca0132_voicefx_presets)
3613 / sizeof(struct ct_voicefx_preset);
3614
3615 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3616 uinfo->count = 1;
3617 uinfo->value.enumerated.items = items;
3618 if (uinfo->value.enumerated.item >= items)
3619 uinfo->value.enumerated.item = items - 1;
3620 strcpy(uinfo->value.enumerated.name,
3621 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3622 return 0;
3623 }
3624
3625 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3626 struct snd_ctl_elem_value *ucontrol)
3627 {
3628 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3629 struct ca0132_spec *spec = codec->spec;
3630
3631 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3632 return 0;
3633 }
3634
3635 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3636 struct snd_ctl_elem_value *ucontrol)
3637 {
3638 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3639 struct ca0132_spec *spec = codec->spec;
3640 int i, err = 0;
3641 int sel = ucontrol->value.enumerated.item[0];
3642 unsigned int items = sizeof(ca0132_voicefx_presets)
3643 / sizeof(struct ct_voicefx_preset);
3644
3645 if (sel >= items)
3646 return 0;
3647
3648 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
3649 sel, ca0132_voicefx_presets[sel].name);
3650
3651 /*
3652 * Idx 0 is default.
3653 * Default needs to qualify with CrystalVoice state.
3654 */
3655 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3656 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3657 ca0132_voicefx.reqs[i],
3658 ca0132_voicefx_presets[sel].vals[i]);
3659 if (err < 0)
3660 break;
3661 }
3662
3663 if (err >= 0) {
3664 spec->voicefx_val = sel;
3665 /* enable voice fx */
3666 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3667 }
3668
3669 return 1;
3670 }
3671
3672 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3673 struct snd_ctl_elem_value *ucontrol)
3674 {
3675 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3676 struct ca0132_spec *spec = codec->spec;
3677 hda_nid_t nid = get_amp_nid(kcontrol);
3678 int ch = get_amp_channels(kcontrol);
3679 long *valp = ucontrol->value.integer.value;
3680
3681 /* vnode */
3682 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3683 if (ch & 1) {
3684 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3685 valp++;
3686 }
3687 if (ch & 2) {
3688 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3689 valp++;
3690 }
3691 return 0;
3692 }
3693
3694 /* effects, include PE and CrystalVoice */
3695 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3696 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3697 return 0;
3698 }
3699
3700 /* mic boost */
3701 if (nid == spec->input_pins[0]) {
3702 *valp = spec->cur_mic_boost;
3703 return 0;
3704 }
3705
3706 return 0;
3707 }
3708
3709 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3710 struct snd_ctl_elem_value *ucontrol)
3711 {
3712 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3713 struct ca0132_spec *spec = codec->spec;
3714 hda_nid_t nid = get_amp_nid(kcontrol);
3715 int ch = get_amp_channels(kcontrol);
3716 long *valp = ucontrol->value.integer.value;
3717 int changed = 1;
3718
3719 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
3720 nid, *valp);
3721
3722 snd_hda_power_up(codec);
3723 /* vnode */
3724 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3725 if (ch & 1) {
3726 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3727 valp++;
3728 }
3729 if (ch & 2) {
3730 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3731 valp++;
3732 }
3733 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3734 goto exit;
3735 }
3736
3737 /* PE */
3738 if (nid == PLAY_ENHANCEMENT) {
3739 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3740 changed = ca0132_pe_switch_set(codec);
3741 goto exit;
3742 }
3743
3744 /* CrystalVoice */
3745 if (nid == CRYSTAL_VOICE) {
3746 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3747 changed = ca0132_cvoice_switch_set(codec);
3748 goto exit;
3749 }
3750
3751 /* out and in effects */
3752 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3753 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3754 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3755 changed = ca0132_effects_set(codec, nid, *valp);
3756 goto exit;
3757 }
3758
3759 /* mic boost */
3760 if (nid == spec->input_pins[0]) {
3761 spec->cur_mic_boost = *valp;
3762
3763 /* Mic boost does not apply to Digital Mic */
3764 if (spec->cur_mic_type != DIGITAL_MIC)
3765 changed = ca0132_mic_boost_set(codec, *valp);
3766 goto exit;
3767 }
3768
3769 exit:
3770 snd_hda_power_down(codec);
3771 return changed;
3772 }
3773
3774 /*
3775 * Volume related
3776 */
3777 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3778 struct snd_ctl_elem_info *uinfo)
3779 {
3780 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3781 struct ca0132_spec *spec = codec->spec;
3782 hda_nid_t nid = get_amp_nid(kcontrol);
3783 int ch = get_amp_channels(kcontrol);
3784 int dir = get_amp_direction(kcontrol);
3785 unsigned long pval;
3786 int err;
3787
3788 switch (nid) {
3789 case VNID_SPK:
3790 /* follow shared_out info */
3791 nid = spec->shared_out_nid;
3792 mutex_lock(&codec->control_mutex);
3793 pval = kcontrol->private_value;
3794 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3795 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3796 kcontrol->private_value = pval;
3797 mutex_unlock(&codec->control_mutex);
3798 break;
3799 case VNID_MIC:
3800 /* follow shared_mic info */
3801 nid = spec->shared_mic_nid;
3802 mutex_lock(&codec->control_mutex);
3803 pval = kcontrol->private_value;
3804 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3805 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3806 kcontrol->private_value = pval;
3807 mutex_unlock(&codec->control_mutex);
3808 break;
3809 default:
3810 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3811 }
3812 return err;
3813 }
3814
3815 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3816 struct snd_ctl_elem_value *ucontrol)
3817 {
3818 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3819 struct ca0132_spec *spec = codec->spec;
3820 hda_nid_t nid = get_amp_nid(kcontrol);
3821 int ch = get_amp_channels(kcontrol);
3822 long *valp = ucontrol->value.integer.value;
3823
3824 /* store the left and right volume */
3825 if (ch & 1) {
3826 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3827 valp++;
3828 }
3829 if (ch & 2) {
3830 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3831 valp++;
3832 }
3833 return 0;
3834 }
3835
3836 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3837 struct snd_ctl_elem_value *ucontrol)
3838 {
3839 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3840 struct ca0132_spec *spec = codec->spec;
3841 hda_nid_t nid = get_amp_nid(kcontrol);
3842 int ch = get_amp_channels(kcontrol);
3843 long *valp = ucontrol->value.integer.value;
3844 hda_nid_t shared_nid = 0;
3845 bool effective;
3846 int changed = 1;
3847
3848 /* store the left and right volume */
3849 if (ch & 1) {
3850 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3851 valp++;
3852 }
3853 if (ch & 2) {
3854 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3855 valp++;
3856 }
3857
3858 /* if effective conditions, then update hw immediately. */
3859 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3860 if (effective) {
3861 int dir = get_amp_direction(kcontrol);
3862 unsigned long pval;
3863
3864 snd_hda_power_up(codec);
3865 mutex_lock(&codec->control_mutex);
3866 pval = kcontrol->private_value;
3867 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3868 0, dir);
3869 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3870 kcontrol->private_value = pval;
3871 mutex_unlock(&codec->control_mutex);
3872 snd_hda_power_down(codec);
3873 }
3874
3875 return changed;
3876 }
3877
3878 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3879 unsigned int size, unsigned int __user *tlv)
3880 {
3881 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3882 struct ca0132_spec *spec = codec->spec;
3883 hda_nid_t nid = get_amp_nid(kcontrol);
3884 int ch = get_amp_channels(kcontrol);
3885 int dir = get_amp_direction(kcontrol);
3886 unsigned long pval;
3887 int err;
3888
3889 switch (nid) {
3890 case VNID_SPK:
3891 /* follow shared_out tlv */
3892 nid = spec->shared_out_nid;
3893 mutex_lock(&codec->control_mutex);
3894 pval = kcontrol->private_value;
3895 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3896 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3897 kcontrol->private_value = pval;
3898 mutex_unlock(&codec->control_mutex);
3899 break;
3900 case VNID_MIC:
3901 /* follow shared_mic tlv */
3902 nid = spec->shared_mic_nid;
3903 mutex_lock(&codec->control_mutex);
3904 pval = kcontrol->private_value;
3905 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3906 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3907 kcontrol->private_value = pval;
3908 mutex_unlock(&codec->control_mutex);
3909 break;
3910 default:
3911 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3912 }
3913 return err;
3914 }
3915
3916 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3917 const char *pfx, int dir)
3918 {
3919 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3920 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3921 struct snd_kcontrol_new knew =
3922 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3923 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3924 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3925 }
3926
3927 static int add_voicefx(struct hda_codec *codec)
3928 {
3929 struct snd_kcontrol_new knew =
3930 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3931 VOICEFX, 1, 0, HDA_INPUT);
3932 knew.info = ca0132_voicefx_info;
3933 knew.get = ca0132_voicefx_get;
3934 knew.put = ca0132_voicefx_put;
3935 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3936 }
3937
3938 /*
3939 * When changing Node IDs for Mixer Controls below, make sure to update
3940 * Node IDs in ca0132_config() as well.
3941 */
3942 static struct snd_kcontrol_new ca0132_mixer[] = {
3943 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3944 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3945 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3946 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3947 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3948 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3949 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3950 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3951 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3952 0x12, 1, HDA_INPUT),
3953 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3954 VNID_HP_SEL, 1, HDA_OUTPUT),
3955 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3956 VNID_AMIC1_SEL, 1, HDA_INPUT),
3957 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3958 VNID_HP_ASEL, 1, HDA_OUTPUT),
3959 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3960 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3961 { } /* end */
3962 };
3963
3964 static int ca0132_build_controls(struct hda_codec *codec)
3965 {
3966 struct ca0132_spec *spec = codec->spec;
3967 int i, num_fx;
3968 int err = 0;
3969
3970 /* Add Mixer controls */
3971 for (i = 0; i < spec->num_mixers; i++) {
3972 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3973 if (err < 0)
3974 return err;
3975 }
3976
3977 /* Add in and out effects controls.
3978 * VoiceFX, PE and CrystalVoice are added separately.
3979 */
3980 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3981 for (i = 0; i < num_fx; i++) {
3982 err = add_fx_switch(codec, ca0132_effects[i].nid,
3983 ca0132_effects[i].name,
3984 ca0132_effects[i].direct);
3985 if (err < 0)
3986 return err;
3987 }
3988
3989 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3990 if (err < 0)
3991 return err;
3992
3993 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3994 if (err < 0)
3995 return err;
3996
3997 add_voicefx(codec);
3998
3999 #ifdef ENABLE_TUNING_CONTROLS
4000 add_tuning_ctls(codec);
4001 #endif
4002
4003 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4004 if (err < 0)
4005 return err;
4006
4007 if (spec->dig_out) {
4008 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4009 spec->dig_out);
4010 if (err < 0)
4011 return err;
4012 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4013 if (err < 0)
4014 return err;
4015 /* spec->multiout.share_spdif = 1; */
4016 }
4017
4018 if (spec->dig_in) {
4019 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4020 if (err < 0)
4021 return err;
4022 }
4023 return 0;
4024 }
4025
4026 /*
4027 * PCM
4028 */
4029 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
4030 .substreams = 1,
4031 .channels_min = 2,
4032 .channels_max = 6,
4033 .ops = {
4034 .prepare = ca0132_playback_pcm_prepare,
4035 .cleanup = ca0132_playback_pcm_cleanup,
4036 .get_delay = ca0132_playback_pcm_delay,
4037 },
4038 };
4039
4040 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
4041 .substreams = 1,
4042 .channels_min = 2,
4043 .channels_max = 2,
4044 .ops = {
4045 .prepare = ca0132_capture_pcm_prepare,
4046 .cleanup = ca0132_capture_pcm_cleanup,
4047 .get_delay = ca0132_capture_pcm_delay,
4048 },
4049 };
4050
4051 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
4052 .substreams = 1,
4053 .channels_min = 2,
4054 .channels_max = 2,
4055 .ops = {
4056 .open = ca0132_dig_playback_pcm_open,
4057 .close = ca0132_dig_playback_pcm_close,
4058 .prepare = ca0132_dig_playback_pcm_prepare,
4059 .cleanup = ca0132_dig_playback_pcm_cleanup
4060 },
4061 };
4062
4063 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
4064 .substreams = 1,
4065 .channels_min = 2,
4066 .channels_max = 2,
4067 };
4068
4069 static int ca0132_build_pcms(struct hda_codec *codec)
4070 {
4071 struct ca0132_spec *spec = codec->spec;
4072 struct hda_pcm *info;
4073
4074 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4075 if (!info)
4076 return -ENOMEM;
4077 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4078 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4079 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4080 spec->multiout.max_channels;
4081 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4082 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4083 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4084
4085 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4086 if (!info)
4087 return -ENOMEM;
4088 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4089 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4090 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4091
4092 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4093 if (!info)
4094 return -ENOMEM;
4095 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4096 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4097 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4098
4099 if (!spec->dig_out && !spec->dig_in)
4100 return 0;
4101
4102 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4103 if (!info)
4104 return -ENOMEM;
4105 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4106 if (spec->dig_out) {
4107 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4108 ca0132_pcm_digital_playback;
4109 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4110 }
4111 if (spec->dig_in) {
4112 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4113 ca0132_pcm_digital_capture;
4114 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4115 }
4116
4117 return 0;
4118 }
4119
4120 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4121 {
4122 if (pin) {
4123 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4124 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4125 snd_hda_codec_write(codec, pin, 0,
4126 AC_VERB_SET_AMP_GAIN_MUTE,
4127 AMP_OUT_UNMUTE);
4128 }
4129 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4130 snd_hda_codec_write(codec, dac, 0,
4131 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4132 }
4133
4134 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4135 {
4136 if (pin) {
4137 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4138 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4139 snd_hda_codec_write(codec, pin, 0,
4140 AC_VERB_SET_AMP_GAIN_MUTE,
4141 AMP_IN_UNMUTE(0));
4142 }
4143 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4144 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4145 AMP_IN_UNMUTE(0));
4146
4147 /* init to 0 dB and unmute. */
4148 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4149 HDA_AMP_VOLMASK, 0x5a);
4150 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4151 HDA_AMP_MUTE, 0);
4152 }
4153 }
4154
4155 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4156 {
4157 unsigned int caps;
4158
4159 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4160 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4161 snd_hda_override_amp_caps(codec, nid, dir, caps);
4162 }
4163
4164 /*
4165 * Switch between Digital built-in mic and analog mic.
4166 */
4167 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4168 {
4169 struct ca0132_spec *spec = codec->spec;
4170 unsigned int tmp;
4171 u8 val;
4172 unsigned int oldval;
4173
4174 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
4175
4176 oldval = stop_mic1(codec);
4177 ca0132_set_vipsource(codec, 0);
4178 if (enable) {
4179 /* set DMic input as 2-ch */
4180 tmp = FLOAT_TWO;
4181 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4182
4183 val = spec->dmic_ctl;
4184 val |= 0x80;
4185 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4186 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4187
4188 if (!(spec->dmic_ctl & 0x20))
4189 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4190 } else {
4191 /* set AMic input as mono */
4192 tmp = FLOAT_ONE;
4193 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4194
4195 val = spec->dmic_ctl;
4196 /* clear bit7 and bit5 to disable dmic */
4197 val &= 0x5f;
4198 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4199 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4200
4201 if (!(spec->dmic_ctl & 0x20))
4202 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4203 }
4204 ca0132_set_vipsource(codec, 1);
4205 resume_mic1(codec, oldval);
4206 }
4207
4208 /*
4209 * Initialization for Digital Mic.
4210 */
4211 static void ca0132_init_dmic(struct hda_codec *codec)
4212 {
4213 struct ca0132_spec *spec = codec->spec;
4214 u8 val;
4215
4216 /* Setup Digital Mic here, but don't enable.
4217 * Enable based on jack detect.
4218 */
4219
4220 /* MCLK uses MPIO1, set to enable.
4221 * Bit 2-0: MPIO select
4222 * Bit 3: set to disable
4223 * Bit 7-4: reserved
4224 */
4225 val = 0x01;
4226 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4227 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4228
4229 /* Data1 uses MPIO3. Data2 not use
4230 * Bit 2-0: Data1 MPIO select
4231 * Bit 3: set disable Data1
4232 * Bit 6-4: Data2 MPIO select
4233 * Bit 7: set disable Data2
4234 */
4235 val = 0x83;
4236 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4237 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4238
4239 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4240 * Bit 3-0: Channel mask
4241 * Bit 4: set for 48KHz, clear for 32KHz
4242 * Bit 5: mode
4243 * Bit 6: set to select Data2, clear for Data1
4244 * Bit 7: set to enable DMic, clear for AMic
4245 */
4246 val = 0x23;
4247 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4248 spec->dmic_ctl = val;
4249 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4250 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4251 }
4252
4253 /*
4254 * Initialization for Analog Mic 2
4255 */
4256 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4257 {
4258 struct ca0132_spec *spec = codec->spec;
4259
4260 mutex_lock(&spec->chipio_mutex);
4261 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4262 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4263 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4264 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4265 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4266 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4267 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4268 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4269 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4270 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4271 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4272 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4273 mutex_unlock(&spec->chipio_mutex);
4274 }
4275
4276 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4277 {
4278 struct ca0132_spec *spec = codec->spec;
4279 int i;
4280
4281 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
4282 snd_hda_codec_update_widgets(codec);
4283
4284 for (i = 0; i < spec->multiout.num_dacs; i++)
4285 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4286
4287 for (i = 0; i < spec->num_outputs; i++)
4288 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4289
4290 for (i = 0; i < spec->num_inputs; i++) {
4291 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4292 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4293 }
4294 }
4295
4296 /*
4297 * Setup default parameters for DSP
4298 */
4299 static void ca0132_setup_defaults(struct hda_codec *codec)
4300 {
4301 struct ca0132_spec *spec = codec->spec;
4302 unsigned int tmp;
4303 int num_fx;
4304 int idx, i;
4305
4306 if (spec->dsp_state != DSP_DOWNLOADED)
4307 return;
4308
4309 /* out, in effects + voicefx */
4310 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4311 for (idx = 0; idx < num_fx; idx++) {
4312 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4313 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4314 ca0132_effects[idx].reqs[i],
4315 ca0132_effects[idx].def_vals[i]);
4316 }
4317 }
4318
4319 /*remove DSP headroom*/
4320 tmp = FLOAT_ZERO;
4321 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4322
4323 /*set speaker EQ bypass attenuation*/
4324 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4325
4326 /* set AMic1 and AMic2 as mono mic */
4327 tmp = FLOAT_ONE;
4328 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4329 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4330
4331 /* set AMic1 as CrystalVoice input */
4332 tmp = FLOAT_ONE;
4333 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4334
4335 /* set WUH source */
4336 tmp = FLOAT_TWO;
4337 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4338 }
4339
4340 /*
4341 * Initialization of flags in chip
4342 */
4343 static void ca0132_init_flags(struct hda_codec *codec)
4344 {
4345 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4346 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4347 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4348 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4349 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4350 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4351 }
4352
4353 /*
4354 * Initialization of parameters in chip
4355 */
4356 static void ca0132_init_params(struct hda_codec *codec)
4357 {
4358 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4359 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4360 }
4361
4362 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4363 {
4364 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4365 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4366 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4367 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4368 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4369 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4370
4371 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4372 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4373 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4374 }
4375
4376 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4377 {
4378 bool dsp_loaded = false;
4379 const struct dsp_image_seg *dsp_os_image;
4380 const struct firmware *fw_entry;
4381
4382 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
4383 return false;
4384
4385 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4386 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4387 codec_err(codec, "ca0132 DSP load image failed\n");
4388 goto exit_download;
4389 }
4390
4391 dsp_loaded = dspload_wait_loaded(codec);
4392
4393 exit_download:
4394 release_firmware(fw_entry);
4395
4396 return dsp_loaded;
4397 }
4398
4399 static void ca0132_download_dsp(struct hda_codec *codec)
4400 {
4401 struct ca0132_spec *spec = codec->spec;
4402
4403 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4404 return; /* NOP */
4405 #endif
4406
4407 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4408 return; /* don't retry failures */
4409
4410 chipio_enable_clocks(codec);
4411 spec->dsp_state = DSP_DOWNLOADING;
4412 if (!ca0132_download_dsp_images(codec))
4413 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4414 else
4415 spec->dsp_state = DSP_DOWNLOADED;
4416
4417 if (spec->dsp_state == DSP_DOWNLOADED)
4418 ca0132_set_dsp_msr(codec, true);
4419 }
4420
4421 static void ca0132_process_dsp_response(struct hda_codec *codec,
4422 struct hda_jack_callback *callback)
4423 {
4424 struct ca0132_spec *spec = codec->spec;
4425
4426 codec_dbg(codec, "ca0132_process_dsp_response\n");
4427 if (spec->wait_scp) {
4428 if (dspio_get_response_data(codec) >= 0)
4429 spec->wait_scp = 0;
4430 }
4431
4432 dspio_clear_response_queue(codec);
4433 }
4434
4435 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4436 {
4437 struct ca0132_spec *spec = codec->spec;
4438 struct hda_jack_tbl *tbl;
4439
4440 /* Delay enabling the HP amp, to let the mic-detection
4441 * state machine run.
4442 */
4443 cancel_delayed_work_sync(&spec->unsol_hp_work);
4444 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
4445 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4446 if (tbl)
4447 tbl->block_report = 1;
4448 }
4449
4450 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4451 {
4452 ca0132_select_mic(codec);
4453 }
4454
4455 static void ca0132_init_unsol(struct hda_codec *codec)
4456 {
4457 struct ca0132_spec *spec = codec->spec;
4458 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4459 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
4460 amic_callback);
4461 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4462 ca0132_process_dsp_response);
4463 }
4464
4465 /*
4466 * Verbs tables.
4467 */
4468
4469 /* Sends before DSP download. */
4470 static struct hda_verb ca0132_base_init_verbs[] = {
4471 /*enable ct extension*/
4472 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4473 {}
4474 };
4475
4476 /* Send at exit. */
4477 static struct hda_verb ca0132_base_exit_verbs[] = {
4478 /*set afg to D3*/
4479 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4480 /*disable ct extension*/
4481 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4482 {}
4483 };
4484
4485 /* Other verbs tables. Sends after DSP download. */
4486 static struct hda_verb ca0132_init_verbs0[] = {
4487 /* chip init verbs */
4488 {0x15, 0x70D, 0xF0},
4489 {0x15, 0x70E, 0xFE},
4490 {0x15, 0x707, 0x75},
4491 {0x15, 0x707, 0xD3},
4492 {0x15, 0x707, 0x09},
4493 {0x15, 0x707, 0x53},
4494 {0x15, 0x707, 0xD4},
4495 {0x15, 0x707, 0xEF},
4496 {0x15, 0x707, 0x75},
4497 {0x15, 0x707, 0xD3},
4498 {0x15, 0x707, 0x09},
4499 {0x15, 0x707, 0x02},
4500 {0x15, 0x707, 0x37},
4501 {0x15, 0x707, 0x78},
4502 {0x15, 0x53C, 0xCE},
4503 {0x15, 0x575, 0xC9},
4504 {0x15, 0x53D, 0xCE},
4505 {0x15, 0x5B7, 0xC9},
4506 {0x15, 0x70D, 0xE8},
4507 {0x15, 0x70E, 0xFE},
4508 {0x15, 0x707, 0x02},
4509 {0x15, 0x707, 0x68},
4510 {0x15, 0x707, 0x62},
4511 {0x15, 0x53A, 0xCE},
4512 {0x15, 0x546, 0xC9},
4513 {0x15, 0x53B, 0xCE},
4514 {0x15, 0x5E8, 0xC9},
4515 {0x15, 0x717, 0x0D},
4516 {0x15, 0x718, 0x20},
4517 {}
4518 };
4519
4520 static void ca0132_init_chip(struct hda_codec *codec)
4521 {
4522 struct ca0132_spec *spec = codec->spec;
4523 int num_fx;
4524 int i;
4525 unsigned int on;
4526
4527 mutex_init(&spec->chipio_mutex);
4528
4529 spec->cur_out_type = SPEAKER_OUT;
4530 spec->cur_mic_type = DIGITAL_MIC;
4531 spec->cur_mic_boost = 0;
4532
4533 for (i = 0; i < VNODES_COUNT; i++) {
4534 spec->vnode_lvol[i] = 0x5a;
4535 spec->vnode_rvol[i] = 0x5a;
4536 spec->vnode_lswitch[i] = 0;
4537 spec->vnode_rswitch[i] = 0;
4538 }
4539
4540 /*
4541 * Default states for effects are in ca0132_effects[].
4542 */
4543 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4544 for (i = 0; i < num_fx; i++) {
4545 on = (unsigned int)ca0132_effects[i].reqs[0];
4546 spec->effects_switch[i] = on ? 1 : 0;
4547 }
4548
4549 spec->voicefx_val = 0;
4550 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4551 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4552
4553 #ifdef ENABLE_TUNING_CONTROLS
4554 ca0132_init_tuning_defaults(codec);
4555 #endif
4556 }
4557
4558 static void ca0132_exit_chip(struct hda_codec *codec)
4559 {
4560 /* put any chip cleanup stuffs here. */
4561
4562 if (dspload_is_loaded(codec))
4563 dsp_reset(codec);
4564 }
4565
4566 static int ca0132_init(struct hda_codec *codec)
4567 {
4568 struct ca0132_spec *spec = codec->spec;
4569 struct auto_pin_cfg *cfg = &spec->autocfg;
4570 int i;
4571
4572 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4573 spec->dsp_state = DSP_DOWNLOAD_INIT;
4574 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4575
4576 snd_hda_power_up_pm(codec);
4577
4578 ca0132_init_unsol(codec);
4579
4580 ca0132_init_params(codec);
4581 ca0132_init_flags(codec);
4582 snd_hda_sequence_write(codec, spec->base_init_verbs);
4583 ca0132_download_dsp(codec);
4584 ca0132_refresh_widget_caps(codec);
4585 ca0132_setup_defaults(codec);
4586 ca0132_init_analog_mic2(codec);
4587 ca0132_init_dmic(codec);
4588
4589 for (i = 0; i < spec->num_outputs; i++)
4590 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4591
4592 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4593
4594 for (i = 0; i < spec->num_inputs; i++)
4595 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4596
4597 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4598
4599 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4600 snd_hda_sequence_write(codec, spec->spec_init_verbs);
4601
4602 ca0132_select_out(codec);
4603 ca0132_select_mic(codec);
4604
4605 snd_hda_jack_report_sync(codec);
4606
4607 snd_hda_power_down_pm(codec);
4608
4609 return 0;
4610 }
4611
4612 static void ca0132_free(struct hda_codec *codec)
4613 {
4614 struct ca0132_spec *spec = codec->spec;
4615
4616 cancel_delayed_work_sync(&spec->unsol_hp_work);
4617 snd_hda_power_up(codec);
4618 snd_hda_sequence_write(codec, spec->base_exit_verbs);
4619 ca0132_exit_chip(codec);
4620 snd_hda_power_down(codec);
4621 kfree(spec->spec_init_verbs);
4622 kfree(codec->spec);
4623 }
4624
4625 static const struct hda_codec_ops ca0132_patch_ops = {
4626 .build_controls = ca0132_build_controls,
4627 .build_pcms = ca0132_build_pcms,
4628 .init = ca0132_init,
4629 .free = ca0132_free,
4630 .unsol_event = snd_hda_jack_unsol_event,
4631 };
4632
4633 static void ca0132_config(struct hda_codec *codec)
4634 {
4635 struct ca0132_spec *spec = codec->spec;
4636 struct auto_pin_cfg *cfg = &spec->autocfg;
4637
4638 spec->dacs[0] = 0x2;
4639 spec->dacs[1] = 0x3;
4640 spec->dacs[2] = 0x4;
4641
4642 spec->multiout.dac_nids = spec->dacs;
4643 spec->multiout.num_dacs = 3;
4644 spec->multiout.max_channels = 2;
4645
4646 if (spec->quirk == QUIRK_ALIENWARE) {
4647 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
4648 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4649
4650 spec->num_outputs = 2;
4651 spec->out_pins[0] = 0x0b; /* speaker out */
4652 spec->out_pins[1] = 0x0f;
4653 spec->shared_out_nid = 0x2;
4654 spec->unsol_tag_hp = 0x0f;
4655
4656 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4657 spec->adcs[1] = 0x8; /* analog mic2 */
4658 spec->adcs[2] = 0xa; /* what u hear */
4659
4660 spec->num_inputs = 3;
4661 spec->input_pins[0] = 0x12;
4662 spec->input_pins[1] = 0x11;
4663 spec->input_pins[2] = 0x13;
4664 spec->shared_mic_nid = 0x7;
4665 spec->unsol_tag_amic1 = 0x11;
4666 } else {
4667 spec->num_outputs = 2;
4668 spec->out_pins[0] = 0x0b; /* speaker out */
4669 spec->out_pins[1] = 0x10; /* headphone out */
4670 spec->shared_out_nid = 0x2;
4671 spec->unsol_tag_hp = spec->out_pins[1];
4672
4673 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4674 spec->adcs[1] = 0x8; /* analog mic2 */
4675 spec->adcs[2] = 0xa; /* what u hear */
4676
4677 spec->num_inputs = 3;
4678 spec->input_pins[0] = 0x12;
4679 spec->input_pins[1] = 0x11;
4680 spec->input_pins[2] = 0x13;
4681 spec->shared_mic_nid = 0x7;
4682 spec->unsol_tag_amic1 = spec->input_pins[0];
4683
4684 /* SPDIF I/O */
4685 spec->dig_out = 0x05;
4686 spec->multiout.dig_out_nid = spec->dig_out;
4687 cfg->dig_out_pins[0] = 0x0c;
4688 cfg->dig_outs = 1;
4689 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4690 spec->dig_in = 0x09;
4691 cfg->dig_in_pin = 0x0e;
4692 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4693 }
4694 }
4695
4696 static int ca0132_prepare_verbs(struct hda_codec *codec)
4697 {
4698 /* Verbs + terminator (an empty element) */
4699 #define NUM_SPEC_VERBS 4
4700 struct ca0132_spec *spec = codec->spec;
4701
4702 spec->chip_init_verbs = ca0132_init_verbs0;
4703 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4704 if (!spec->spec_init_verbs)
4705 return -ENOMEM;
4706
4707 /* HP jack autodetection */
4708 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4709 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4710 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4711
4712 /* MIC1 jack autodetection */
4713 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4714 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4715 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4716
4717 /* config EAPD */
4718 spec->spec_init_verbs[2].nid = 0x0b;
4719 spec->spec_init_verbs[2].param = 0x78D;
4720 spec->spec_init_verbs[2].verb = 0x00;
4721
4722 /* Previously commented configuration */
4723 /*
4724 spec->spec_init_verbs[3].nid = 0x0b;
4725 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4726 spec->spec_init_verbs[3].verb = 0x02;
4727
4728 spec->spec_init_verbs[4].nid = 0x10;
4729 spec->spec_init_verbs[4].param = 0x78D;
4730 spec->spec_init_verbs[4].verb = 0x02;
4731
4732 spec->spec_init_verbs[5].nid = 0x10;
4733 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4734 spec->spec_init_verbs[5].verb = 0x02;
4735 */
4736
4737 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4738 return 0;
4739 }
4740
4741 static int patch_ca0132(struct hda_codec *codec)
4742 {
4743 struct ca0132_spec *spec;
4744 int err;
4745 const struct snd_pci_quirk *quirk;
4746
4747 codec_dbg(codec, "patch_ca0132\n");
4748
4749 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4750 if (!spec)
4751 return -ENOMEM;
4752 codec->spec = spec;
4753 spec->codec = codec;
4754
4755 codec->patch_ops = ca0132_patch_ops;
4756 codec->pcm_format_first = 1;
4757 codec->no_sticky_stream = 1;
4758
4759 /* Detect codec quirk */
4760 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4761 if (quirk)
4762 spec->quirk = quirk->value;
4763 else
4764 spec->quirk = QUIRK_NONE;
4765
4766 spec->dsp_state = DSP_DOWNLOAD_INIT;
4767 spec->num_mixers = 1;
4768 spec->mixers[0] = ca0132_mixer;
4769
4770 spec->base_init_verbs = ca0132_base_init_verbs;
4771 spec->base_exit_verbs = ca0132_base_exit_verbs;
4772
4773 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4774
4775 ca0132_init_chip(codec);
4776
4777 ca0132_config(codec);
4778
4779 err = ca0132_prepare_verbs(codec);
4780 if (err < 0)
4781 return err;
4782
4783 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4784 if (err < 0)
4785 return err;
4786
4787 return 0;
4788 }
4789
4790 /*
4791 * patch entries
4792 */
4793 static struct hda_device_id snd_hda_id_ca0132[] = {
4794 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
4795 {} /* terminator */
4796 };
4797 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
4798
4799 MODULE_LICENSE("GPL");
4800 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4801
4802 static struct hda_codec_driver ca0132_driver = {
4803 .id = snd_hda_id_ca0132,
4804 };
4805
4806 module_hda_codec_driver(ca0132_driver);
Linux with added FPC-III support