?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Revert "ALSA: hda: Flush interrupts on disabling"
[linux/fpc-iii.git] / sound / soc / davinci / davinci-mcasp.c
blob624c209c94981696a4f91601ed52de75eb4068ab
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
31
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <sound/omap-pcm.h>
40
41 #include "edma-pcm.h"
42 #include "davinci-mcasp.h"
43
44 #define MCASP_MAX_AFIFO_DEPTH 64
45
46 #ifdef CONFIG_PM
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
61 };
62
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
67 bool pm_state;
68 };
69 #endif
70
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
73 int serializers;
74 };
75
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
78 void __iomem *base;
79 u32 fifo_base;
80 struct device *dev;
81 struct snd_pcm_substream *substreams[2];
82 unsigned int dai_fmt;
83
84 /* McASP specific data */
85 int tdm_slots;
86 u32 tdm_mask[2];
87 int slot_width;
88 u8 op_mode;
89 u8 num_serializer;
90 u8 *serial_dir;
91 u8 version;
92 u8 bclk_div;
93 int streams;
94 u32 irq_request[2];
95 int dma_request[2];
96
97 int sysclk_freq;
98 bool bclk_master;
99
100 /* McASP FIFO related */
101 u8 txnumevt;
102 u8 rxnumevt;
103
104 bool dat_port;
105
106 /* Used for comstraint setting on the second stream */
107 u32 channels;
108
109 #ifdef CONFIG_PM_SLEEP
110 struct davinci_mcasp_context context;
111 #endif
112
113 struct davinci_mcasp_ruledata ruledata[2];
114 struct snd_pcm_hw_constraint_list chconstr[2];
115 };
116
117 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
118 u32 val)
119 {
120 void __iomem *reg = mcasp->base + offset;
121 __raw_writel(__raw_readl(reg) | val, reg);
122 }
123
124 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
125 u32 val)
126 {
127 void __iomem *reg = mcasp->base + offset;
128 __raw_writel((__raw_readl(reg) & ~(val)), reg);
129 }
130
131 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
132 u32 val, u32 mask)
133 {
134 void __iomem *reg = mcasp->base + offset;
135 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
136 }
137
138 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
139 u32 val)
140 {
141 __raw_writel(val, mcasp->base + offset);
142 }
143
144 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
145 {
146 return (u32)__raw_readl(mcasp->base + offset);
147 }
148
149 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
150 {
151 int i = 0;
152
153 mcasp_set_bits(mcasp, ctl_reg, val);
154
155 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
156 /* loop count is to avoid the lock-up */
157 for (i = 0; i < 1000; i++) {
158 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
159 break;
160 }
161
162 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
163 printk(KERN_ERR "GBLCTL write error\n");
164 }
165
166 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
167 {
168 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
169 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
170
171 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
172 }
173
174 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
175 {
176 if (mcasp->rxnumevt) { /* enable FIFO */
177 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
178
179 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
180 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
181 }
182
183 /* Start clocks */
184 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
185 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
186 /*
187 * When ASYNC == 0 the transmit and receive sections operate
188 * synchronously from the transmit clock and frame sync. We need to make
189 * sure that the TX signlas are enabled when starting reception.
190 */
191 if (mcasp_is_synchronous(mcasp)) {
192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
193 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
194 }
195
196 /* Activate serializer(s) */
197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
198 /* Release RX state machine */
199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
200 /* Release Frame Sync generator */
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
202 if (mcasp_is_synchronous(mcasp))
203 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
204
205 /* enable receive IRQs */
206 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
207 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
208 }
209
210 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
211 {
212 u32 cnt;
213
214 if (mcasp->txnumevt) { /* enable FIFO */
215 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
216
217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
219 }
220
221 /* Start clocks */
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
224 /* Activate serializer(s) */
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
226
227 /* wait for XDATA to be cleared */
228 cnt = 0;
229 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
230 (cnt < 100000))
231 cnt++;
232
233 /* Release TX state machine */
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
235 /* Release Frame Sync generator */
236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
237
238 /* enable transmit IRQs */
239 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
240 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
241 }
242
243 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
244 {
245 mcasp->streams++;
246
247 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
248 mcasp_start_tx(mcasp);
249 else
250 mcasp_start_rx(mcasp);
251 }
252
253 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
254 {
255 /* disable IRQ sources */
256 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
257 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
258
259 /*
260 * In synchronous mode stop the TX clocks if no other stream is
261 * running
262 */
263 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
265
266 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
267 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
268
269 if (mcasp->rxnumevt) { /* disable FIFO */
270 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
271
272 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
273 }
274 }
275
276 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
277 {
278 u32 val = 0;
279
280 /* disable IRQ sources */
281 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
283
284 /*
285 * In synchronous mode keep TX clocks running if the capture stream is
286 * still running.
287 */
288 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
289 val = TXHCLKRST | TXCLKRST | TXFSRST;
290
291 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
292 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
293
294 if (mcasp->txnumevt) { /* disable FIFO */
295 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
296
297 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
298 }
299 }
300
301 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
302 {
303 mcasp->streams--;
304
305 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
306 mcasp_stop_tx(mcasp);
307 else
308 mcasp_stop_rx(mcasp);
309 }
310
311 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
312 {
313 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
314 struct snd_pcm_substream *substream;
315 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
316 u32 handled_mask = 0;
317 u32 stat;
318
319 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
320 if (stat & XUNDRN & irq_mask) {
321 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
322 handled_mask |= XUNDRN;
323
324 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
325 if (substream) {
326 snd_pcm_stream_lock_irq(substream);
327 if (snd_pcm_running(substream))
328 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
329 snd_pcm_stream_unlock_irq(substream);
330 }
331 }
332
333 if (!handled_mask)
334 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
335 stat);
336
337 if (stat & XRERR)
338 handled_mask |= XRERR;
339
340 /* Ack the handled event only */
341 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
342
343 return IRQ_RETVAL(handled_mask);
344 }
345
346 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
347 {
348 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
349 struct snd_pcm_substream *substream;
350 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
351 u32 handled_mask = 0;
352 u32 stat;
353
354 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
355 if (stat & ROVRN & irq_mask) {
356 dev_warn(mcasp->dev, "Receive buffer overflow\n");
357 handled_mask |= ROVRN;
358
359 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
360 if (substream) {
361 snd_pcm_stream_lock_irq(substream);
362 if (snd_pcm_running(substream))
363 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
364 snd_pcm_stream_unlock_irq(substream);
365 }
366 }
367
368 if (!handled_mask)
369 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
370 stat);
371
372 if (stat & XRERR)
373 handled_mask |= XRERR;
374
375 /* Ack the handled event only */
376 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
377
378 return IRQ_RETVAL(handled_mask);
379 }
380
381 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
382 {
383 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
384 irqreturn_t ret = IRQ_NONE;
385
386 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
387 ret = davinci_mcasp_tx_irq_handler(irq, data);
388
389 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
390 ret |= davinci_mcasp_rx_irq_handler(irq, data);
391
392 return ret;
393 }
394
395 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
396 unsigned int fmt)
397 {
398 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
399 int ret = 0;
400 u32 data_delay;
401 bool fs_pol_rising;
402 bool inv_fs = false;
403
404 if (!fmt)
405 return 0;
406
407 pm_runtime_get_sync(mcasp->dev);
408 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
409 case SND_SOC_DAIFMT_DSP_A:
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
411 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
412 /* 1st data bit occur one ACLK cycle after the frame sync */
413 data_delay = 1;
414 break;
415 case SND_SOC_DAIFMT_DSP_B:
416 case SND_SOC_DAIFMT_AC97:
417 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
418 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
419 /* No delay after FS */
420 data_delay = 0;
421 break;
422 case SND_SOC_DAIFMT_I2S:
423 /* configure a full-word SYNC pulse (LRCLK) */
424 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
425 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
426 /* 1st data bit occur one ACLK cycle after the frame sync */
427 data_delay = 1;
428 /* FS need to be inverted */
429 inv_fs = true;
430 break;
431 case SND_SOC_DAIFMT_LEFT_J:
432 /* configure a full-word SYNC pulse (LRCLK) */
433 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
434 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
435 /* No delay after FS */
436 data_delay = 0;
437 break;
438 default:
439 ret = -EINVAL;
440 goto out;
441 }
442
443 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
444 FSXDLY(3));
445 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
446 FSRDLY(3));
447
448 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
449 case SND_SOC_DAIFMT_CBS_CFS:
450 /* codec is clock and frame slave */
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
452 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
453
454 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
456
457 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
459 mcasp->bclk_master = 1;
460 break;
461 case SND_SOC_DAIFMT_CBS_CFM:
462 /* codec is clock slave and frame master */
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
464 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
465
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
468
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
471 mcasp->bclk_master = 1;
472 break;
473 case SND_SOC_DAIFMT_CBM_CFS:
474 /* codec is clock master and frame slave */
475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
477
478 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
479 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
480
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
482 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
483 mcasp->bclk_master = 0;
484 break;
485 case SND_SOC_DAIFMT_CBM_CFM:
486 /* codec is clock and frame master */
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
488 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
489
490 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
491 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
492
493 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
494 ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
495 mcasp->bclk_master = 0;
496 break;
497 default:
498 ret = -EINVAL;
499 goto out;
500 }
501
502 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
503 case SND_SOC_DAIFMT_IB_NF:
504 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
505 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
506 fs_pol_rising = true;
507 break;
508 case SND_SOC_DAIFMT_NB_IF:
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
511 fs_pol_rising = false;
512 break;
513 case SND_SOC_DAIFMT_IB_IF:
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
515 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
516 fs_pol_rising = false;
517 break;
518 case SND_SOC_DAIFMT_NB_NF:
519 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
520 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
521 fs_pol_rising = true;
522 break;
523 default:
524 ret = -EINVAL;
525 goto out;
526 }
527
528 if (inv_fs)
529 fs_pol_rising = !fs_pol_rising;
530
531 if (fs_pol_rising) {
532 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
534 } else {
535 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
536 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
537 }
538
539 mcasp->dai_fmt = fmt;
540 out:
541 pm_runtime_put(mcasp->dev);
542 return ret;
543 }
544
545 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
546 int div, bool explicit)
547 {
548 pm_runtime_get_sync(mcasp->dev);
549 switch (div_id) {
550 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
551 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
552 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
553 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
554 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
555 break;
556
557 case MCASP_CLKDIV_BCLK: /* BCLK divider */
558 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
559 ACLKXDIV(div - 1), ACLKXDIV_MASK);
560 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
561 ACLKRDIV(div - 1), ACLKRDIV_MASK);
562 if (explicit)
563 mcasp->bclk_div = div;
564 break;
565
566 case MCASP_CLKDIV_BCLK_FS_RATIO:
567 /*
568 * BCLK/LRCLK ratio descries how many bit-clock cycles
569 * fit into one frame. The clock ratio is given for a
570 * full period of data (for I2S format both left and
571 * right channels), so it has to be divided by number
572 * of tdm-slots (for I2S - divided by 2).
573 * Instead of storing this ratio, we calculate a new
574 * tdm_slot width by dividing the the ratio by the
575 * number of configured tdm slots.
576 */
577 mcasp->slot_width = div / mcasp->tdm_slots;
578 if (div % mcasp->tdm_slots)
579 dev_warn(mcasp->dev,
580 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
581 __func__, div, mcasp->tdm_slots);
582 break;
583
584 default:
585 return -EINVAL;
586 }
587
588 pm_runtime_put(mcasp->dev);
589 return 0;
590 }
591
592 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
593 int div)
594 {
595 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
596
597 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
598 }
599
600 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
601 unsigned int freq, int dir)
602 {
603 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
604
605 pm_runtime_get_sync(mcasp->dev);
606 if (dir == SND_SOC_CLOCK_OUT) {
607 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
608 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
609 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
610 } else {
611 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
612 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
613 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
614 }
615
616 mcasp->sysclk_freq = freq;
617
618 pm_runtime_put(mcasp->dev);
619 return 0;
620 }
621
622 /* All serializers must have equal number of channels */
623 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
624 int serializers)
625 {
626 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
627 unsigned int *list = (unsigned int *) cl->list;
628 int slots = mcasp->tdm_slots;
629 int i, count = 0;
630
631 if (mcasp->tdm_mask[stream])
632 slots = hweight32(mcasp->tdm_mask[stream]);
633
634 for (i = 2; i <= slots; i++)
635 list[count++] = i;
636
637 for (i = 2; i <= serializers; i++)
638 list[count++] = i*slots;
639
640 cl->count = count;
641
642 return 0;
643 }
644
645 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
646 {
647 int rx_serializers = 0, tx_serializers = 0, ret, i;
648
649 for (i = 0; i < mcasp->num_serializer; i++)
650 if (mcasp->serial_dir[i] == TX_MODE)
651 tx_serializers++;
652 else if (mcasp->serial_dir[i] == RX_MODE)
653 rx_serializers++;
654
655 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
656 tx_serializers);
657 if (ret)
658 return ret;
659
660 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
661 rx_serializers);
662
663 return ret;
664 }
665
666
667 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
668 unsigned int tx_mask,
669 unsigned int rx_mask,
670 int slots, int slot_width)
671 {
672 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
673
674 dev_dbg(mcasp->dev,
675 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
676 __func__, tx_mask, rx_mask, slots, slot_width);
677
678 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
679 dev_err(mcasp->dev,
680 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
681 tx_mask, rx_mask, slots);
682 return -EINVAL;
683 }
684
685 if (slot_width &&
686 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
687 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
688 __func__, slot_width);
689 return -EINVAL;
690 }
691
692 mcasp->tdm_slots = slots;
693 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
694 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
695 mcasp->slot_width = slot_width;
696
697 return davinci_mcasp_set_ch_constraints(mcasp);
698 }
699
700 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
701 int sample_width)
702 {
703 u32 fmt;
704 u32 tx_rotate = (sample_width / 4) & 0x7;
705 u32 mask = (1ULL << sample_width) - 1;
706 u32 slot_width = sample_width;
707
708 /*
709 * For captured data we should not rotate, inversion and masking is
710 * enoguh to get the data to the right position:
711 * Format data from bus after reverse (XRBUF)
712 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
713 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
714 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
715 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
716 */
717 u32 rx_rotate = 0;
718
719 /*
720 * Setting the tdm slot width either with set_clkdiv() or
721 * set_tdm_slot() allows us to for example send 32 bits per
722 * channel to the codec, while only 16 of them carry audio
723 * payload.
724 */
725 if (mcasp->slot_width) {
726 /*
727 * When we have more bclk then it is needed for the
728 * data, we need to use the rotation to move the
729 * received samples to have correct alignment.
730 */
731 slot_width = mcasp->slot_width;
732 rx_rotate = (slot_width - sample_width) / 4;
733 }
734
735 /* mapping of the XSSZ bit-field as described in the datasheet */
736 fmt = (slot_width >> 1) - 1;
737
738 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
739 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
740 RXSSZ(0x0F));
741 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
742 TXSSZ(0x0F));
743 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
744 TXROT(7));
745 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
746 RXROT(7));
747 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
748 }
749
750 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
751
752 return 0;
753 }
754
755 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
756 int period_words, int channels)
757 {
758 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
759 int i;
760 u8 tx_ser = 0;
761 u8 rx_ser = 0;
762 u8 slots = mcasp->tdm_slots;
763 u8 max_active_serializers = (channels + slots - 1) / slots;
764 int active_serializers, numevt;
765 u32 reg;
766 /* Default configuration */
767 if (mcasp->version < MCASP_VERSION_3)
768 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
769
770 /* All PINS as McASP */
771 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
772
773 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
774 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
775 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
776 } else {
777 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
778 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
779 }
780
781 for (i = 0; i < mcasp->num_serializer; i++) {
782 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
783 mcasp->serial_dir[i]);
784 if (mcasp->serial_dir[i] == TX_MODE &&
785 tx_ser < max_active_serializers) {
786 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
787 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
788 DISMOD_LOW, DISMOD_MASK);
789 tx_ser++;
790 } else if (mcasp->serial_dir[i] == RX_MODE &&
791 rx_ser < max_active_serializers) {
792 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
793 rx_ser++;
794 } else {
795 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
796 SRMOD_INACTIVE, SRMOD_MASK);
797 }
798 }
799
800 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
801 active_serializers = tx_ser;
802 numevt = mcasp->txnumevt;
803 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
804 } else {
805 active_serializers = rx_ser;
806 numevt = mcasp->rxnumevt;
807 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
808 }
809
810 if (active_serializers < max_active_serializers) {
811 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
812 "enabled in mcasp (%d)\n", channels,
813 active_serializers * slots);
814 return -EINVAL;
815 }
816
817 /* AFIFO is not in use */
818 if (!numevt) {
819 /* Configure the burst size for platform drivers */
820 if (active_serializers > 1) {
821 /*
822 * If more than one serializers are in use we have one
823 * DMA request to provide data for all serializers.
824 * For example if three serializers are enabled the DMA
825 * need to transfer three words per DMA request.
826 */
827 dma_data->maxburst = active_serializers;
828 } else {
829 dma_data->maxburst = 0;
830 }
831 return 0;
832 }
833
834 if (period_words % active_serializers) {
835 dev_err(mcasp->dev, "Invalid combination of period words and "
836 "active serializers: %d, %d\n", period_words,
837 active_serializers);
838 return -EINVAL;
839 }
840
841 /*
842 * Calculate the optimal AFIFO depth for platform side:
843 * The number of words for numevt need to be in steps of active
844 * serializers.
845 */
846 numevt = (numevt / active_serializers) * active_serializers;
847
848 while (period_words % numevt && numevt > 0)
849 numevt -= active_serializers;
850 if (numevt <= 0)
851 numevt = active_serializers;
852
853 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
854 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
855
856 /* Configure the burst size for platform drivers */
857 if (numevt == 1)
858 numevt = 0;
859 dma_data->maxburst = numevt;
860
861 return 0;
862 }
863
864 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
865 int channels)
866 {
867 int i, active_slots;
868 int total_slots;
869 int active_serializers;
870 u32 mask = 0;
871 u32 busel = 0;
872
873 total_slots = mcasp->tdm_slots;
874
875 /*
876 * If more than one serializer is needed, then use them with
877 * all the specified tdm_slots. Otherwise, one serializer can
878 * cope with the transaction using just as many slots as there
879 * are channels in the stream.
880 */
881 if (mcasp->tdm_mask[stream]) {
882 active_slots = hweight32(mcasp->tdm_mask[stream]);
883 active_serializers = (channels + active_slots - 1) /
884 active_slots;
885 if (active_serializers == 1) {
886 active_slots = channels;
887 for (i = 0; i < total_slots; i++) {
888 if ((1 << i) & mcasp->tdm_mask[stream]) {
889 mask |= (1 << i);
890 if (--active_slots <= 0)
891 break;
892 }
893 }
894 }
895 } else {
896 active_serializers = (channels + total_slots - 1) / total_slots;
897 if (active_serializers == 1)
898 active_slots = channels;
899 else
900 active_slots = total_slots;
901
902 for (i = 0; i < active_slots; i++)
903 mask |= (1 << i);
904 }
905 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
906
907 if (!mcasp->dat_port)
908 busel = TXSEL;
909
910 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
911 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
912 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
913 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
914 FSXMOD(total_slots), FSXMOD(0x1FF));
915 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
916 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
917 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
918 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
919 FSRMOD(total_slots), FSRMOD(0x1FF));
920 /*
921 * If McASP is set to be TX/RX synchronous and the playback is
922 * not running already we need to configure the TX slots in
923 * order to have correct FSX on the bus
924 */
925 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
926 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
927 FSXMOD(total_slots), FSXMOD(0x1FF));
928 }
929
930 return 0;
931 }
932
933 /* S/PDIF */
934 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
935 unsigned int rate)
936 {
937 u32 cs_value = 0;
938 u8 *cs_bytes = (u8*) &cs_value;
939
940 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
941 and LSB first */
942 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
943
944 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
945 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
946
947 /* Set the TX tdm : for all the slots */
948 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
949
950 /* Set the TX clock controls : div = 1 and internal */
951 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
952
953 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
954
955 /* Only 44100 and 48000 are valid, both have the same setting */
956 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
957
958 /* Enable the DIT */
959 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
960
961 /* Set S/PDIF channel status bits */
962 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
963 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
964
965 switch (rate) {
966 case 22050:
967 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
968 break;
969 case 24000:
970 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
971 break;
972 case 32000:
973 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
974 break;
975 case 44100:
976 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
977 break;
978 case 48000:
979 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
980 break;
981 case 88200:
982 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
983 break;
984 case 96000:
985 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
986 break;
987 case 176400:
988 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
989 break;
990 case 192000:
991 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
992 break;
993 default:
994 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
995 return -EINVAL;
996 }
997
998 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
999 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1000
1001 return 0;
1002 }
1003
1004 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1005 unsigned int bclk_freq, bool set)
1006 {
1007 int error_ppm;
1008 unsigned int sysclk_freq = mcasp->sysclk_freq;
1009 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1010 int div = sysclk_freq / bclk_freq;
1011 int rem = sysclk_freq % bclk_freq;
1012 int aux_div = 1;
1013
1014 if (div > (ACLKXDIV_MASK + 1)) {
1015 if (reg & AHCLKXE) {
1016 aux_div = div / (ACLKXDIV_MASK + 1);
1017 if (div % (ACLKXDIV_MASK + 1))
1018 aux_div++;
1019
1020 sysclk_freq /= aux_div;
1021 div = sysclk_freq / bclk_freq;
1022 rem = sysclk_freq % bclk_freq;
1023 } else if (set) {
1024 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1025 sysclk_freq);
1026 }
1027 }
1028
1029 if (rem != 0) {
1030 if (div == 0 ||
1031 ((sysclk_freq / div) - bclk_freq) >
1032 (bclk_freq - (sysclk_freq / (div+1)))) {
1033 div++;
1034 rem = rem - bclk_freq;
1035 }
1036 }
1037 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1038 (int)bclk_freq)) / div - 1000000;
1039
1040 if (set) {
1041 if (error_ppm)
1042 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1043 error_ppm);
1044
1045 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1046 if (reg & AHCLKXE)
1047 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1048 aux_div, 0);
1049 }
1050
1051 return error_ppm;
1052 }
1053
1054 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1055 struct snd_pcm_hw_params *params,
1056 struct snd_soc_dai *cpu_dai)
1057 {
1058 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1059 int word_length;
1060 int channels = params_channels(params);
1061 int period_size = params_period_size(params);
1062 int ret;
1063
1064 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1065 if (ret)
1066 return ret;
1067
1068 /*
1069 * If mcasp is BCLK master, and a BCLK divider was not provided by
1070 * the machine driver, we need to calculate the ratio.
1071 */
1072 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1073 int slots = mcasp->tdm_slots;
1074 int rate = params_rate(params);
1075 int sbits = params_width(params);
1076
1077 if (mcasp->slot_width)
1078 sbits = mcasp->slot_width;
1079
1080 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1081 }
1082
1083 ret = mcasp_common_hw_param(mcasp, substream->stream,
1084 period_size * channels, channels);
1085 if (ret)
1086 return ret;
1087
1088 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1089 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1090 else
1091 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1092 channels);
1093
1094 if (ret)
1095 return ret;
1096
1097 switch (params_format(params)) {
1098 case SNDRV_PCM_FORMAT_U8:
1099 case SNDRV_PCM_FORMAT_S8:
1100 word_length = 8;
1101 break;
1102
1103 case SNDRV_PCM_FORMAT_U16_LE:
1104 case SNDRV_PCM_FORMAT_S16_LE:
1105 word_length = 16;
1106 break;
1107
1108 case SNDRV_PCM_FORMAT_U24_3LE:
1109 case SNDRV_PCM_FORMAT_S24_3LE:
1110 word_length = 24;
1111 break;
1112
1113 case SNDRV_PCM_FORMAT_U24_LE:
1114 case SNDRV_PCM_FORMAT_S24_LE:
1115 word_length = 24;
1116 break;
1117
1118 case SNDRV_PCM_FORMAT_U32_LE:
1119 case SNDRV_PCM_FORMAT_S32_LE:
1120 word_length = 32;
1121 break;
1122
1123 default:
1124 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1125 return -EINVAL;
1126 }
1127
1128 davinci_config_channel_size(mcasp, word_length);
1129
1130 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1131 mcasp->channels = channels;
1132
1133 return 0;
1134 }
1135
1136 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1137 int cmd, struct snd_soc_dai *cpu_dai)
1138 {
1139 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1140 int ret = 0;
1141
1142 switch (cmd) {
1143 case SNDRV_PCM_TRIGGER_RESUME:
1144 case SNDRV_PCM_TRIGGER_START:
1145 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1146 davinci_mcasp_start(mcasp, substream->stream);
1147 break;
1148 case SNDRV_PCM_TRIGGER_SUSPEND:
1149 case SNDRV_PCM_TRIGGER_STOP:
1150 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1151 davinci_mcasp_stop(mcasp, substream->stream);
1152 break;
1153
1154 default:
1155 ret = -EINVAL;
1156 }
1157
1158 return ret;
1159 }
1160
1161 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1162 struct snd_pcm_hw_rule *rule)
1163 {
1164 struct davinci_mcasp_ruledata *rd = rule->private;
1165 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1166 struct snd_mask nfmt;
1167 int i, slot_width;
1168
1169 snd_mask_none(&nfmt);
1170 slot_width = rd->mcasp->slot_width;
1171
1172 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1173 if (snd_mask_test(fmt, i)) {
1174 if (snd_pcm_format_width(i) <= slot_width) {
1175 snd_mask_set(&nfmt, i);
1176 }
1177 }
1178 }
1179
1180 return snd_mask_refine(fmt, &nfmt);
1181 }
1182
1183 static const unsigned int davinci_mcasp_dai_rates[] = {
1184 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1185 88200, 96000, 176400, 192000,
1186 };
1187
1188 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1189
1190 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1191 struct snd_pcm_hw_rule *rule)
1192 {
1193 struct davinci_mcasp_ruledata *rd = rule->private;
1194 struct snd_interval *ri =
1195 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1196 int sbits = params_width(params);
1197 int slots = rd->mcasp->tdm_slots;
1198 struct snd_interval range;
1199 int i;
1200
1201 if (rd->mcasp->slot_width)
1202 sbits = rd->mcasp->slot_width;
1203
1204 snd_interval_any(&range);
1205 range.empty = 1;
1206
1207 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1208 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1209 uint bclk_freq = sbits*slots*
1210 davinci_mcasp_dai_rates[i];
1211 int ppm;
1212
1213 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1214 false);
1215 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1216 if (range.empty) {
1217 range.min = davinci_mcasp_dai_rates[i];
1218 range.empty = 0;
1219 }
1220 range.max = davinci_mcasp_dai_rates[i];
1221 }
1222 }
1223 }
1224
1225 dev_dbg(rd->mcasp->dev,
1226 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1227 ri->min, ri->max, range.min, range.max, sbits, slots);
1228
1229 return snd_interval_refine(hw_param_interval(params, rule->var),
1230 &range);
1231 }
1232
1233 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1234 struct snd_pcm_hw_rule *rule)
1235 {
1236 struct davinci_mcasp_ruledata *rd = rule->private;
1237 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1238 struct snd_mask nfmt;
1239 int rate = params_rate(params);
1240 int slots = rd->mcasp->tdm_slots;
1241 int i, count = 0;
1242
1243 snd_mask_none(&nfmt);
1244
1245 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1246 if (snd_mask_test(fmt, i)) {
1247 uint sbits = snd_pcm_format_width(i);
1248 int ppm;
1249
1250 if (rd->mcasp->slot_width)
1251 sbits = rd->mcasp->slot_width;
1252
1253 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1254 sbits * slots * rate,
1255 false);
1256 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1257 snd_mask_set(&nfmt, i);
1258 count++;
1259 }
1260 }
1261 }
1262 dev_dbg(rd->mcasp->dev,
1263 "%d possible sample format for %d Hz and %d tdm slots\n",
1264 count, rate, slots);
1265
1266 return snd_mask_refine(fmt, &nfmt);
1267 }
1268
1269 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1270 struct snd_soc_dai *cpu_dai)
1271 {
1272 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1273 struct davinci_mcasp_ruledata *ruledata =
1274 &mcasp->ruledata[substream->stream];
1275 u32 max_channels = 0;
1276 int i, dir, ret;
1277 int tdm_slots = mcasp->tdm_slots;
1278
1279 /* Do not allow more then one stream per direction */
1280 if (mcasp->substreams[substream->stream])
1281 return -EBUSY;
1282
1283 mcasp->substreams[substream->stream] = substream;
1284
1285 if (mcasp->tdm_mask[substream->stream])
1286 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1287
1288 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1289 return 0;
1290
1291 /*
1292 * Limit the maximum allowed channels for the first stream:
1293 * number of serializers for the direction * tdm slots per serializer
1294 */
1295 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1296 dir = TX_MODE;
1297 else
1298 dir = RX_MODE;
1299
1300 for (i = 0; i < mcasp->num_serializer; i++) {
1301 if (mcasp->serial_dir[i] == dir)
1302 max_channels++;
1303 }
1304 ruledata->serializers = max_channels;
1305 ruledata->mcasp = mcasp;
1306 max_channels *= tdm_slots;
1307 /*
1308 * If the already active stream has less channels than the calculated
1309 * limnit based on the seirializers * tdm_slots, we need to use that as
1310 * a constraint for the second stream.
1311 * Otherwise (first stream or less allowed channels) we use the
1312 * calculated constraint.
1313 */
1314 if (mcasp->channels && mcasp->channels < max_channels)
1315 max_channels = mcasp->channels;
1316 /*
1317 * But we can always allow channels upto the amount of
1318 * the available tdm_slots.
1319 */
1320 if (max_channels < tdm_slots)
1321 max_channels = tdm_slots;
1322
1323 snd_pcm_hw_constraint_minmax(substream->runtime,
1324 SNDRV_PCM_HW_PARAM_CHANNELS,
1325 2, max_channels);
1326
1327 snd_pcm_hw_constraint_list(substream->runtime,
1328 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1329 &mcasp->chconstr[substream->stream]);
1330
1331 if (mcasp->slot_width) {
1332 /* Only allow formats require <= slot_width bits on the bus */
1333 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1334 SNDRV_PCM_HW_PARAM_FORMAT,
1335 davinci_mcasp_hw_rule_slot_width,
1336 ruledata,
1337 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1338 if (ret)
1339 return ret;
1340 }
1341
1342 /*
1343 * If we rely on implicit BCLK divider setting we should
1344 * set constraints based on what we can provide.
1345 */
1346 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1347 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1348 SNDRV_PCM_HW_PARAM_RATE,
1349 davinci_mcasp_hw_rule_rate,
1350 ruledata,
1351 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1352 if (ret)
1353 return ret;
1354 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1355 SNDRV_PCM_HW_PARAM_FORMAT,
1356 davinci_mcasp_hw_rule_format,
1357 ruledata,
1358 SNDRV_PCM_HW_PARAM_RATE, -1);
1359 if (ret)
1360 return ret;
1361 }
1362
1363 return 0;
1364 }
1365
1366 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1367 struct snd_soc_dai *cpu_dai)
1368 {
1369 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1370
1371 mcasp->substreams[substream->stream] = NULL;
1372
1373 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1374 return;
1375
1376 if (!cpu_dai->active)
1377 mcasp->channels = 0;
1378 }
1379
1380 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1381 .startup = davinci_mcasp_startup,
1382 .shutdown = davinci_mcasp_shutdown,
1383 .trigger = davinci_mcasp_trigger,
1384 .hw_params = davinci_mcasp_hw_params,
1385 .set_fmt = davinci_mcasp_set_dai_fmt,
1386 .set_clkdiv = davinci_mcasp_set_clkdiv,
1387 .set_sysclk = davinci_mcasp_set_sysclk,
1388 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1389 };
1390
1391 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1392 {
1393 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1394
1395 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1396 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1397
1398 return 0;
1399 }
1400
1401 #ifdef CONFIG_PM_SLEEP
1402 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1403 {
1404 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1405 struct davinci_mcasp_context *context = &mcasp->context;
1406 u32 reg;
1407 int i;
1408
1409 context->pm_state = pm_runtime_active(mcasp->dev);
1410 if (!context->pm_state)
1411 pm_runtime_get_sync(mcasp->dev);
1412
1413 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1414 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1415
1416 if (mcasp->txnumevt) {
1417 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1418 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1419 }
1420 if (mcasp->rxnumevt) {
1421 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1422 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1423 }
1424
1425 for (i = 0; i < mcasp->num_serializer; i++)
1426 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1427 DAVINCI_MCASP_XRSRCTL_REG(i));
1428
1429 pm_runtime_put_sync(mcasp->dev);
1430
1431 return 0;
1432 }
1433
1434 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1435 {
1436 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1437 struct davinci_mcasp_context *context = &mcasp->context;
1438 u32 reg;
1439 int i;
1440
1441 pm_runtime_get_sync(mcasp->dev);
1442
1443 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1444 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1445
1446 if (mcasp->txnumevt) {
1447 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1448 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1449 }
1450 if (mcasp->rxnumevt) {
1451 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1452 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1453 }
1454
1455 for (i = 0; i < mcasp->num_serializer; i++)
1456 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1457 context->xrsr_regs[i]);
1458
1459 if (!context->pm_state)
1460 pm_runtime_put_sync(mcasp->dev);
1461
1462 return 0;
1463 }
1464 #else
1465 #define davinci_mcasp_suspend NULL
1466 #define davinci_mcasp_resume NULL
1467 #endif
1468
1469 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1470
1471 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1472 SNDRV_PCM_FMTBIT_U8 | \
1473 SNDRV_PCM_FMTBIT_S16_LE | \
1474 SNDRV_PCM_FMTBIT_U16_LE | \
1475 SNDRV_PCM_FMTBIT_S24_LE | \
1476 SNDRV_PCM_FMTBIT_U24_LE | \
1477 SNDRV_PCM_FMTBIT_S24_3LE | \
1478 SNDRV_PCM_FMTBIT_U24_3LE | \
1479 SNDRV_PCM_FMTBIT_S32_LE | \
1480 SNDRV_PCM_FMTBIT_U32_LE)
1481
1482 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1483 {
1484 .name = "davinci-mcasp.0",
1485 .probe = davinci_mcasp_dai_probe,
1486 .suspend = davinci_mcasp_suspend,
1487 .resume = davinci_mcasp_resume,
1488 .playback = {
1489 .channels_min = 2,
1490 .channels_max = 32 * 16,
1491 .rates = DAVINCI_MCASP_RATES,
1492 .formats = DAVINCI_MCASP_PCM_FMTS,
1493 },
1494 .capture = {
1495 .channels_min = 2,
1496 .channels_max = 32 * 16,
1497 .rates = DAVINCI_MCASP_RATES,
1498 .formats = DAVINCI_MCASP_PCM_FMTS,
1499 },
1500 .ops = &davinci_mcasp_dai_ops,
1501
1502 .symmetric_samplebits = 1,
1503 .symmetric_rates = 1,
1504 },
1505 {
1506 .name = "davinci-mcasp.1",
1507 .probe = davinci_mcasp_dai_probe,
1508 .playback = {
1509 .channels_min = 1,
1510 .channels_max = 384,
1511 .rates = DAVINCI_MCASP_RATES,
1512 .formats = DAVINCI_MCASP_PCM_FMTS,
1513 },
1514 .ops = &davinci_mcasp_dai_ops,
1515 },
1516
1517 };
1518
1519 static const struct snd_soc_component_driver davinci_mcasp_component = {
1520 .name = "davinci-mcasp",
1521 };
1522
1523 /* Some HW specific values and defaults. The rest is filled in from DT. */
1524 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1525 .tx_dma_offset = 0x400,
1526 .rx_dma_offset = 0x400,
1527 .version = MCASP_VERSION_1,
1528 };
1529
1530 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1531 .tx_dma_offset = 0x2000,
1532 .rx_dma_offset = 0x2000,
1533 .version = MCASP_VERSION_2,
1534 };
1535
1536 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1537 .tx_dma_offset = 0,
1538 .rx_dma_offset = 0,
1539 .version = MCASP_VERSION_3,
1540 };
1541
1542 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1543 /* The CFG port offset will be calculated if it is needed */
1544 .tx_dma_offset = 0,
1545 .rx_dma_offset = 0,
1546 .version = MCASP_VERSION_4,
1547 };
1548
1549 static const struct of_device_id mcasp_dt_ids[] = {
1550 {
1551 .compatible = "ti,dm646x-mcasp-audio",
1552 .data = &dm646x_mcasp_pdata,
1553 },
1554 {
1555 .compatible = "ti,da830-mcasp-audio",
1556 .data = &da830_mcasp_pdata,
1557 },
1558 {
1559 .compatible = "ti,am33xx-mcasp-audio",
1560 .data = &am33xx_mcasp_pdata,
1561 },
1562 {
1563 .compatible = "ti,dra7-mcasp-audio",
1564 .data = &dra7_mcasp_pdata,
1565 },
1566 { /* sentinel */ }
1567 };
1568 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1569
1570 static int mcasp_reparent_fck(struct platform_device *pdev)
1571 {
1572 struct device_node *node = pdev->dev.of_node;
1573 struct clk *gfclk, *parent_clk;
1574 const char *parent_name;
1575 int ret;
1576
1577 if (!node)
1578 return 0;
1579
1580 parent_name = of_get_property(node, "fck_parent", NULL);
1581 if (!parent_name)
1582 return 0;
1583
1584 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1585
1586 gfclk = clk_get(&pdev->dev, "fck");
1587 if (IS_ERR(gfclk)) {
1588 dev_err(&pdev->dev, "failed to get fck\n");
1589 return PTR_ERR(gfclk);
1590 }
1591
1592 parent_clk = clk_get(NULL, parent_name);
1593 if (IS_ERR(parent_clk)) {
1594 dev_err(&pdev->dev, "failed to get parent clock\n");
1595 ret = PTR_ERR(parent_clk);
1596 goto err1;
1597 }
1598
1599 ret = clk_set_parent(gfclk, parent_clk);
1600 if (ret) {
1601 dev_err(&pdev->dev, "failed to reparent fck\n");
1602 goto err2;
1603 }
1604
1605 err2:
1606 clk_put(parent_clk);
1607 err1:
1608 clk_put(gfclk);
1609 return ret;
1610 }
1611
1612 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1613 struct platform_device *pdev)
1614 {
1615 struct device_node *np = pdev->dev.of_node;
1616 struct davinci_mcasp_pdata *pdata = NULL;
1617 const struct of_device_id *match =
1618 of_match_device(mcasp_dt_ids, &pdev->dev);
1619 struct of_phandle_args dma_spec;
1620
1621 const u32 *of_serial_dir32;
1622 u32 val;
1623 int i, ret = 0;
1624
1625 if (pdev->dev.platform_data) {
1626 pdata = pdev->dev.platform_data;
1627 return pdata;
1628 } else if (match) {
1629 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1630 GFP_KERNEL);
1631 if (!pdata) {
1632 dev_err(&pdev->dev,
1633 "Failed to allocate memory for pdata\n");
1634 ret = -ENOMEM;
1635 return pdata;
1636 }
1637 } else {
1638 /* control shouldn't reach here. something is wrong */
1639 ret = -EINVAL;
1640 goto nodata;
1641 }
1642
1643 ret = of_property_read_u32(np, "op-mode", &val);
1644 if (ret >= 0)
1645 pdata->op_mode = val;
1646
1647 ret = of_property_read_u32(np, "tdm-slots", &val);
1648 if (ret >= 0) {
1649 if (val < 2 || val > 32) {
1650 dev_err(&pdev->dev,
1651 "tdm-slots must be in rage [2-32]\n");
1652 ret = -EINVAL;
1653 goto nodata;
1654 }
1655
1656 pdata->tdm_slots = val;
1657 }
1658
1659 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1660 val /= sizeof(u32);
1661 if (of_serial_dir32) {
1662 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1663 (sizeof(*of_serial_dir) * val),
1664 GFP_KERNEL);
1665 if (!of_serial_dir) {
1666 ret = -ENOMEM;
1667 goto nodata;
1668 }
1669
1670 for (i = 0; i < val; i++)
1671 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1672
1673 pdata->num_serializer = val;
1674 pdata->serial_dir = of_serial_dir;
1675 }
1676
1677 ret = of_property_match_string(np, "dma-names", "tx");
1678 if (ret < 0)
1679 goto nodata;
1680
1681 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1682 &dma_spec);
1683 if (ret < 0)
1684 goto nodata;
1685
1686 pdata->tx_dma_channel = dma_spec.args[0];
1687
1688 /* RX is not valid in DIT mode */
1689 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1690 ret = of_property_match_string(np, "dma-names", "rx");
1691 if (ret < 0)
1692 goto nodata;
1693
1694 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1695 &dma_spec);
1696 if (ret < 0)
1697 goto nodata;
1698
1699 pdata->rx_dma_channel = dma_spec.args[0];
1700 }
1701
1702 ret = of_property_read_u32(np, "tx-num-evt", &val);
1703 if (ret >= 0)
1704 pdata->txnumevt = val;
1705
1706 ret = of_property_read_u32(np, "rx-num-evt", &val);
1707 if (ret >= 0)
1708 pdata->rxnumevt = val;
1709
1710 ret = of_property_read_u32(np, "sram-size-playback", &val);
1711 if (ret >= 0)
1712 pdata->sram_size_playback = val;
1713
1714 ret = of_property_read_u32(np, "sram-size-capture", &val);
1715 if (ret >= 0)
1716 pdata->sram_size_capture = val;
1717
1718 return pdata;
1719
1720 nodata:
1721 if (ret < 0) {
1722 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1723 ret);
1724 pdata = NULL;
1725 }
1726 return pdata;
1727 }
1728
1729 enum {
1730 PCM_EDMA,
1731 PCM_SDMA,
1732 };
1733 static const char *sdma_prefix = "ti,omap";
1734
1735 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1736 {
1737 struct dma_chan *chan;
1738 const char *tmp;
1739 int ret = PCM_EDMA;
1740
1741 if (!mcasp->dev->of_node)
1742 return PCM_EDMA;
1743
1744 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1745 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1746 if (IS_ERR(chan)) {
1747 if (PTR_ERR(chan) != -EPROBE_DEFER)
1748 dev_err(mcasp->dev,
1749 "Can't verify DMA configuration (%ld)\n",
1750 PTR_ERR(chan));
1751 return PTR_ERR(chan);
1752 }
1753 BUG_ON(!chan->device || !chan->device->dev);
1754
1755 if (chan->device->dev->of_node)
1756 ret = of_property_read_string(chan->device->dev->of_node,
1757 "compatible", &tmp);
1758 else
1759 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1760
1761 dma_release_channel(chan);
1762 if (ret)
1763 return ret;
1764
1765 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1766 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1767 return PCM_SDMA;
1768
1769 return PCM_EDMA;
1770 }
1771
1772 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1773 {
1774 int i;
1775 u32 offset = 0;
1776
1777 if (pdata->version != MCASP_VERSION_4)
1778 return pdata->tx_dma_offset;
1779
1780 for (i = 0; i < pdata->num_serializer; i++) {
1781 if (pdata->serial_dir[i] == TX_MODE) {
1782 if (!offset) {
1783 offset = DAVINCI_MCASP_TXBUF_REG(i);
1784 } else {
1785 pr_err("%s: Only one serializer allowed!\n",
1786 __func__);
1787 break;
1788 }
1789 }
1790 }
1791
1792 return offset;
1793 }
1794
1795 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1796 {
1797 int i;
1798 u32 offset = 0;
1799
1800 if (pdata->version != MCASP_VERSION_4)
1801 return pdata->rx_dma_offset;
1802
1803 for (i = 0; i < pdata->num_serializer; i++) {
1804 if (pdata->serial_dir[i] == RX_MODE) {
1805 if (!offset) {
1806 offset = DAVINCI_MCASP_RXBUF_REG(i);
1807 } else {
1808 pr_err("%s: Only one serializer allowed!\n",
1809 __func__);
1810 break;
1811 }
1812 }
1813 }
1814
1815 return offset;
1816 }
1817
1818 static int davinci_mcasp_probe(struct platform_device *pdev)
1819 {
1820 struct snd_dmaengine_dai_dma_data *dma_data;
1821 struct resource *mem, *res, *dat;
1822 struct davinci_mcasp_pdata *pdata;
1823 struct davinci_mcasp *mcasp;
1824 char *irq_name;
1825 int *dma;
1826 int irq;
1827 int ret;
1828
1829 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1830 dev_err(&pdev->dev, "No platform data supplied\n");
1831 return -EINVAL;
1832 }
1833
1834 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1835 GFP_KERNEL);
1836 if (!mcasp)
1837 return -ENOMEM;
1838
1839 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1840 if (!pdata) {
1841 dev_err(&pdev->dev, "no platform data\n");
1842 return -EINVAL;
1843 }
1844
1845 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1846 if (!mem) {
1847 dev_warn(mcasp->dev,
1848 "\"mpu\" mem resource not found, using index 0\n");
1849 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1850 if (!mem) {
1851 dev_err(&pdev->dev, "no mem resource?\n");
1852 return -ENODEV;
1853 }
1854 }
1855
1856 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1857 if (IS_ERR(mcasp->base))
1858 return PTR_ERR(mcasp->base);
1859
1860 pm_runtime_enable(&pdev->dev);
1861
1862 mcasp->op_mode = pdata->op_mode;
1863 /* sanity check for tdm slots parameter */
1864 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1865 if (pdata->tdm_slots < 2) {
1866 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1867 pdata->tdm_slots);
1868 mcasp->tdm_slots = 2;
1869 } else if (pdata->tdm_slots > 32) {
1870 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1871 pdata->tdm_slots);
1872 mcasp->tdm_slots = 32;
1873 } else {
1874 mcasp->tdm_slots = pdata->tdm_slots;
1875 }
1876 }
1877
1878 mcasp->num_serializer = pdata->num_serializer;
1879 #ifdef CONFIG_PM_SLEEP
1880 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1881 sizeof(u32) * mcasp->num_serializer,
1882 GFP_KERNEL);
1883 #endif
1884 mcasp->serial_dir = pdata->serial_dir;
1885 mcasp->version = pdata->version;
1886 mcasp->txnumevt = pdata->txnumevt;
1887 mcasp->rxnumevt = pdata->rxnumevt;
1888
1889 mcasp->dev = &pdev->dev;
1890
1891 irq = platform_get_irq_byname(pdev, "common");
1892 if (irq >= 0) {
1893 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1894 dev_name(&pdev->dev));
1895 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1896 davinci_mcasp_common_irq_handler,
1897 IRQF_ONESHOT | IRQF_SHARED,
1898 irq_name, mcasp);
1899 if (ret) {
1900 dev_err(&pdev->dev, "common IRQ request failed\n");
1901 goto err;
1902 }
1903
1904 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1905 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1906 }
1907
1908 irq = platform_get_irq_byname(pdev, "rx");
1909 if (irq >= 0) {
1910 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1911 dev_name(&pdev->dev));
1912 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1913 davinci_mcasp_rx_irq_handler,
1914 IRQF_ONESHOT, irq_name, mcasp);
1915 if (ret) {
1916 dev_err(&pdev->dev, "RX IRQ request failed\n");
1917 goto err;
1918 }
1919
1920 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1921 }
1922
1923 irq = platform_get_irq_byname(pdev, "tx");
1924 if (irq >= 0) {
1925 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1926 dev_name(&pdev->dev));
1927 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1928 davinci_mcasp_tx_irq_handler,
1929 IRQF_ONESHOT, irq_name, mcasp);
1930 if (ret) {
1931 dev_err(&pdev->dev, "TX IRQ request failed\n");
1932 goto err;
1933 }
1934
1935 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1936 }
1937
1938 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1939 if (dat)
1940 mcasp->dat_port = true;
1941
1942 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1943 if (dat)
1944 dma_data->addr = dat->start;
1945 else
1946 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1947
1948 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1949 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1950 if (res)
1951 *dma = res->start;
1952 else
1953 *dma = pdata->tx_dma_channel;
1954
1955 /* dmaengine filter data for DT and non-DT boot */
1956 if (pdev->dev.of_node)
1957 dma_data->filter_data = "tx";
1958 else
1959 dma_data->filter_data = dma;
1960
1961 /* RX is not valid in DIT mode */
1962 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1963 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1964 if (dat)
1965 dma_data->addr = dat->start;
1966 else
1967 dma_data->addr =
1968 mem->start + davinci_mcasp_rxdma_offset(pdata);
1969
1970 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1971 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1972 if (res)
1973 *dma = res->start;
1974 else
1975 *dma = pdata->rx_dma_channel;
1976
1977 /* dmaengine filter data for DT and non-DT boot */
1978 if (pdev->dev.of_node)
1979 dma_data->filter_data = "rx";
1980 else
1981 dma_data->filter_data = dma;
1982 }
1983
1984 if (mcasp->version < MCASP_VERSION_3) {
1985 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1986 /* dma_params->dma_addr is pointing to the data port address */
1987 mcasp->dat_port = true;
1988 } else {
1989 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1990 }
1991
1992 /* Allocate memory for long enough list for all possible
1993 * scenarios. Maximum number tdm slots is 32 and there cannot
1994 * be more serializers than given in the configuration. The
1995 * serializer directions could be taken into account, but it
1996 * would make code much more complex and save only couple of
1997 * bytes.
1998 */
1999 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2000 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
2001 (32 + mcasp->num_serializer - 2),
2002 GFP_KERNEL);
2003
2004 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2005 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
2006 (32 + mcasp->num_serializer - 2),
2007 GFP_KERNEL);
2008
2009 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2010 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
2011 return -ENOMEM;
2012
2013 ret = davinci_mcasp_set_ch_constraints(mcasp);
2014 if (ret)
2015 goto err;
2016
2017 dev_set_drvdata(&pdev->dev, mcasp);
2018
2019 mcasp_reparent_fck(pdev);
2020
2021 ret = devm_snd_soc_register_component(&pdev->dev,
2022 &davinci_mcasp_component,
2023 &davinci_mcasp_dai[pdata->op_mode], 1);
2024
2025 if (ret != 0)
2026 goto err;
2027
2028 ret = davinci_mcasp_get_dma_type(mcasp);
2029 switch (ret) {
2030 case PCM_EDMA:
2031 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2032 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2033 IS_MODULE(CONFIG_SND_EDMA_SOC))
2034 ret = edma_pcm_platform_register(&pdev->dev);
2035 #else
2036 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2037 ret = -EINVAL;
2038 goto err;
2039 #endif
2040 break;
2041 case PCM_SDMA:
2042 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
2043 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2044 IS_MODULE(CONFIG_SND_OMAP_SOC))
2045 ret = omap_pcm_platform_register(&pdev->dev);
2046 #else
2047 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2048 ret = -EINVAL;
2049 goto err;
2050 #endif
2051 break;
2052 default:
2053 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2054 case -EPROBE_DEFER:
2055 goto err;
2056 break;
2057 }
2058
2059 if (ret) {
2060 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2061 goto err;
2062 }
2063
2064 return 0;
2065
2066 err:
2067 pm_runtime_disable(&pdev->dev);
2068 return ret;
2069 }
2070
2071 static int davinci_mcasp_remove(struct platform_device *pdev)
2072 {
2073 pm_runtime_disable(&pdev->dev);
2074
2075 return 0;
2076 }
2077
2078 static struct platform_driver davinci_mcasp_driver = {
2079 .probe = davinci_mcasp_probe,
2080 .remove = davinci_mcasp_remove,
2081 .driver = {
2082 .name = "davinci-mcasp",
2083 .of_match_table = mcasp_dt_ids,
2084 },
2085 };
2086
2087 module_platform_driver(davinci_mcasp_driver);
2088
2089 MODULE_AUTHOR("Steve Chen");
2090 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2091 MODULE_LICENSE("GPL");
Linux with added FPC-III support