include/drm/i915_pciids.h

   1 /*
   2  * Copyright 2013 Intel Corporation
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25 #ifndef _I915_PCIIDS_H
  26 #define _I915_PCIIDS_H
  27
  28 /*
  29  * A pci_device_id struct {
  30  *      __u32 vendor, device;
  31  *      __u32 subvendor, subdevice;
  32  *      __u32 class, class_mask;
  33  *      kernel_ulong_t driver_data;
  34  * };
  35  * Don't use C99 here because "class" is reserved and we want to
  36  * give userspace flexibility.
  37  */
  38 #define INTEL_VGA_DEVICE(id, info) {            \
  39         0x8086, id,                             \
  40         ~0, ~0,                                 \
  41         0x030000, 0xff0000,                     \
  42         (unsigned long) info }
  43
  44 #define INTEL_QUANTA_VGA_DEVICE(info) {         \
  45         0x8086, 0x16a,                          \
  46         0x152d, 0x8990,                         \
  47         0x030000, 0xff0000,                     \
  48         (unsigned long) info }
  49
  50 #define INTEL_I810_IDS(info)                                    \
  51         INTEL_VGA_DEVICE(0x7121, info), /* I810 */              \
  52         INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */        \
  53         INTEL_VGA_DEVICE(0x7125, info)  /* I810_E */
  54
  55 #define INTEL_I815_IDS(info)                                    \
  56         INTEL_VGA_DEVICE(0x1132, info)  /* I815*/
  57
  58 #define INTEL_I830_IDS(info)                            \
  59         INTEL_VGA_DEVICE(0x3577, info)
  60
  61 #define INTEL_I845G_IDS(info)                           \
  62         INTEL_VGA_DEVICE(0x2562, info)
  63
  64 #define INTEL_I85X_IDS(info)                            \
  65         INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
  66         INTEL_VGA_DEVICE(0x358e, info)
  67
  68 #define INTEL_I865G_IDS(info)                           \
  69         INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
  70
  71 #define INTEL_I915G_IDS(info)                           \
  72         INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
  73         INTEL_VGA_DEVICE(0x258a, info)  /* E7221_G */
  74
  75 #define INTEL_I915GM_IDS(info)                          \
  76         INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
  77
  78 #define INTEL_I945G_IDS(info)                           \
  79         INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
  80
  81 #define INTEL_I945GM_IDS(info)                          \
  82         INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
  83         INTEL_VGA_DEVICE(0x27ae, info)  /* I945_GME */
  84
  85 #define INTEL_I965G_IDS(info)                           \
  86         INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */   \
  87         INTEL_VGA_DEVICE(0x2982, info), /* G35_G */     \
  88         INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */    \
  89         INTEL_VGA_DEVICE(0x29a2, info)  /* I965_G */
  90
  91 #define INTEL_G33_IDS(info)                             \
  92         INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
  93         INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
  94         INTEL_VGA_DEVICE(0x29d2, info)  /* Q33_G */
  95
  96 #define INTEL_I965GM_IDS(info)                          \
  97         INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
  98         INTEL_VGA_DEVICE(0x2a12, info)  /* I965_GME */
  99
 100 #define INTEL_GM45_IDS(info)                            \
 101         INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
 102
 103 #define INTEL_G45_IDS(info)                             \
 104         INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
 105         INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
 106         INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
 107         INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
 108         INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
 109         INTEL_VGA_DEVICE(0x2e92, info)  /* B43_G.1 */
 110
 111 #define INTEL_PINEVIEW_IDS(info)                        \
 112         INTEL_VGA_DEVICE(0xa001, info),                 \
 113         INTEL_VGA_DEVICE(0xa011, info)
 114
 115 #define INTEL_IRONLAKE_D_IDS(info) \
 116         INTEL_VGA_DEVICE(0x0042, info)
 117
 118 #define INTEL_IRONLAKE_M_IDS(info) \
 119         INTEL_VGA_DEVICE(0x0046, info)
 120
 121 #define INTEL_SNB_D_GT1_IDS(info) \
 122         INTEL_VGA_DEVICE(0x0102, info), \
 123         INTEL_VGA_DEVICE(0x010A, info)
 124
 125 #define INTEL_SNB_D_GT2_IDS(info) \
 126         INTEL_VGA_DEVICE(0x0112, info), \
 127         INTEL_VGA_DEVICE(0x0122, info)
 128
 129 #define INTEL_SNB_D_IDS(info) \
 130         INTEL_SNB_D_GT1_IDS(info), \
 131         INTEL_SNB_D_GT2_IDS(info)
 132
 133 #define INTEL_SNB_M_GT1_IDS(info) \
 134         INTEL_VGA_DEVICE(0x0106, info)
 135
 136 #define INTEL_SNB_M_GT2_IDS(info) \
 137         INTEL_VGA_DEVICE(0x0116, info), \
 138         INTEL_VGA_DEVICE(0x0126, info)
 139
 140 #define INTEL_SNB_M_IDS(info) \
 141         INTEL_SNB_M_GT1_IDS(info), \
 142         INTEL_SNB_M_GT2_IDS(info)
 143
 144 #define INTEL_IVB_M_GT1_IDS(info) \
 145         INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
 146
 147 #define INTEL_IVB_M_GT2_IDS(info) \
 148         INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
 149
 150 #define INTEL_IVB_M_IDS(info) \
 151         INTEL_IVB_M_GT1_IDS(info), \
 152         INTEL_IVB_M_GT2_IDS(info)
 153
 154 #define INTEL_IVB_D_GT1_IDS(info) \
 155         INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
 156         INTEL_VGA_DEVICE(0x015a, info)  /* GT1 server */
 157
 158 #define INTEL_IVB_D_GT2_IDS(info) \
 159         INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
 160         INTEL_VGA_DEVICE(0x016a, info)  /* GT2 server */
 161
 162 #define INTEL_IVB_D_IDS(info) \
 163         INTEL_IVB_D_GT1_IDS(info), \
 164         INTEL_IVB_D_GT2_IDS(info)
 165
 166 #define INTEL_IVB_Q_IDS(info) \
 167         INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
 168
 169 #define INTEL_HSW_GT1_IDS(info) \
 170         INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
 171         INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
 172         INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
 173         INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
 174         INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
 175         INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
 176         INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
 177         INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
 178         INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
 179         INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
 180         INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
 181         INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
 182         INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
 183         INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
 184         INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
 185         INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
 186         INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
 187         INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
 188         INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
 189         INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
 190
 191 #define INTEL_HSW_GT2_IDS(info) \
 192         INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
 193         INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
 194         INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
 195         INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
 196         INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
 197         INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
 198         INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
 199         INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
 200         INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
 201         INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
 202         INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
 203         INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
 204         INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
 205         INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
 206         INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
 207         INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
 208         INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
 209         INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
 210         INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
 211         INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
 212         INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
 213
 214 #define INTEL_HSW_GT3_IDS(info) \
 215         INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
 216         INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
 217         INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
 218         INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
 219         INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
 220         INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
 221         INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
 222         INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
 223         INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
 224         INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
 225         INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
 226         INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
 227         INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
 228         INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
 229         INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
 230         INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
 231         INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
 232         INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
 233         INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
 234
 235 #define INTEL_HSW_IDS(info) \
 236         INTEL_HSW_GT1_IDS(info), \
 237         INTEL_HSW_GT2_IDS(info), \
 238         INTEL_HSW_GT3_IDS(info)
 239
 240 #define INTEL_VLV_IDS(info) \
 241         INTEL_VGA_DEVICE(0x0f30, info), \
 242         INTEL_VGA_DEVICE(0x0f31, info), \
 243         INTEL_VGA_DEVICE(0x0f32, info), \
 244         INTEL_VGA_DEVICE(0x0f33, info), \
 245         INTEL_VGA_DEVICE(0x0157, info), \
 246         INTEL_VGA_DEVICE(0x0155, info)
 247
 248 #define INTEL_BDW_GT1_IDS(info)  \
 249         INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 250         INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
 251         INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
 252         INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
 253         INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 254         INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */
 255
 256 #define INTEL_BDW_GT2_IDS(info)  \
 257         INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */  \
 258         INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
 259         INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
 260         INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
 261         INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 262         INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
 263
 264 #define INTEL_BDW_GT3_IDS(info) \
 265         INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
 266         INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
 267         INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
 268         INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
 269         INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
 270         INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
 271
 272 #define INTEL_BDW_RSVD_IDS(info) \
 273         INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
 274         INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
 275         INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
 276         INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
 277         INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
 278         INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
 279
 280 #define INTEL_BDW_IDS(info) \
 281         INTEL_BDW_GT1_IDS(info), \
 282         INTEL_BDW_GT2_IDS(info), \
 283         INTEL_BDW_GT3_IDS(info), \
 284         INTEL_BDW_RSVD_IDS(info)
 285
 286 #define INTEL_CHV_IDS(info) \
 287         INTEL_VGA_DEVICE(0x22b0, info), \
 288         INTEL_VGA_DEVICE(0x22b1, info), \
 289         INTEL_VGA_DEVICE(0x22b2, info), \
 290         INTEL_VGA_DEVICE(0x22b3, info)
 291
 292 #define INTEL_SKL_GT1_IDS(info) \
 293         INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
 294         INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
 295         INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
 296         INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
 297         INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
 298
 299 #define INTEL_SKL_GT2_IDS(info) \
 300         INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
 301         INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
 302         INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
 303         INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
 304         INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 305         INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
 306         INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
 307
 308 #define INTEL_SKL_GT3_IDS(info) \
 309         INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
 310         INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
 311         INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
 312         INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
 313         INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
 314
 315 #define INTEL_SKL_GT4_IDS(info) \
 316         INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
 317         INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
 318         INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
 319         INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
 320         INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
 321
 322 #define INTEL_SKL_IDS(info)      \
 323         INTEL_SKL_GT1_IDS(info), \
 324         INTEL_SKL_GT2_IDS(info), \
 325         INTEL_SKL_GT3_IDS(info), \
 326         INTEL_SKL_GT4_IDS(info)
 327
 328 #define INTEL_BXT_IDS(info) \
 329         INTEL_VGA_DEVICE(0x0A84, info), \
 330         INTEL_VGA_DEVICE(0x1A84, info), \
 331         INTEL_VGA_DEVICE(0x1A85, info), \
 332         INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
 333         INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
 334
 335 #define INTEL_GLK_IDS(info) \
 336         INTEL_VGA_DEVICE(0x3184, info), \
 337         INTEL_VGA_DEVICE(0x3185, info)
 338
 339 #define INTEL_KBL_GT1_IDS(info) \
 340         INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
 341         INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
 342         INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
 343         INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
 344         INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 345         INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 346         INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 347         INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
 348
 349 #define INTEL_KBL_GT2_IDS(info) \
 350         INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
 351         INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 352         INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
 353         INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
 354         INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
 355         INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 356         INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
 357         INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
 358
 359 #define INTEL_KBL_GT3_IDS(info) \
 360         INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
 361         INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
 362         INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
 363
 364 #define INTEL_KBL_GT4_IDS(info) \
 365         INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
 366
 367 #define INTEL_KBL_IDS(info) \
 368         INTEL_KBL_GT1_IDS(info), \
 369         INTEL_KBL_GT2_IDS(info), \
 370         INTEL_KBL_GT3_IDS(info), \
 371         INTEL_KBL_GT4_IDS(info)
 372
 373 /* CFL S */
 374 #define INTEL_CFL_S_GT1_IDS(info) \
 375         INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
 376         INTEL_VGA_DEVICE(0x3E93, info)  /* SRV GT1 */
 377
 378 #define INTEL_CFL_S_GT2_IDS(info) \
 379         INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
 380         INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
 381         INTEL_VGA_DEVICE(0x3E96, info)  /* SRV GT2 */
 382
 383 /* CFL H */
 384 #define INTEL_CFL_H_GT2_IDS(info) \
 385         INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
 386         INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
 387
 388 /* CFL U */
 389 #define INTEL_CFL_U_GT3_IDS(info) \
 390         INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
 391         INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
 392         INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
 393         INTEL_VGA_DEVICE(0x3EA5, info)  /* ULT GT3 */
 394
 395 #define INTEL_CFL_IDS(info) \
 396         INTEL_CFL_S_GT1_IDS(info), \
 397         INTEL_CFL_S_GT2_IDS(info), \
 398         INTEL_CFL_H_GT2_IDS(info), \
 399         INTEL_CFL_U_GT3_IDS(info)
 400
 401 /* CNL U 2+2 */
 402 #define INTEL_CNL_U_GT2_IDS(info) \
 403         INTEL_VGA_DEVICE(0x5A52, info), \
 404         INTEL_VGA_DEVICE(0x5A5A, info), \
 405         INTEL_VGA_DEVICE(0x5A42, info), \
 406         INTEL_VGA_DEVICE(0x5A4A, info)
 407
 408 /* CNL Y 2+2 */
 409 #define INTEL_CNL_Y_GT2_IDS(info) \
 410         INTEL_VGA_DEVICE(0x5A51, info), \
 411         INTEL_VGA_DEVICE(0x5A59, info), \
 412         INTEL_VGA_DEVICE(0x5A41, info), \
 413         INTEL_VGA_DEVICE(0x5A49, info), \
 414         INTEL_VGA_DEVICE(0x5A71, info), \
 415         INTEL_VGA_DEVICE(0x5A79, info)
 416
 417 #define INTEL_CNL_IDS(info) \
 418         INTEL_CNL_U_GT2_IDS(info), \
 419         INTEL_CNL_Y_GT2_IDS(info)
 420
 421 #endif /* _I915_PCIIDS_H */