UHCI: don't stop at an Iso error
[linux/fpc-iii.git] / include / asm-powerpc / pgtable-4k.h
blobe7036155672e57bb0d9b6e60c0d9f1ee1930be89
1 /*
2 * Entries per page directory level. The PTE level must use a 64b record
3 * for each page table entry. The PMD and PGD level use a 32b record for
4 * each entry by assuming that each entry is page aligned.
5 */
6 #define PTE_INDEX_SIZE 9
7 #define PMD_INDEX_SIZE 7
8 #define PUD_INDEX_SIZE 7
9 #define PGD_INDEX_SIZE 9
11 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
12 #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
13 #define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
14 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
16 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
17 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
18 #define PTRS_PER_PUD (1 << PMD_INDEX_SIZE)
19 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
21 /* PMD_SHIFT determines what a second-level page table entry can map */
22 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
23 #define PMD_SIZE (1UL << PMD_SHIFT)
24 #define PMD_MASK (~(PMD_SIZE-1))
26 /* With 4k base page size, hugepage PTEs go at the PMD level */
27 #define MIN_HUGEPTE_SHIFT PMD_SHIFT
29 /* PUD_SHIFT determines what a third-level page table entry can map */
30 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
31 #define PUD_SIZE (1UL << PUD_SHIFT)
32 #define PUD_MASK (~(PUD_SIZE-1))
34 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
35 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
36 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
37 #define PGDIR_MASK (~(PGDIR_SIZE-1))
39 /* PTE bits */
40 #define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
41 #define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
42 #define _PAGE_F_SECOND _PAGE_SECONDARY
43 #define _PAGE_F_GIX _PAGE_GROUP_IX
45 /* PTE flags to conserve for HPTE identification */
46 #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
47 _PAGE_SECONDARY | _PAGE_GROUP_IX)
49 /* PAGE_MASK gives the right answer below, but only by accident */
50 /* It should be preserving the high 48 bits and then specifically */
51 /* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
52 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
53 _PAGE_HPTEFLAGS)
55 /* Bits to mask out from a PMD to get to the PTE page */
56 #define PMD_MASKED_BITS 0
57 /* Bits to mask out from a PUD to get to the PMD page */
58 #define PUD_MASKED_BITS 0
59 /* Bits to mask out from a PGD to get to the PUD page */
60 #define PGD_MASKED_BITS 0
62 /* shift to put page number into pte */
63 #define PTE_RPN_SHIFT (17)
65 #ifdef STRICT_MM_TYPECHECKS
66 #define __real_pte(e,p) ((real_pte_t){(e)})
67 #define __rpte_to_pte(r) ((r).pte)
68 #else
69 #define __real_pte(e,p) (e)
70 #define __rpte_to_pte(r) (__pte(r))
71 #endif
72 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
74 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
75 do { \
76 index = 0; \
77 shift = mmu_psize_defs[psize].shift; \
79 #define pte_iterate_hashed_end() } while(0)
81 #define pte_pagesize_index(pte) MMU_PAGE_4K
84 * 4-level page tables related bits
87 #define pgd_none(pgd) (!pgd_val(pgd))
88 #define pgd_bad(pgd) (pgd_val(pgd) == 0)
89 #define pgd_present(pgd) (pgd_val(pgd) != 0)
90 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0)
91 #define pgd_page(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS)
93 #define pud_offset(pgdp, addr) \
94 (((pud_t *) pgd_page(*(pgdp))) + \
95 (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
97 #define pud_ERROR(e) \
98 printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))