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media: stv06xx: add missing descriptor sanity checks
[linux/fpc-iii.git] / sound / soc / ti / davinci-mcasp.c
blob8e5371801d88d22203af71cf23bf514bb88b8e09
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 *
5 * Multi-channel Audio Serial Port Driver
6 *
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
8 * Suresh Rajashekara <suresh.r@ti.com>
9 * Steve Chen <schen@.mvista.com>
10 *
11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12 * Copyright: (C) 2009 Texas Instruments, India
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <linux/clk.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/of.h>
24 #include <linux/of_platform.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_data/davinci_asp.h>
27 #include <linux/math64.h>
28 #include <linux/bitmap.h>
29 #include <linux/gpio/driver.h>
30
31 #include <sound/asoundef.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/dmaengine_pcm.h>
38
39 #include "edma-pcm.h"
40 #include "sdma-pcm.h"
41 #include "davinci-mcasp.h"
42
43 #define MCASP_MAX_AFIFO_DEPTH 64
44
45 #ifdef CONFIG_PM
46 static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_PFUNC_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
61 };
62
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
67 bool pm_state;
68 };
69 #endif
70
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
73 int serializers;
74 };
75
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
78 void __iomem *base;
79 u32 fifo_base;
80 struct device *dev;
81 struct snd_pcm_substream *substreams[2];
82 unsigned int dai_fmt;
83
84 /* McASP specific data */
85 int tdm_slots;
86 u32 tdm_mask[2];
87 int slot_width;
88 u8 op_mode;
89 u8 dismod;
90 u8 num_serializer;
91 u8 *serial_dir;
92 u8 version;
93 u8 bclk_div;
94 int streams;
95 u32 irq_request[2];
96 int dma_request[2];
97
98 int sysclk_freq;
99 bool bclk_master;
100 u32 auxclk_fs_ratio;
101
102 unsigned long pdir; /* Pin direction bitfield */
103
104 /* McASP FIFO related */
105 u8 txnumevt;
106 u8 rxnumevt;
107
108 bool dat_port;
109
110 /* Used for comstraint setting on the second stream */
111 u32 channels;
112 int max_format_width;
113 u8 active_serializers[2];
114
115 #ifdef CONFIG_GPIOLIB
116 struct gpio_chip gpio_chip;
117 #endif
118
119 #ifdef CONFIG_PM
120 struct davinci_mcasp_context context;
121 #endif
122
123 struct davinci_mcasp_ruledata ruledata[2];
124 struct snd_pcm_hw_constraint_list chconstr[2];
125 };
126
127 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
128 u32 val)
129 {
130 void __iomem *reg = mcasp->base + offset;
131 __raw_writel(__raw_readl(reg) | val, reg);
132 }
133
134 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
135 u32 val)
136 {
137 void __iomem *reg = mcasp->base + offset;
138 __raw_writel((__raw_readl(reg) & ~(val)), reg);
139 }
140
141 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
142 u32 val, u32 mask)
143 {
144 void __iomem *reg = mcasp->base + offset;
145 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
146 }
147
148 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
149 u32 val)
150 {
151 __raw_writel(val, mcasp->base + offset);
152 }
153
154 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
155 {
156 return (u32)__raw_readl(mcasp->base + offset);
157 }
158
159 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
160 {
161 int i = 0;
162
163 mcasp_set_bits(mcasp, ctl_reg, val);
164
165 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
166 /* loop count is to avoid the lock-up */
167 for (i = 0; i < 1000; i++) {
168 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
169 break;
170 }
171
172 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
173 printk(KERN_ERR "GBLCTL write error\n");
174 }
175
176 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
177 {
178 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
179 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
180
181 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
182 }
183
184 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
185 {
186 u32 bit = PIN_BIT_AMUTE;
187
188 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
189 if (enable)
190 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
191 else
192 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
193 }
194 }
195
196 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
197 {
198 u32 bit;
199
200 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
201 if (enable)
202 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
203 else
204 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
205 }
206 }
207
208 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
209 {
210 if (mcasp->rxnumevt) { /* enable FIFO */
211 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
212
213 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
214 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
215 }
216
217 /* Start clocks */
218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
220 /*
221 * When ASYNC == 0 the transmit and receive sections operate
222 * synchronously from the transmit clock and frame sync. We need to make
223 * sure that the TX signlas are enabled when starting reception.
224 */
225 if (mcasp_is_synchronous(mcasp)) {
226 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
227 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
228 mcasp_set_clk_pdir(mcasp, true);
229 }
230
231 /* Activate serializer(s) */
232 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
234 /* Release RX state machine */
235 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
236 /* Release Frame Sync generator */
237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
238 if (mcasp_is_synchronous(mcasp))
239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
240
241 /* enable receive IRQs */
242 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
243 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
244 }
245
246 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
247 {
248 u32 cnt;
249
250 if (mcasp->txnumevt) { /* enable FIFO */
251 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
252
253 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
254 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
255 }
256
257 /* Start clocks */
258 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
259 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
260 mcasp_set_clk_pdir(mcasp, true);
261
262 /* Activate serializer(s) */
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
264 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
265
266 /* wait for XDATA to be cleared */
267 cnt = 0;
268 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
269 (cnt < 100000))
270 cnt++;
271
272 mcasp_set_axr_pdir(mcasp, true);
273
274 /* Release TX state machine */
275 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
276 /* Release Frame Sync generator */
277 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
278
279 /* enable transmit IRQs */
280 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
281 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
282 }
283
284 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
285 {
286 mcasp->streams++;
287
288 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
289 mcasp_start_tx(mcasp);
290 else
291 mcasp_start_rx(mcasp);
292 }
293
294 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
295 {
296 /* disable IRQ sources */
297 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
298 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
299
300 /*
301 * In synchronous mode stop the TX clocks if no other stream is
302 * running
303 */
304 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
305 mcasp_set_clk_pdir(mcasp, false);
306 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
307 }
308
309 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
310 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
311
312 if (mcasp->rxnumevt) { /* disable FIFO */
313 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
314
315 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
316 }
317 }
318
319 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
320 {
321 u32 val = 0;
322
323 /* disable IRQ sources */
324 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
325 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
326
327 /*
328 * In synchronous mode keep TX clocks running if the capture stream is
329 * still running.
330 */
331 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
332 val = TXHCLKRST | TXCLKRST | TXFSRST;
333 else
334 mcasp_set_clk_pdir(mcasp, false);
335
336
337 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
338 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
339
340 if (mcasp->txnumevt) { /* disable FIFO */
341 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
342
343 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
344 }
345
346 mcasp_set_axr_pdir(mcasp, false);
347 }
348
349 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
350 {
351 mcasp->streams--;
352
353 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
354 mcasp_stop_tx(mcasp);
355 else
356 mcasp_stop_rx(mcasp);
357 }
358
359 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
360 {
361 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
362 struct snd_pcm_substream *substream;
363 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
364 u32 handled_mask = 0;
365 u32 stat;
366
367 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
368 if (stat & XUNDRN & irq_mask) {
369 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
370 handled_mask |= XUNDRN;
371
372 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
373 if (substream)
374 snd_pcm_stop_xrun(substream);
375 }
376
377 if (!handled_mask)
378 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
379 stat);
380
381 if (stat & XRERR)
382 handled_mask |= XRERR;
383
384 /* Ack the handled event only */
385 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
386
387 return IRQ_RETVAL(handled_mask);
388 }
389
390 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
391 {
392 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
393 struct snd_pcm_substream *substream;
394 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
395 u32 handled_mask = 0;
396 u32 stat;
397
398 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
399 if (stat & ROVRN & irq_mask) {
400 dev_warn(mcasp->dev, "Receive buffer overflow\n");
401 handled_mask |= ROVRN;
402
403 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
404 if (substream)
405 snd_pcm_stop_xrun(substream);
406 }
407
408 if (!handled_mask)
409 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
410 stat);
411
412 if (stat & XRERR)
413 handled_mask |= XRERR;
414
415 /* Ack the handled event only */
416 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
417
418 return IRQ_RETVAL(handled_mask);
419 }
420
421 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
422 {
423 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
424 irqreturn_t ret = IRQ_NONE;
425
426 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
427 ret = davinci_mcasp_tx_irq_handler(irq, data);
428
429 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
430 ret |= davinci_mcasp_rx_irq_handler(irq, data);
431
432 return ret;
433 }
434
435 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
436 unsigned int fmt)
437 {
438 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
439 int ret = 0;
440 u32 data_delay;
441 bool fs_pol_rising;
442 bool inv_fs = false;
443
444 if (!fmt)
445 return 0;
446
447 pm_runtime_get_sync(mcasp->dev);
448 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
449 case SND_SOC_DAIFMT_DSP_A:
450 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
451 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
452 /* 1st data bit occur one ACLK cycle after the frame sync */
453 data_delay = 1;
454 break;
455 case SND_SOC_DAIFMT_DSP_B:
456 case SND_SOC_DAIFMT_AC97:
457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
459 /* No delay after FS */
460 data_delay = 0;
461 break;
462 case SND_SOC_DAIFMT_I2S:
463 /* configure a full-word SYNC pulse (LRCLK) */
464 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
466 /* 1st data bit occur one ACLK cycle after the frame sync */
467 data_delay = 1;
468 /* FS need to be inverted */
469 inv_fs = true;
470 break;
471 case SND_SOC_DAIFMT_RIGHT_J:
472 case SND_SOC_DAIFMT_LEFT_J:
473 /* configure a full-word SYNC pulse (LRCLK) */
474 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
476 /* No delay after FS */
477 data_delay = 0;
478 break;
479 default:
480 ret = -EINVAL;
481 goto out;
482 }
483
484 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
485 FSXDLY(3));
486 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
487 FSRDLY(3));
488
489 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
490 case SND_SOC_DAIFMT_CBS_CFS:
491 /* codec is clock and frame slave */
492 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
493 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
494
495 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
496 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
497
498 /* BCLK */
499 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
500 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
501 /* Frame Sync */
502 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
503 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
504
505 mcasp->bclk_master = 1;
506 break;
507 case SND_SOC_DAIFMT_CBS_CFM:
508 /* codec is clock slave and frame master */
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
510 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
511
512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
513 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
514
515 /* BCLK */
516 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
517 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
518 /* Frame Sync */
519 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
520 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
521
522 mcasp->bclk_master = 1;
523 break;
524 case SND_SOC_DAIFMT_CBM_CFS:
525 /* codec is clock master and frame slave */
526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
528
529 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
530 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
531
532 /* BCLK */
533 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
534 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
535 /* Frame Sync */
536 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
537 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
538
539 mcasp->bclk_master = 0;
540 break;
541 case SND_SOC_DAIFMT_CBM_CFM:
542 /* codec is clock and frame master */
543 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
545
546 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
548
549 /* BCLK */
550 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
551 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
552 /* Frame Sync */
553 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
554 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
555
556 mcasp->bclk_master = 0;
557 break;
558 default:
559 ret = -EINVAL;
560 goto out;
561 }
562
563 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
564 case SND_SOC_DAIFMT_IB_NF:
565 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
567 fs_pol_rising = true;
568 break;
569 case SND_SOC_DAIFMT_NB_IF:
570 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
572 fs_pol_rising = false;
573 break;
574 case SND_SOC_DAIFMT_IB_IF:
575 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
576 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
577 fs_pol_rising = false;
578 break;
579 case SND_SOC_DAIFMT_NB_NF:
580 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
581 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
582 fs_pol_rising = true;
583 break;
584 default:
585 ret = -EINVAL;
586 goto out;
587 }
588
589 if (inv_fs)
590 fs_pol_rising = !fs_pol_rising;
591
592 if (fs_pol_rising) {
593 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
594 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
595 } else {
596 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
597 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
598 }
599
600 mcasp->dai_fmt = fmt;
601 out:
602 pm_runtime_put(mcasp->dev);
603 return ret;
604 }
605
606 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
607 int div, bool explicit)
608 {
609 pm_runtime_get_sync(mcasp->dev);
610 switch (div_id) {
611 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
612 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
613 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
614 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
615 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
616 break;
617
618 case MCASP_CLKDIV_BCLK: /* BCLK divider */
619 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
620 ACLKXDIV(div - 1), ACLKXDIV_MASK);
621 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
622 ACLKRDIV(div - 1), ACLKRDIV_MASK);
623 if (explicit)
624 mcasp->bclk_div = div;
625 break;
626
627 case MCASP_CLKDIV_BCLK_FS_RATIO:
628 /*
629 * BCLK/LRCLK ratio descries how many bit-clock cycles
630 * fit into one frame. The clock ratio is given for a
631 * full period of data (for I2S format both left and
632 * right channels), so it has to be divided by number
633 * of tdm-slots (for I2S - divided by 2).
634 * Instead of storing this ratio, we calculate a new
635 * tdm_slot width by dividing the the ratio by the
636 * number of configured tdm slots.
637 */
638 mcasp->slot_width = div / mcasp->tdm_slots;
639 if (div % mcasp->tdm_slots)
640 dev_warn(mcasp->dev,
641 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
642 __func__, div, mcasp->tdm_slots);
643 break;
644
645 default:
646 return -EINVAL;
647 }
648
649 pm_runtime_put(mcasp->dev);
650 return 0;
651 }
652
653 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
654 int div)
655 {
656 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
657
658 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
659 }
660
661 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
662 unsigned int freq, int dir)
663 {
664 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
665
666 pm_runtime_get_sync(mcasp->dev);
667 if (dir == SND_SOC_CLOCK_OUT) {
668 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
669 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
670 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
671 } else {
672 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
673 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
674 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
675 }
676
677 mcasp->sysclk_freq = freq;
678
679 pm_runtime_put(mcasp->dev);
680 return 0;
681 }
682
683 /* All serializers must have equal number of channels */
684 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
685 int serializers)
686 {
687 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
688 unsigned int *list = (unsigned int *) cl->list;
689 int slots = mcasp->tdm_slots;
690 int i, count = 0;
691
692 if (mcasp->tdm_mask[stream])
693 slots = hweight32(mcasp->tdm_mask[stream]);
694
695 for (i = 1; i <= slots; i++)
696 list[count++] = i;
697
698 for (i = 2; i <= serializers; i++)
699 list[count++] = i*slots;
700
701 cl->count = count;
702
703 return 0;
704 }
705
706 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
707 {
708 int rx_serializers = 0, tx_serializers = 0, ret, i;
709
710 for (i = 0; i < mcasp->num_serializer; i++)
711 if (mcasp->serial_dir[i] == TX_MODE)
712 tx_serializers++;
713 else if (mcasp->serial_dir[i] == RX_MODE)
714 rx_serializers++;
715
716 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
717 tx_serializers);
718 if (ret)
719 return ret;
720
721 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
722 rx_serializers);
723
724 return ret;
725 }
726
727
728 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
729 unsigned int tx_mask,
730 unsigned int rx_mask,
731 int slots, int slot_width)
732 {
733 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
734
735 dev_dbg(mcasp->dev,
736 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
737 __func__, tx_mask, rx_mask, slots, slot_width);
738
739 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
740 dev_err(mcasp->dev,
741 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
742 tx_mask, rx_mask, slots);
743 return -EINVAL;
744 }
745
746 if (slot_width &&
747 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
748 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
749 __func__, slot_width);
750 return -EINVAL;
751 }
752
753 mcasp->tdm_slots = slots;
754 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
755 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
756 mcasp->slot_width = slot_width;
757
758 return davinci_mcasp_set_ch_constraints(mcasp);
759 }
760
761 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
762 int sample_width)
763 {
764 u32 fmt;
765 u32 tx_rotate, rx_rotate, slot_width;
766 u32 mask = (1ULL << sample_width) - 1;
767
768 if (mcasp->slot_width)
769 slot_width = mcasp->slot_width;
770 else if (mcasp->max_format_width)
771 slot_width = mcasp->max_format_width;
772 else
773 slot_width = sample_width;
774 /*
775 * TX rotation:
776 * right aligned formats: rotate w/ slot_width
777 * left aligned formats: rotate w/ sample_width
778 *
779 * RX rotation:
780 * right aligned formats: no rotation needed
781 * left aligned formats: rotate w/ (slot_width - sample_width)
782 */
783 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
784 SND_SOC_DAIFMT_RIGHT_J) {
785 tx_rotate = (slot_width / 4) & 0x7;
786 rx_rotate = 0;
787 } else {
788 tx_rotate = (sample_width / 4) & 0x7;
789 rx_rotate = (slot_width - sample_width) / 4;
790 }
791
792 /* mapping of the XSSZ bit-field as described in the datasheet */
793 fmt = (slot_width >> 1) - 1;
794
795 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
796 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
797 RXSSZ(0x0F));
798 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
799 TXSSZ(0x0F));
800 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
801 TXROT(7));
802 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
803 RXROT(7));
804 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
805 }
806
807 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
808
809 return 0;
810 }
811
812 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
813 int period_words, int channels)
814 {
815 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
816 int i;
817 u8 tx_ser = 0;
818 u8 rx_ser = 0;
819 u8 slots = mcasp->tdm_slots;
820 u8 max_active_serializers = (channels + slots - 1) / slots;
821 u8 max_rx_serializers, max_tx_serializers;
822 int active_serializers, numevt;
823 u32 reg;
824 /* Default configuration */
825 if (mcasp->version < MCASP_VERSION_3)
826 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
827
828 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
829 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
830 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
831 max_tx_serializers = max_active_serializers;
832 max_rx_serializers =
833 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
834 } else {
835 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
836 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
837 max_tx_serializers =
838 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
839 max_rx_serializers = max_active_serializers;
840 }
841
842 for (i = 0; i < mcasp->num_serializer; i++) {
843 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
844 mcasp->serial_dir[i]);
845 if (mcasp->serial_dir[i] == TX_MODE &&
846 tx_ser < max_tx_serializers) {
847 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
848 mcasp->dismod, DISMOD_MASK);
849 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
850 tx_ser++;
851 } else if (mcasp->serial_dir[i] == RX_MODE &&
852 rx_ser < max_rx_serializers) {
853 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
854 rx_ser++;
855 } else {
856 /* Inactive or unused pin, set it to inactive */
857 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
858 SRMOD_INACTIVE, SRMOD_MASK);
859 /* If unused, set DISMOD for the pin */
860 if (mcasp->serial_dir[i] != INACTIVE_MODE)
861 mcasp_mod_bits(mcasp,
862 DAVINCI_MCASP_XRSRCTL_REG(i),
863 mcasp->dismod, DISMOD_MASK);
864 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
865 }
866 }
867
868 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
869 active_serializers = tx_ser;
870 numevt = mcasp->txnumevt;
871 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
872 } else {
873 active_serializers = rx_ser;
874 numevt = mcasp->rxnumevt;
875 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
876 }
877
878 if (active_serializers < max_active_serializers) {
879 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
880 "enabled in mcasp (%d)\n", channels,
881 active_serializers * slots);
882 return -EINVAL;
883 }
884
885 /* AFIFO is not in use */
886 if (!numevt) {
887 /* Configure the burst size for platform drivers */
888 if (active_serializers > 1) {
889 /*
890 * If more than one serializers are in use we have one
891 * DMA request to provide data for all serializers.
892 * For example if three serializers are enabled the DMA
893 * need to transfer three words per DMA request.
894 */
895 dma_data->maxburst = active_serializers;
896 } else {
897 dma_data->maxburst = 0;
898 }
899
900 goto out;
901 }
902
903 if (period_words % active_serializers) {
904 dev_err(mcasp->dev, "Invalid combination of period words and "
905 "active serializers: %d, %d\n", period_words,
906 active_serializers);
907 return -EINVAL;
908 }
909
910 /*
911 * Calculate the optimal AFIFO depth for platform side:
912 * The number of words for numevt need to be in steps of active
913 * serializers.
914 */
915 numevt = (numevt / active_serializers) * active_serializers;
916
917 while (period_words % numevt && numevt > 0)
918 numevt -= active_serializers;
919 if (numevt <= 0)
920 numevt = active_serializers;
921
922 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
923 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
924
925 /* Configure the burst size for platform drivers */
926 if (numevt == 1)
927 numevt = 0;
928 dma_data->maxburst = numevt;
929
930 out:
931 mcasp->active_serializers[stream] = active_serializers;
932
933 return 0;
934 }
935
936 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
937 int channels)
938 {
939 int i, active_slots;
940 int total_slots;
941 int active_serializers;
942 u32 mask = 0;
943 u32 busel = 0;
944
945 total_slots = mcasp->tdm_slots;
946
947 /*
948 * If more than one serializer is needed, then use them with
949 * all the specified tdm_slots. Otherwise, one serializer can
950 * cope with the transaction using just as many slots as there
951 * are channels in the stream.
952 */
953 if (mcasp->tdm_mask[stream]) {
954 active_slots = hweight32(mcasp->tdm_mask[stream]);
955 active_serializers = (channels + active_slots - 1) /
956 active_slots;
957 if (active_serializers == 1)
958 active_slots = channels;
959 for (i = 0; i < total_slots; i++) {
960 if ((1 << i) & mcasp->tdm_mask[stream]) {
961 mask |= (1 << i);
962 if (--active_slots <= 0)
963 break;
964 }
965 }
966 } else {
967 active_serializers = (channels + total_slots - 1) / total_slots;
968 if (active_serializers == 1)
969 active_slots = channels;
970 else
971 active_slots = total_slots;
972
973 for (i = 0; i < active_slots; i++)
974 mask |= (1 << i);
975 }
976
977 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
978
979 if (!mcasp->dat_port)
980 busel = TXSEL;
981
982 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
983 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
984 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
985 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
986 FSXMOD(total_slots), FSXMOD(0x1FF));
987 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
988 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
989 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
990 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
991 FSRMOD(total_slots), FSRMOD(0x1FF));
992 /*
993 * If McASP is set to be TX/RX synchronous and the playback is
994 * not running already we need to configure the TX slots in
995 * order to have correct FSX on the bus
996 */
997 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
998 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
999 FSXMOD(total_slots), FSXMOD(0x1FF));
1000 }
1001
1002 return 0;
1003 }
1004
1005 /* S/PDIF */
1006 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1007 unsigned int rate)
1008 {
1009 u32 cs_value = 0;
1010 u8 *cs_bytes = (u8*) &cs_value;
1011
1012 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1013 and LSB first */
1014 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
1015
1016 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1017 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1018
1019 /* Set the TX tdm : for all the slots */
1020 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1021
1022 /* Set the TX clock controls : div = 1 and internal */
1023 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1024
1025 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1026
1027 /* Only 44100 and 48000 are valid, both have the same setting */
1028 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
1029
1030 /* Enable the DIT */
1031 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1032
1033 /* Set S/PDIF channel status bits */
1034 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1035 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1036
1037 switch (rate) {
1038 case 22050:
1039 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1040 break;
1041 case 24000:
1042 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1043 break;
1044 case 32000:
1045 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1046 break;
1047 case 44100:
1048 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1049 break;
1050 case 48000:
1051 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1052 break;
1053 case 88200:
1054 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1055 break;
1056 case 96000:
1057 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1058 break;
1059 case 176400:
1060 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1061 break;
1062 case 192000:
1063 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1064 break;
1065 default:
1066 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1067 return -EINVAL;
1068 }
1069
1070 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1071 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1072
1073 return 0;
1074 }
1075
1076 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1077 unsigned int sysclk_freq,
1078 unsigned int bclk_freq, bool set)
1079 {
1080 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1081 int div = sysclk_freq / bclk_freq;
1082 int rem = sysclk_freq % bclk_freq;
1083 int error_ppm;
1084 int aux_div = 1;
1085
1086 if (div > (ACLKXDIV_MASK + 1)) {
1087 if (reg & AHCLKXE) {
1088 aux_div = div / (ACLKXDIV_MASK + 1);
1089 if (div % (ACLKXDIV_MASK + 1))
1090 aux_div++;
1091
1092 sysclk_freq /= aux_div;
1093 div = sysclk_freq / bclk_freq;
1094 rem = sysclk_freq % bclk_freq;
1095 } else if (set) {
1096 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1097 sysclk_freq);
1098 }
1099 }
1100
1101 if (rem != 0) {
1102 if (div == 0 ||
1103 ((sysclk_freq / div) - bclk_freq) >
1104 (bclk_freq - (sysclk_freq / (div+1)))) {
1105 div++;
1106 rem = rem - bclk_freq;
1107 }
1108 }
1109 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1110 (int)bclk_freq)) / div - 1000000;
1111
1112 if (set) {
1113 if (error_ppm)
1114 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1115 error_ppm);
1116
1117 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1118 if (reg & AHCLKXE)
1119 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1120 aux_div, 0);
1121 }
1122
1123 return error_ppm;
1124 }
1125
1126 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1127 {
1128 if (!mcasp->txnumevt)
1129 return 0;
1130
1131 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1132 }
1133
1134 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1135 {
1136 if (!mcasp->rxnumevt)
1137 return 0;
1138
1139 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1140 }
1141
1142 static snd_pcm_sframes_t davinci_mcasp_delay(
1143 struct snd_pcm_substream *substream,
1144 struct snd_soc_dai *cpu_dai)
1145 {
1146 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1147 u32 fifo_use;
1148
1149 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1150 fifo_use = davinci_mcasp_tx_delay(mcasp);
1151 else
1152 fifo_use = davinci_mcasp_rx_delay(mcasp);
1153
1154 /*
1155 * Divide the used locations with the channel count to get the
1156 * FIFO usage in samples (don't care about partial samples in the
1157 * buffer).
1158 */
1159 return fifo_use / substream->runtime->channels;
1160 }
1161
1162 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1163 struct snd_pcm_hw_params *params,
1164 struct snd_soc_dai *cpu_dai)
1165 {
1166 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1167 int word_length;
1168 int channels = params_channels(params);
1169 int period_size = params_period_size(params);
1170 int ret;
1171
1172 switch (params_format(params)) {
1173 case SNDRV_PCM_FORMAT_U8:
1174 case SNDRV_PCM_FORMAT_S8:
1175 word_length = 8;
1176 break;
1177
1178 case SNDRV_PCM_FORMAT_U16_LE:
1179 case SNDRV_PCM_FORMAT_S16_LE:
1180 word_length = 16;
1181 break;
1182
1183 case SNDRV_PCM_FORMAT_U24_3LE:
1184 case SNDRV_PCM_FORMAT_S24_3LE:
1185 word_length = 24;
1186 break;
1187
1188 case SNDRV_PCM_FORMAT_U24_LE:
1189 case SNDRV_PCM_FORMAT_S24_LE:
1190 word_length = 24;
1191 break;
1192
1193 case SNDRV_PCM_FORMAT_U32_LE:
1194 case SNDRV_PCM_FORMAT_S32_LE:
1195 word_length = 32;
1196 break;
1197
1198 default:
1199 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1200 return -EINVAL;
1201 }
1202
1203 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1204 if (ret)
1205 return ret;
1206
1207 /*
1208 * If mcasp is BCLK master, and a BCLK divider was not provided by
1209 * the machine driver, we need to calculate the ratio.
1210 */
1211 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1212 int slots = mcasp->tdm_slots;
1213 int rate = params_rate(params);
1214 int sbits = params_width(params);
1215
1216 if (mcasp->slot_width)
1217 sbits = mcasp->slot_width;
1218
1219 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1220 rate * sbits * slots, true);
1221 }
1222
1223 ret = mcasp_common_hw_param(mcasp, substream->stream,
1224 period_size * channels, channels);
1225 if (ret)
1226 return ret;
1227
1228 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1229 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1230 else
1231 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1232 channels);
1233
1234 if (ret)
1235 return ret;
1236
1237 davinci_config_channel_size(mcasp, word_length);
1238
1239 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1240 mcasp->channels = channels;
1241 if (!mcasp->max_format_width)
1242 mcasp->max_format_width = word_length;
1243 }
1244
1245 return 0;
1246 }
1247
1248 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1249 int cmd, struct snd_soc_dai *cpu_dai)
1250 {
1251 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1252 int ret = 0;
1253
1254 switch (cmd) {
1255 case SNDRV_PCM_TRIGGER_RESUME:
1256 case SNDRV_PCM_TRIGGER_START:
1257 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1258 davinci_mcasp_start(mcasp, substream->stream);
1259 break;
1260 case SNDRV_PCM_TRIGGER_SUSPEND:
1261 case SNDRV_PCM_TRIGGER_STOP:
1262 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1263 davinci_mcasp_stop(mcasp, substream->stream);
1264 break;
1265
1266 default:
1267 ret = -EINVAL;
1268 }
1269
1270 return ret;
1271 }
1272
1273 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1274 struct snd_pcm_hw_rule *rule)
1275 {
1276 struct davinci_mcasp_ruledata *rd = rule->private;
1277 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1278 struct snd_mask nfmt;
1279 int i, slot_width;
1280
1281 snd_mask_none(&nfmt);
1282 slot_width = rd->mcasp->slot_width;
1283
1284 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1285 if (snd_mask_test(fmt, i)) {
1286 if (snd_pcm_format_width(i) <= slot_width) {
1287 snd_mask_set(&nfmt, i);
1288 }
1289 }
1290 }
1291
1292 return snd_mask_refine(fmt, &nfmt);
1293 }
1294
1295 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
1296 struct snd_pcm_hw_rule *rule)
1297 {
1298 struct davinci_mcasp_ruledata *rd = rule->private;
1299 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1300 struct snd_mask nfmt;
1301 int i, format_width;
1302
1303 snd_mask_none(&nfmt);
1304 format_width = rd->mcasp->max_format_width;
1305
1306 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1307 if (snd_mask_test(fmt, i)) {
1308 if (snd_pcm_format_width(i) == format_width) {
1309 snd_mask_set(&nfmt, i);
1310 }
1311 }
1312 }
1313
1314 return snd_mask_refine(fmt, &nfmt);
1315 }
1316
1317 static const unsigned int davinci_mcasp_dai_rates[] = {
1318 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1319 88200, 96000, 176400, 192000,
1320 };
1321
1322 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1323
1324 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1325 struct snd_pcm_hw_rule *rule)
1326 {
1327 struct davinci_mcasp_ruledata *rd = rule->private;
1328 struct snd_interval *ri =
1329 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1330 int sbits = params_width(params);
1331 int slots = rd->mcasp->tdm_slots;
1332 struct snd_interval range;
1333 int i;
1334
1335 if (rd->mcasp->slot_width)
1336 sbits = rd->mcasp->slot_width;
1337
1338 snd_interval_any(&range);
1339 range.empty = 1;
1340
1341 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1342 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1343 uint bclk_freq = sbits * slots *
1344 davinci_mcasp_dai_rates[i];
1345 unsigned int sysclk_freq;
1346 int ppm;
1347
1348 if (rd->mcasp->auxclk_fs_ratio)
1349 sysclk_freq = davinci_mcasp_dai_rates[i] *
1350 rd->mcasp->auxclk_fs_ratio;
1351 else
1352 sysclk_freq = rd->mcasp->sysclk_freq;
1353
1354 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1355 bclk_freq, false);
1356 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1357 if (range.empty) {
1358 range.min = davinci_mcasp_dai_rates[i];
1359 range.empty = 0;
1360 }
1361 range.max = davinci_mcasp_dai_rates[i];
1362 }
1363 }
1364 }
1365
1366 dev_dbg(rd->mcasp->dev,
1367 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1368 ri->min, ri->max, range.min, range.max, sbits, slots);
1369
1370 return snd_interval_refine(hw_param_interval(params, rule->var),
1371 &range);
1372 }
1373
1374 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1375 struct snd_pcm_hw_rule *rule)
1376 {
1377 struct davinci_mcasp_ruledata *rd = rule->private;
1378 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1379 struct snd_mask nfmt;
1380 int rate = params_rate(params);
1381 int slots = rd->mcasp->tdm_slots;
1382 int i, count = 0;
1383
1384 snd_mask_none(&nfmt);
1385
1386 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1387 if (snd_mask_test(fmt, i)) {
1388 uint sbits = snd_pcm_format_width(i);
1389 unsigned int sysclk_freq;
1390 int ppm;
1391
1392 if (rd->mcasp->auxclk_fs_ratio)
1393 sysclk_freq = rate *
1394 rd->mcasp->auxclk_fs_ratio;
1395 else
1396 sysclk_freq = rd->mcasp->sysclk_freq;
1397
1398 if (rd->mcasp->slot_width)
1399 sbits = rd->mcasp->slot_width;
1400
1401 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1402 sbits * slots * rate,
1403 false);
1404 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1405 snd_mask_set(&nfmt, i);
1406 count++;
1407 }
1408 }
1409 }
1410 dev_dbg(rd->mcasp->dev,
1411 "%d possible sample format for %d Hz and %d tdm slots\n",
1412 count, rate, slots);
1413
1414 return snd_mask_refine(fmt, &nfmt);
1415 }
1416
1417 static int davinci_mcasp_hw_rule_min_periodsize(
1418 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1419 {
1420 struct snd_interval *period_size = hw_param_interval(params,
1421 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1422 struct snd_interval frames;
1423
1424 snd_interval_any(&frames);
1425 frames.min = 64;
1426 frames.integer = 1;
1427
1428 return snd_interval_refine(period_size, &frames);
1429 }
1430
1431 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1432 struct snd_soc_dai *cpu_dai)
1433 {
1434 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1435 struct davinci_mcasp_ruledata *ruledata =
1436 &mcasp->ruledata[substream->stream];
1437 u32 max_channels = 0;
1438 int i, dir, ret;
1439 int tdm_slots = mcasp->tdm_slots;
1440
1441 /* Do not allow more then one stream per direction */
1442 if (mcasp->substreams[substream->stream])
1443 return -EBUSY;
1444
1445 mcasp->substreams[substream->stream] = substream;
1446
1447 if (mcasp->tdm_mask[substream->stream])
1448 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1449
1450 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1451 return 0;
1452
1453 /*
1454 * Limit the maximum allowed channels for the first stream:
1455 * number of serializers for the direction * tdm slots per serializer
1456 */
1457 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1458 dir = TX_MODE;
1459 else
1460 dir = RX_MODE;
1461
1462 for (i = 0; i < mcasp->num_serializer; i++) {
1463 if (mcasp->serial_dir[i] == dir)
1464 max_channels++;
1465 }
1466 ruledata->serializers = max_channels;
1467 ruledata->mcasp = mcasp;
1468 max_channels *= tdm_slots;
1469 /*
1470 * If the already active stream has less channels than the calculated
1471 * limit based on the seirializers * tdm_slots, and only one serializer
1472 * is in use we need to use that as a constraint for the second stream.
1473 * Otherwise (first stream or less allowed channels or more than one
1474 * serializer in use) we use the calculated constraint.
1475 */
1476 if (mcasp->channels && mcasp->channels < max_channels &&
1477 ruledata->serializers == 1)
1478 max_channels = mcasp->channels;
1479 /*
1480 * But we can always allow channels upto the amount of
1481 * the available tdm_slots.
1482 */
1483 if (max_channels < tdm_slots)
1484 max_channels = tdm_slots;
1485
1486 snd_pcm_hw_constraint_minmax(substream->runtime,
1487 SNDRV_PCM_HW_PARAM_CHANNELS,
1488 0, max_channels);
1489
1490 snd_pcm_hw_constraint_list(substream->runtime,
1491 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1492 &mcasp->chconstr[substream->stream]);
1493
1494 if (mcasp->max_format_width) {
1495 /*
1496 * Only allow formats which require same amount of bits on the
1497 * bus as the currently running stream
1498 */
1499 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1500 SNDRV_PCM_HW_PARAM_FORMAT,
1501 davinci_mcasp_hw_rule_format_width,
1502 ruledata,
1503 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1504 if (ret)
1505 return ret;
1506 }
1507 else if (mcasp->slot_width) {
1508 /* Only allow formats require <= slot_width bits on the bus */
1509 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1510 SNDRV_PCM_HW_PARAM_FORMAT,
1511 davinci_mcasp_hw_rule_slot_width,
1512 ruledata,
1513 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1514 if (ret)
1515 return ret;
1516 }
1517
1518 /*
1519 * If we rely on implicit BCLK divider setting we should
1520 * set constraints based on what we can provide.
1521 */
1522 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1523 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1524 SNDRV_PCM_HW_PARAM_RATE,
1525 davinci_mcasp_hw_rule_rate,
1526 ruledata,
1527 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1528 if (ret)
1529 return ret;
1530 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1531 SNDRV_PCM_HW_PARAM_FORMAT,
1532 davinci_mcasp_hw_rule_format,
1533 ruledata,
1534 SNDRV_PCM_HW_PARAM_RATE, -1);
1535 if (ret)
1536 return ret;
1537 }
1538
1539 snd_pcm_hw_rule_add(substream->runtime, 0,
1540 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1541 davinci_mcasp_hw_rule_min_periodsize, NULL,
1542 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1543
1544 return 0;
1545 }
1546
1547 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1548 struct snd_soc_dai *cpu_dai)
1549 {
1550 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1551
1552 mcasp->substreams[substream->stream] = NULL;
1553 mcasp->active_serializers[substream->stream] = 0;
1554
1555 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1556 return;
1557
1558 if (!cpu_dai->active) {
1559 mcasp->channels = 0;
1560 mcasp->max_format_width = 0;
1561 }
1562 }
1563
1564 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1565 .startup = davinci_mcasp_startup,
1566 .shutdown = davinci_mcasp_shutdown,
1567 .trigger = davinci_mcasp_trigger,
1568 .delay = davinci_mcasp_delay,
1569 .hw_params = davinci_mcasp_hw_params,
1570 .set_fmt = davinci_mcasp_set_dai_fmt,
1571 .set_clkdiv = davinci_mcasp_set_clkdiv,
1572 .set_sysclk = davinci_mcasp_set_sysclk,
1573 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1574 };
1575
1576 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1577 {
1578 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1579
1580 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1581 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1582
1583 return 0;
1584 }
1585
1586 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1587
1588 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1589 SNDRV_PCM_FMTBIT_U8 | \
1590 SNDRV_PCM_FMTBIT_S16_LE | \
1591 SNDRV_PCM_FMTBIT_U16_LE | \
1592 SNDRV_PCM_FMTBIT_S24_LE | \
1593 SNDRV_PCM_FMTBIT_U24_LE | \
1594 SNDRV_PCM_FMTBIT_S24_3LE | \
1595 SNDRV_PCM_FMTBIT_U24_3LE | \
1596 SNDRV_PCM_FMTBIT_S32_LE | \
1597 SNDRV_PCM_FMTBIT_U32_LE)
1598
1599 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1600 {
1601 .name = "davinci-mcasp.0",
1602 .probe = davinci_mcasp_dai_probe,
1603 .playback = {
1604 .channels_min = 1,
1605 .channels_max = 32 * 16,
1606 .rates = DAVINCI_MCASP_RATES,
1607 .formats = DAVINCI_MCASP_PCM_FMTS,
1608 },
1609 .capture = {
1610 .channels_min = 1,
1611 .channels_max = 32 * 16,
1612 .rates = DAVINCI_MCASP_RATES,
1613 .formats = DAVINCI_MCASP_PCM_FMTS,
1614 },
1615 .ops = &davinci_mcasp_dai_ops,
1616
1617 .symmetric_rates = 1,
1618 },
1619 {
1620 .name = "davinci-mcasp.1",
1621 .probe = davinci_mcasp_dai_probe,
1622 .playback = {
1623 .channels_min = 1,
1624 .channels_max = 384,
1625 .rates = DAVINCI_MCASP_RATES,
1626 .formats = DAVINCI_MCASP_PCM_FMTS,
1627 },
1628 .ops = &davinci_mcasp_dai_ops,
1629 },
1630
1631 };
1632
1633 static const struct snd_soc_component_driver davinci_mcasp_component = {
1634 .name = "davinci-mcasp",
1635 };
1636
1637 /* Some HW specific values and defaults. The rest is filled in from DT. */
1638 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1639 .tx_dma_offset = 0x400,
1640 .rx_dma_offset = 0x400,
1641 .version = MCASP_VERSION_1,
1642 };
1643
1644 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1645 .tx_dma_offset = 0x2000,
1646 .rx_dma_offset = 0x2000,
1647 .version = MCASP_VERSION_2,
1648 };
1649
1650 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1651 .tx_dma_offset = 0,
1652 .rx_dma_offset = 0,
1653 .version = MCASP_VERSION_3,
1654 };
1655
1656 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1657 /* The CFG port offset will be calculated if it is needed */
1658 .tx_dma_offset = 0,
1659 .rx_dma_offset = 0,
1660 .version = MCASP_VERSION_4,
1661 };
1662
1663 static const struct of_device_id mcasp_dt_ids[] = {
1664 {
1665 .compatible = "ti,dm646x-mcasp-audio",
1666 .data = &dm646x_mcasp_pdata,
1667 },
1668 {
1669 .compatible = "ti,da830-mcasp-audio",
1670 .data = &da830_mcasp_pdata,
1671 },
1672 {
1673 .compatible = "ti,am33xx-mcasp-audio",
1674 .data = &am33xx_mcasp_pdata,
1675 },
1676 {
1677 .compatible = "ti,dra7-mcasp-audio",
1678 .data = &dra7_mcasp_pdata,
1679 },
1680 { /* sentinel */ }
1681 };
1682 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1683
1684 static int mcasp_reparent_fck(struct platform_device *pdev)
1685 {
1686 struct device_node *node = pdev->dev.of_node;
1687 struct clk *gfclk, *parent_clk;
1688 const char *parent_name;
1689 int ret;
1690
1691 if (!node)
1692 return 0;
1693
1694 parent_name = of_get_property(node, "fck_parent", NULL);
1695 if (!parent_name)
1696 return 0;
1697
1698 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1699
1700 gfclk = clk_get(&pdev->dev, "fck");
1701 if (IS_ERR(gfclk)) {
1702 dev_err(&pdev->dev, "failed to get fck\n");
1703 return PTR_ERR(gfclk);
1704 }
1705
1706 parent_clk = clk_get(NULL, parent_name);
1707 if (IS_ERR(parent_clk)) {
1708 dev_err(&pdev->dev, "failed to get parent clock\n");
1709 ret = PTR_ERR(parent_clk);
1710 goto err1;
1711 }
1712
1713 ret = clk_set_parent(gfclk, parent_clk);
1714 if (ret) {
1715 dev_err(&pdev->dev, "failed to reparent fck\n");
1716 goto err2;
1717 }
1718
1719 err2:
1720 clk_put(parent_clk);
1721 err1:
1722 clk_put(gfclk);
1723 return ret;
1724 }
1725
1726 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1727 struct platform_device *pdev)
1728 {
1729 struct device_node *np = pdev->dev.of_node;
1730 struct davinci_mcasp_pdata *pdata = NULL;
1731 const struct of_device_id *match =
1732 of_match_device(mcasp_dt_ids, &pdev->dev);
1733 struct of_phandle_args dma_spec;
1734
1735 const u32 *of_serial_dir32;
1736 u32 val;
1737 int i, ret = 0;
1738
1739 if (pdev->dev.platform_data) {
1740 pdata = pdev->dev.platform_data;
1741 pdata->dismod = DISMOD_LOW;
1742 return pdata;
1743 } else if (match) {
1744 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1745 GFP_KERNEL);
1746 if (!pdata) {
1747 ret = -ENOMEM;
1748 return pdata;
1749 }
1750 } else {
1751 /* control shouldn't reach here. something is wrong */
1752 ret = -EINVAL;
1753 goto nodata;
1754 }
1755
1756 ret = of_property_read_u32(np, "op-mode", &val);
1757 if (ret >= 0)
1758 pdata->op_mode = val;
1759
1760 ret = of_property_read_u32(np, "tdm-slots", &val);
1761 if (ret >= 0) {
1762 if (val < 2 || val > 32) {
1763 dev_err(&pdev->dev,
1764 "tdm-slots must be in rage [2-32]\n");
1765 ret = -EINVAL;
1766 goto nodata;
1767 }
1768
1769 pdata->tdm_slots = val;
1770 }
1771
1772 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1773 val /= sizeof(u32);
1774 if (of_serial_dir32) {
1775 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1776 (sizeof(*of_serial_dir) * val),
1777 GFP_KERNEL);
1778 if (!of_serial_dir) {
1779 ret = -ENOMEM;
1780 goto nodata;
1781 }
1782
1783 for (i = 0; i < val; i++)
1784 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1785
1786 pdata->num_serializer = val;
1787 pdata->serial_dir = of_serial_dir;
1788 }
1789
1790 ret = of_property_match_string(np, "dma-names", "tx");
1791 if (ret < 0)
1792 goto nodata;
1793
1794 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1795 &dma_spec);
1796 if (ret < 0)
1797 goto nodata;
1798
1799 pdata->tx_dma_channel = dma_spec.args[0];
1800
1801 /* RX is not valid in DIT mode */
1802 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1803 ret = of_property_match_string(np, "dma-names", "rx");
1804 if (ret < 0)
1805 goto nodata;
1806
1807 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1808 &dma_spec);
1809 if (ret < 0)
1810 goto nodata;
1811
1812 pdata->rx_dma_channel = dma_spec.args[0];
1813 }
1814
1815 ret = of_property_read_u32(np, "tx-num-evt", &val);
1816 if (ret >= 0)
1817 pdata->txnumevt = val;
1818
1819 ret = of_property_read_u32(np, "rx-num-evt", &val);
1820 if (ret >= 0)
1821 pdata->rxnumevt = val;
1822
1823 ret = of_property_read_u32(np, "sram-size-playback", &val);
1824 if (ret >= 0)
1825 pdata->sram_size_playback = val;
1826
1827 ret = of_property_read_u32(np, "sram-size-capture", &val);
1828 if (ret >= 0)
1829 pdata->sram_size_capture = val;
1830
1831 ret = of_property_read_u32(np, "dismod", &val);
1832 if (ret >= 0) {
1833 if (val == 0 || val == 2 || val == 3) {
1834 pdata->dismod = DISMOD_VAL(val);
1835 } else {
1836 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1837 pdata->dismod = DISMOD_LOW;
1838 }
1839 } else {
1840 pdata->dismod = DISMOD_LOW;
1841 }
1842
1843 return pdata;
1844
1845 nodata:
1846 if (ret < 0) {
1847 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1848 ret);
1849 pdata = NULL;
1850 }
1851 return pdata;
1852 }
1853
1854 enum {
1855 PCM_EDMA,
1856 PCM_SDMA,
1857 };
1858 static const char *sdma_prefix = "ti,omap";
1859
1860 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1861 {
1862 struct dma_chan *chan;
1863 const char *tmp;
1864 int ret = PCM_EDMA;
1865
1866 if (!mcasp->dev->of_node)
1867 return PCM_EDMA;
1868
1869 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1870 chan = dma_request_chan(mcasp->dev, tmp);
1871 if (IS_ERR(chan)) {
1872 if (PTR_ERR(chan) != -EPROBE_DEFER)
1873 dev_err(mcasp->dev,
1874 "Can't verify DMA configuration (%ld)\n",
1875 PTR_ERR(chan));
1876 return PTR_ERR(chan);
1877 }
1878 if (WARN_ON(!chan->device || !chan->device->dev))
1879 return -EINVAL;
1880
1881 if (chan->device->dev->of_node)
1882 ret = of_property_read_string(chan->device->dev->of_node,
1883 "compatible", &tmp);
1884 else
1885 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1886
1887 dma_release_channel(chan);
1888 if (ret)
1889 return ret;
1890
1891 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1892 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1893 return PCM_SDMA;
1894
1895 return PCM_EDMA;
1896 }
1897
1898 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1899 {
1900 int i;
1901 u32 offset = 0;
1902
1903 if (pdata->version != MCASP_VERSION_4)
1904 return pdata->tx_dma_offset;
1905
1906 for (i = 0; i < pdata->num_serializer; i++) {
1907 if (pdata->serial_dir[i] == TX_MODE) {
1908 if (!offset) {
1909 offset = DAVINCI_MCASP_TXBUF_REG(i);
1910 } else {
1911 pr_err("%s: Only one serializer allowed!\n",
1912 __func__);
1913 break;
1914 }
1915 }
1916 }
1917
1918 return offset;
1919 }
1920
1921 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1922 {
1923 int i;
1924 u32 offset = 0;
1925
1926 if (pdata->version != MCASP_VERSION_4)
1927 return pdata->rx_dma_offset;
1928
1929 for (i = 0; i < pdata->num_serializer; i++) {
1930 if (pdata->serial_dir[i] == RX_MODE) {
1931 if (!offset) {
1932 offset = DAVINCI_MCASP_RXBUF_REG(i);
1933 } else {
1934 pr_err("%s: Only one serializer allowed!\n",
1935 __func__);
1936 break;
1937 }
1938 }
1939 }
1940
1941 return offset;
1942 }
1943
1944 #ifdef CONFIG_GPIOLIB
1945 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
1946 {
1947 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1948
1949 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1950 mcasp->serial_dir[offset] != INACTIVE_MODE) {
1951 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
1952 return -EBUSY;
1953 }
1954
1955 /* Do not change the PIN yet */
1956
1957 return pm_runtime_get_sync(mcasp->dev);
1958 }
1959
1960 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
1961 {
1962 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1963
1964 /* Set the direction to input */
1965 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1966
1967 /* Set the pin as McASP pin */
1968 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1969
1970 pm_runtime_put_sync(mcasp->dev);
1971 }
1972
1973 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
1974 unsigned offset, int value)
1975 {
1976 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1977 u32 val;
1978
1979 if (value)
1980 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1981 else
1982 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1983
1984 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1985 if (!(val & BIT(offset))) {
1986 /* Set the pin as GPIO pin */
1987 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1988
1989 /* Set the direction to output */
1990 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1991 }
1992
1993 return 0;
1994 }
1995
1996 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
1997 int value)
1998 {
1999 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2000
2001 if (value)
2002 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2003 else
2004 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2005 }
2006
2007 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
2008 unsigned offset)
2009 {
2010 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2011 u32 val;
2012
2013 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2014 if (!(val & BIT(offset))) {
2015 /* Set the direction to input */
2016 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2017
2018 /* Set the pin as GPIO pin */
2019 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2020 }
2021
2022 return 0;
2023 }
2024
2025 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
2026 {
2027 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2028 u32 val;
2029
2030 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2031 if (val & BIT(offset))
2032 return 1;
2033
2034 return 0;
2035 }
2036
2037 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
2038 unsigned offset)
2039 {
2040 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2041 u32 val;
2042
2043 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2044 if (val & BIT(offset))
2045 return 0;
2046
2047 return 1;
2048 }
2049
2050 static const struct gpio_chip davinci_mcasp_template_chip = {
2051 .owner = THIS_MODULE,
2052 .request = davinci_mcasp_gpio_request,
2053 .free = davinci_mcasp_gpio_free,
2054 .direction_output = davinci_mcasp_gpio_direction_out,
2055 .set = davinci_mcasp_gpio_set,
2056 .direction_input = davinci_mcasp_gpio_direction_in,
2057 .get = davinci_mcasp_gpio_get,
2058 .get_direction = davinci_mcasp_gpio_get_direction,
2059 .base = -1,
2060 .ngpio = 32,
2061 };
2062
2063 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2064 {
2065 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
2066 return 0;
2067
2068 mcasp->gpio_chip = davinci_mcasp_template_chip;
2069 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2070 mcasp->gpio_chip.parent = mcasp->dev;
2071 #ifdef CONFIG_OF_GPIO
2072 mcasp->gpio_chip.of_node = mcasp->dev->of_node;
2073 #endif
2074
2075 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2076 }
2077
2078 #else /* CONFIG_GPIOLIB */
2079 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2080 {
2081 return 0;
2082 }
2083 #endif /* CONFIG_GPIOLIB */
2084
2085 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
2086 {
2087 struct device_node *np = mcasp->dev->of_node;
2088 int ret;
2089 u32 val;
2090
2091 if (!np)
2092 return 0;
2093
2094 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
2095 if (ret >= 0)
2096 mcasp->auxclk_fs_ratio = val;
2097
2098 return 0;
2099 }
2100
2101 static int davinci_mcasp_probe(struct platform_device *pdev)
2102 {
2103 struct snd_dmaengine_dai_dma_data *dma_data;
2104 struct resource *mem, *res, *dat;
2105 struct davinci_mcasp_pdata *pdata;
2106 struct davinci_mcasp *mcasp;
2107 char *irq_name;
2108 int *dma;
2109 int irq;
2110 int ret;
2111
2112 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2113 dev_err(&pdev->dev, "No platform data supplied\n");
2114 return -EINVAL;
2115 }
2116
2117 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2118 GFP_KERNEL);
2119 if (!mcasp)
2120 return -ENOMEM;
2121
2122 pdata = davinci_mcasp_set_pdata_from_of(pdev);
2123 if (!pdata) {
2124 dev_err(&pdev->dev, "no platform data\n");
2125 return -EINVAL;
2126 }
2127
2128 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2129 if (!mem) {
2130 dev_warn(mcasp->dev,
2131 "\"mpu\" mem resource not found, using index 0\n");
2132 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2133 if (!mem) {
2134 dev_err(&pdev->dev, "no mem resource?\n");
2135 return -ENODEV;
2136 }
2137 }
2138
2139 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2140 if (IS_ERR(mcasp->base))
2141 return PTR_ERR(mcasp->base);
2142
2143 pm_runtime_enable(&pdev->dev);
2144
2145 mcasp->op_mode = pdata->op_mode;
2146 /* sanity check for tdm slots parameter */
2147 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2148 if (pdata->tdm_slots < 2) {
2149 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2150 pdata->tdm_slots);
2151 mcasp->tdm_slots = 2;
2152 } else if (pdata->tdm_slots > 32) {
2153 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2154 pdata->tdm_slots);
2155 mcasp->tdm_slots = 32;
2156 } else {
2157 mcasp->tdm_slots = pdata->tdm_slots;
2158 }
2159 }
2160
2161 mcasp->num_serializer = pdata->num_serializer;
2162 #ifdef CONFIG_PM
2163 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2164 mcasp->num_serializer, sizeof(u32),
2165 GFP_KERNEL);
2166 if (!mcasp->context.xrsr_regs) {
2167 ret = -ENOMEM;
2168 goto err;
2169 }
2170 #endif
2171 mcasp->serial_dir = pdata->serial_dir;
2172 mcasp->version = pdata->version;
2173 mcasp->txnumevt = pdata->txnumevt;
2174 mcasp->rxnumevt = pdata->rxnumevt;
2175 mcasp->dismod = pdata->dismod;
2176
2177 mcasp->dev = &pdev->dev;
2178
2179 irq = platform_get_irq_byname(pdev, "common");
2180 if (irq >= 0) {
2181 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2182 dev_name(&pdev->dev));
2183 if (!irq_name) {
2184 ret = -ENOMEM;
2185 goto err;
2186 }
2187 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2188 davinci_mcasp_common_irq_handler,
2189 IRQF_ONESHOT | IRQF_SHARED,
2190 irq_name, mcasp);
2191 if (ret) {
2192 dev_err(&pdev->dev, "common IRQ request failed\n");
2193 goto err;
2194 }
2195
2196 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2197 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2198 }
2199
2200 irq = platform_get_irq_byname(pdev, "rx");
2201 if (irq >= 0) {
2202 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2203 dev_name(&pdev->dev));
2204 if (!irq_name) {
2205 ret = -ENOMEM;
2206 goto err;
2207 }
2208 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2209 davinci_mcasp_rx_irq_handler,
2210 IRQF_ONESHOT, irq_name, mcasp);
2211 if (ret) {
2212 dev_err(&pdev->dev, "RX IRQ request failed\n");
2213 goto err;
2214 }
2215
2216 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2217 }
2218
2219 irq = platform_get_irq_byname(pdev, "tx");
2220 if (irq >= 0) {
2221 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2222 dev_name(&pdev->dev));
2223 if (!irq_name) {
2224 ret = -ENOMEM;
2225 goto err;
2226 }
2227 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2228 davinci_mcasp_tx_irq_handler,
2229 IRQF_ONESHOT, irq_name, mcasp);
2230 if (ret) {
2231 dev_err(&pdev->dev, "TX IRQ request failed\n");
2232 goto err;
2233 }
2234
2235 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2236 }
2237
2238 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2239 if (dat)
2240 mcasp->dat_port = true;
2241
2242 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2243 if (dat)
2244 dma_data->addr = dat->start;
2245 else
2246 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
2247
2248 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
2249 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2250 if (res)
2251 *dma = res->start;
2252 else
2253 *dma = pdata->tx_dma_channel;
2254
2255 /* dmaengine filter data for DT and non-DT boot */
2256 if (pdev->dev.of_node)
2257 dma_data->filter_data = "tx";
2258 else
2259 dma_data->filter_data = dma;
2260
2261 /* RX is not valid in DIT mode */
2262 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2263 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2264 if (dat)
2265 dma_data->addr = dat->start;
2266 else
2267 dma_data->addr =
2268 mem->start + davinci_mcasp_rxdma_offset(pdata);
2269
2270 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2271 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2272 if (res)
2273 *dma = res->start;
2274 else
2275 *dma = pdata->rx_dma_channel;
2276
2277 /* dmaengine filter data for DT and non-DT boot */
2278 if (pdev->dev.of_node)
2279 dma_data->filter_data = "rx";
2280 else
2281 dma_data->filter_data = dma;
2282 }
2283
2284 if (mcasp->version < MCASP_VERSION_3) {
2285 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2286 /* dma_params->dma_addr is pointing to the data port address */
2287 mcasp->dat_port = true;
2288 } else {
2289 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2290 }
2291
2292 /* Allocate memory for long enough list for all possible
2293 * scenarios. Maximum number tdm slots is 32 and there cannot
2294 * be more serializers than given in the configuration. The
2295 * serializer directions could be taken into account, but it
2296 * would make code much more complex and save only couple of
2297 * bytes.
2298 */
2299 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2300 devm_kcalloc(mcasp->dev,
2301 32 + mcasp->num_serializer - 1,
2302 sizeof(unsigned int),
2303 GFP_KERNEL);
2304
2305 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2306 devm_kcalloc(mcasp->dev,
2307 32 + mcasp->num_serializer - 1,
2308 sizeof(unsigned int),
2309 GFP_KERNEL);
2310
2311 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2312 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2313 ret = -ENOMEM;
2314 goto err;
2315 }
2316
2317 ret = davinci_mcasp_set_ch_constraints(mcasp);
2318 if (ret)
2319 goto err;
2320
2321 dev_set_drvdata(&pdev->dev, mcasp);
2322
2323 mcasp_reparent_fck(pdev);
2324
2325 /* All PINS as McASP */
2326 pm_runtime_get_sync(mcasp->dev);
2327 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2328 pm_runtime_put(mcasp->dev);
2329
2330 ret = davinci_mcasp_init_gpiochip(mcasp);
2331 if (ret)
2332 goto err;
2333
2334 ret = davinci_mcasp_get_dt_params(mcasp);
2335 if (ret)
2336 return -EINVAL;
2337
2338 ret = devm_snd_soc_register_component(&pdev->dev,
2339 &davinci_mcasp_component,
2340 &davinci_mcasp_dai[pdata->op_mode], 1);
2341
2342 if (ret != 0)
2343 goto err;
2344
2345 ret = davinci_mcasp_get_dma_type(mcasp);
2346 switch (ret) {
2347 case PCM_EDMA:
2348 ret = edma_pcm_platform_register(&pdev->dev);
2349 break;
2350 case PCM_SDMA:
2351 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
2352 break;
2353 default:
2354 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2355 case -EPROBE_DEFER:
2356 goto err;
2357 break;
2358 }
2359
2360 if (ret) {
2361 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2362 goto err;
2363 }
2364
2365 return 0;
2366
2367 err:
2368 pm_runtime_disable(&pdev->dev);
2369 return ret;
2370 }
2371
2372 static int davinci_mcasp_remove(struct platform_device *pdev)
2373 {
2374 pm_runtime_disable(&pdev->dev);
2375
2376 return 0;
2377 }
2378
2379 #ifdef CONFIG_PM
2380 static int davinci_mcasp_runtime_suspend(struct device *dev)
2381 {
2382 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2383 struct davinci_mcasp_context *context = &mcasp->context;
2384 u32 reg;
2385 int i;
2386
2387 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2388 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2389
2390 if (mcasp->txnumevt) {
2391 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2392 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2393 }
2394 if (mcasp->rxnumevt) {
2395 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2396 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2397 }
2398
2399 for (i = 0; i < mcasp->num_serializer; i++)
2400 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2401 DAVINCI_MCASP_XRSRCTL_REG(i));
2402
2403 return 0;
2404 }
2405
2406 static int davinci_mcasp_runtime_resume(struct device *dev)
2407 {
2408 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2409 struct davinci_mcasp_context *context = &mcasp->context;
2410 u32 reg;
2411 int i;
2412
2413 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2414 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2415
2416 if (mcasp->txnumevt) {
2417 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2418 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2419 }
2420 if (mcasp->rxnumevt) {
2421 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2422 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2423 }
2424
2425 for (i = 0; i < mcasp->num_serializer; i++)
2426 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2427 context->xrsr_regs[i]);
2428
2429 return 0;
2430 }
2431
2432 #endif
2433
2434 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2435 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2436 davinci_mcasp_runtime_resume,
2437 NULL)
2438 };
2439
2440 static struct platform_driver davinci_mcasp_driver = {
2441 .probe = davinci_mcasp_probe,
2442 .remove = davinci_mcasp_remove,
2443 .driver = {
2444 .name = "davinci-mcasp",
2445 .pm = &davinci_mcasp_pm_ops,
2446 .of_match_table = mcasp_dt_ids,
2447 },
2448 };
2449
2450 module_platform_driver(davinci_mcasp_driver);
2451
2452 MODULE_AUTHOR("Steve Chen");
2453 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2454 MODULE_LICENSE("GPL");
Linux with added FPC-III support