1 // SPDX-License-Identifier: GPL-2.0
3 * McBSP Sidetone support
5 * Copyright (C) 2004 Nokia Corporation
6 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
9 * Peter Ujfalusi <peter.ujfalusi@ti.com>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/pm_runtime.h>
24 #include "omap-mcbsp.h"
25 #include "omap-mcbsp-priv.h"
27 /* OMAP3 sidetone control registers */
28 #define OMAP_ST_REG_REV 0x00
29 #define OMAP_ST_REG_SYSCONFIG 0x10
30 #define OMAP_ST_REG_IRQSTATUS 0x18
31 #define OMAP_ST_REG_IRQENABLE 0x1C
32 #define OMAP_ST_REG_SGAINCR 0x24
33 #define OMAP_ST_REG_SFIRCR 0x28
34 #define OMAP_ST_REG_SSELCR 0x2C
36 /********************** McBSP SSELCR bit definitions ***********************/
37 #define SIDETONEEN BIT(10)
39 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
40 #define ST_AUTOIDLE BIT(0)
42 /********************** McBSP Sidetone SGAINCR bit definitions *************/
43 #define ST_CH0GAIN(value) ((value) & 0xffff) /* Bits 0:15 */
44 #define ST_CH1GAIN(value) (((value) & 0xffff) << 16) /* Bits 16:31 */
46 /********************** McBSP Sidetone SFIRCR bit definitions **************/
47 #define ST_FIRCOEFF(value) ((value) & 0xffff) /* Bits 0:15 */
49 /********************** McBSP Sidetone SSELCR bit definitions **************/
50 #define ST_SIDETONEEN BIT(0)
51 #define ST_COEFFWREN BIT(1)
52 #define ST_COEFFWRDONE BIT(2)
54 struct omap_mcbsp_st_data
{
55 void __iomem
*io_base_st
;
56 struct clk
*mcbsp_iclk
;
59 s16 taps
[128]; /* Sidetone filter coefficients */
60 int nr_taps
; /* Number of filter coefficients in use */
65 static void omap_mcbsp_st_write(struct omap_mcbsp
*mcbsp
, u16 reg
, u32 val
)
67 writel_relaxed(val
, mcbsp
->st_data
->io_base_st
+ reg
);
70 static int omap_mcbsp_st_read(struct omap_mcbsp
*mcbsp
, u16 reg
)
72 return readl_relaxed(mcbsp
->st_data
->io_base_st
+ reg
);
75 #define MCBSP_ST_READ(mcbsp, reg) omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
76 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
77 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
79 static void omap_mcbsp_st_on(struct omap_mcbsp
*mcbsp
)
83 if (mcbsp
->pdata
->force_ick_on
)
84 mcbsp
->pdata
->force_ick_on(mcbsp
->st_data
->mcbsp_iclk
, true);
86 /* Disable Sidetone clock auto-gating for normal operation */
87 w
= MCBSP_ST_READ(mcbsp
, SYSCONFIG
);
88 MCBSP_ST_WRITE(mcbsp
, SYSCONFIG
, w
& ~(ST_AUTOIDLE
));
90 /* Enable McBSP Sidetone */
91 w
= MCBSP_READ(mcbsp
, SSELCR
);
92 MCBSP_WRITE(mcbsp
, SSELCR
, w
| SIDETONEEN
);
94 /* Enable Sidetone from Sidetone Core */
95 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
96 MCBSP_ST_WRITE(mcbsp
, SSELCR
, w
| ST_SIDETONEEN
);
99 static void omap_mcbsp_st_off(struct omap_mcbsp
*mcbsp
)
103 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
104 MCBSP_ST_WRITE(mcbsp
, SSELCR
, w
& ~(ST_SIDETONEEN
));
106 w
= MCBSP_READ(mcbsp
, SSELCR
);
107 MCBSP_WRITE(mcbsp
, SSELCR
, w
& ~(SIDETONEEN
));
109 /* Enable Sidetone clock auto-gating to reduce power consumption */
110 w
= MCBSP_ST_READ(mcbsp
, SYSCONFIG
);
111 MCBSP_ST_WRITE(mcbsp
, SYSCONFIG
, w
| ST_AUTOIDLE
);
113 if (mcbsp
->pdata
->force_ick_on
)
114 mcbsp
->pdata
->force_ick_on(mcbsp
->st_data
->mcbsp_iclk
, false);
117 static void omap_mcbsp_st_fir_write(struct omap_mcbsp
*mcbsp
, s16
*fir
)
121 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
123 if (val
& ST_COEFFWREN
)
124 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
& ~(ST_COEFFWREN
));
126 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
| ST_COEFFWREN
);
128 for (i
= 0; i
< 128; i
++)
129 MCBSP_ST_WRITE(mcbsp
, SFIRCR
, fir
[i
]);
133 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
134 while (!(val
& ST_COEFFWRDONE
) && (++i
< 1000))
135 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
137 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
& ~(ST_COEFFWREN
));
140 dev_err(mcbsp
->dev
, "McBSP FIR load error!\n");
143 static void omap_mcbsp_st_chgain(struct omap_mcbsp
*mcbsp
)
146 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
148 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
150 MCBSP_ST_WRITE(mcbsp
, SGAINCR
, ST_CH0GAIN(st_data
->ch0gain
) |
151 ST_CH1GAIN(st_data
->ch1gain
));
154 static int omap_mcbsp_st_set_chgain(struct omap_mcbsp
*mcbsp
, int channel
,
157 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
163 spin_lock_irq(&mcbsp
->lock
);
165 st_data
->ch0gain
= chgain
;
166 else if (channel
== 1)
167 st_data
->ch1gain
= chgain
;
171 if (st_data
->enabled
)
172 omap_mcbsp_st_chgain(mcbsp
);
173 spin_unlock_irq(&mcbsp
->lock
);
178 static int omap_mcbsp_st_get_chgain(struct omap_mcbsp
*mcbsp
, int channel
,
181 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
187 spin_lock_irq(&mcbsp
->lock
);
189 *chgain
= st_data
->ch0gain
;
190 else if (channel
== 1)
191 *chgain
= st_data
->ch1gain
;
194 spin_unlock_irq(&mcbsp
->lock
);
199 static int omap_mcbsp_st_enable(struct omap_mcbsp
*mcbsp
)
201 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
206 spin_lock_irq(&mcbsp
->lock
);
207 st_data
->enabled
= 1;
208 omap_mcbsp_st_start(mcbsp
);
209 spin_unlock_irq(&mcbsp
->lock
);
214 static int omap_mcbsp_st_disable(struct omap_mcbsp
*mcbsp
)
216 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
222 spin_lock_irq(&mcbsp
->lock
);
223 omap_mcbsp_st_stop(mcbsp
);
224 st_data
->enabled
= 0;
225 spin_unlock_irq(&mcbsp
->lock
);
230 static int omap_mcbsp_st_is_enabled(struct omap_mcbsp
*mcbsp
)
232 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
237 return st_data
->enabled
;
240 static ssize_t
st_taps_show(struct device
*dev
,
241 struct device_attribute
*attr
, char *buf
)
243 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
244 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
248 spin_lock_irq(&mcbsp
->lock
);
249 for (i
= 0; i
< st_data
->nr_taps
; i
++)
250 status
+= sprintf(&buf
[status
], (i
? ", %d" : "%d"),
253 status
+= sprintf(&buf
[status
], "\n");
254 spin_unlock_irq(&mcbsp
->lock
);
259 static ssize_t
st_taps_store(struct device
*dev
,
260 struct device_attribute
*attr
,
261 const char *buf
, size_t size
)
263 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
264 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
265 int val
, tmp
, status
, i
= 0;
267 spin_lock_irq(&mcbsp
->lock
);
268 memset(st_data
->taps
, 0, sizeof(st_data
->taps
));
269 st_data
->nr_taps
= 0;
272 status
= sscanf(buf
, "%d%n", &val
, &tmp
);
273 if (status
< 0 || status
== 0) {
277 if (val
< -32768 || val
> 32767) {
281 st_data
->taps
[i
++] = val
;
288 st_data
->nr_taps
= i
;
291 spin_unlock_irq(&mcbsp
->lock
);
296 static DEVICE_ATTR_RW(st_taps
);
298 static const struct attribute
*sidetone_attrs
[] = {
299 &dev_attr_st_taps
.attr
,
303 static const struct attribute_group sidetone_attr_group
= {
304 .attrs
= (struct attribute
**)sidetone_attrs
,
307 int omap_mcbsp_st_start(struct omap_mcbsp
*mcbsp
)
309 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
311 if (st_data
->enabled
&& !st_data
->running
) {
312 omap_mcbsp_st_fir_write(mcbsp
, st_data
->taps
);
313 omap_mcbsp_st_chgain(mcbsp
);
316 omap_mcbsp_st_on(mcbsp
);
317 st_data
->running
= 1;
324 int omap_mcbsp_st_stop(struct omap_mcbsp
*mcbsp
)
326 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
328 if (st_data
->running
) {
330 omap_mcbsp_st_off(mcbsp
);
331 st_data
->running
= 0;
338 int omap_mcbsp_st_init(struct platform_device
*pdev
)
340 struct omap_mcbsp
*mcbsp
= platform_get_drvdata(pdev
);
341 struct omap_mcbsp_st_data
*st_data
;
342 struct resource
*res
;
345 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "sidetone");
349 st_data
= devm_kzalloc(mcbsp
->dev
, sizeof(*mcbsp
->st_data
), GFP_KERNEL
);
353 st_data
->mcbsp_iclk
= clk_get(mcbsp
->dev
, "ick");
354 if (IS_ERR(st_data
->mcbsp_iclk
)) {
356 "Failed to get ick, sidetone might be broken\n");
357 st_data
->mcbsp_iclk
= NULL
;
360 st_data
->io_base_st
= devm_ioremap(mcbsp
->dev
, res
->start
,
362 if (!st_data
->io_base_st
)
365 ret
= sysfs_create_group(&mcbsp
->dev
->kobj
, &sidetone_attr_group
);
369 mcbsp
->st_data
= st_data
;
374 void omap_mcbsp_st_cleanup(struct platform_device
*pdev
)
376 struct omap_mcbsp
*mcbsp
= platform_get_drvdata(pdev
);
378 if (mcbsp
->st_data
) {
379 sysfs_remove_group(&mcbsp
->dev
->kobj
, &sidetone_attr_group
);
380 clk_put(mcbsp
->st_data
->mcbsp_iclk
);
384 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol
*kcontrol
,
385 struct snd_ctl_elem_info
*uinfo
)
387 struct soc_mixer_control
*mc
=
388 (struct soc_mixer_control
*)kcontrol
->private_value
;
392 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
394 uinfo
->value
.integer
.min
= min
;
395 uinfo
->value
.integer
.max
= max
;
399 #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel) \
401 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
402 struct snd_ctl_elem_value *uc) \
404 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
405 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
406 struct soc_mixer_control *mc = \
407 (struct soc_mixer_control *)kc->private_value; \
410 int val = uc->value.integer.value[0]; \
412 if (val < min || val > max) \
415 /* OMAP McBSP implementation uses index values 0..4 */ \
416 return omap_mcbsp_st_set_chgain(mcbsp, channel, val); \
420 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
421 struct snd_ctl_elem_value *uc) \
423 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
424 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
427 if (omap_mcbsp_st_get_chgain(mcbsp, channel, &chgain)) \
430 uc->value.integer.value[0] = chgain; \
434 OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
435 OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
437 static int omap_mcbsp_st_put_mode(struct snd_kcontrol
*kcontrol
,
438 struct snd_ctl_elem_value
*ucontrol
)
440 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
441 struct omap_mcbsp
*mcbsp
= snd_soc_dai_get_drvdata(cpu_dai
);
442 u8 value
= ucontrol
->value
.integer
.value
[0];
444 if (value
== omap_mcbsp_st_is_enabled(mcbsp
))
448 omap_mcbsp_st_enable(mcbsp
);
450 omap_mcbsp_st_disable(mcbsp
);
455 static int omap_mcbsp_st_get_mode(struct snd_kcontrol
*kcontrol
,
456 struct snd_ctl_elem_value
*ucontrol
)
458 struct snd_soc_dai
*cpu_dai
= snd_kcontrol_chip(kcontrol
);
459 struct omap_mcbsp
*mcbsp
= snd_soc_dai_get_drvdata(cpu_dai
);
461 ucontrol
->value
.integer
.value
[0] = omap_mcbsp_st_is_enabled(mcbsp
);
465 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
466 xhandler_get, xhandler_put) \
467 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
468 .info = omap_mcbsp_st_info_volsw, \
469 .get = xhandler_get, .put = xhandler_put, \
470 .private_value = (unsigned long)&(struct soc_mixer_control) \
471 {.min = xmin, .max = xmax} }
473 #define OMAP_MCBSP_ST_CONTROLS(port) \
474 static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
475 SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0, \
476 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), \
477 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
479 omap_mcbsp_get_st_ch0_volume, \
480 omap_mcbsp_set_st_ch0_volume), \
481 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
483 omap_mcbsp_get_st_ch1_volume, \
484 omap_mcbsp_set_st_ch1_volume), \
487 OMAP_MCBSP_ST_CONTROLS(2);
488 OMAP_MCBSP_ST_CONTROLS(3);
490 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime
*rtd
, int port_id
)
492 struct snd_soc_dai
*cpu_dai
= rtd
->cpu_dai
;
493 struct omap_mcbsp
*mcbsp
= snd_soc_dai_get_drvdata(cpu_dai
);
495 if (!mcbsp
->st_data
) {
496 dev_warn(mcbsp
->dev
, "No sidetone data for port\n");
501 case 2: /* McBSP 2 */
502 return snd_soc_add_dai_controls(cpu_dai
,
503 omap_mcbsp2_st_controls
,
504 ARRAY_SIZE(omap_mcbsp2_st_controls
));
505 case 3: /* McBSP 3 */
506 return snd_soc_add_dai_controls(cpu_dai
,
507 omap_mcbsp3_st_controls
,
508 ARRAY_SIZE(omap_mcbsp3_st_controls
));
510 dev_err(mcbsp
->dev
, "Port %d not supported\n", port_id
);
516 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls
);