arch/s390/include/asm/pci_clp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_S390_PCI_CLP_H
   3 #define _ASM_S390_PCI_CLP_H
   4
   5 #include <asm/clp.h>
   6
   7 /*
   8  * Call Logical Processor - Command Codes
   9  */
  10 #define CLP_LIST_PCI            0x0002
  11 #define CLP_QUERY_PCI_FN        0x0003
  12 #define CLP_QUERY_PCI_FNGRP     0x0004
  13 #define CLP_SET_PCI_FN          0x0005
  14
  15 /* PCI function handle list entry */
  16 struct clp_fh_list_entry {
  17         u16 device_id;
  18         u16 vendor_id;
  19         u32 config_state :  1;
  20         u32              : 31;
  21         u32 fid;                /* PCI function id */
  22         u32 fh;                 /* PCI function handle */
  23 } __packed;
  24
  25 #define CLP_RC_SETPCIFN_FH      0x0101  /* Invalid PCI fn handle */
  26 #define CLP_RC_SETPCIFN_FHOP    0x0102  /* Fn handle not valid for op */
  27 #define CLP_RC_SETPCIFN_DMAAS   0x0103  /* Invalid DMA addr space */
  28 #define CLP_RC_SETPCIFN_RES     0x0104  /* Insufficient resources */
  29 #define CLP_RC_SETPCIFN_ALRDY   0x0105  /* Fn already in requested state */
  30 #define CLP_RC_SETPCIFN_ERR     0x0106  /* Fn in permanent error state */
  31 #define CLP_RC_SETPCIFN_RECPND  0x0107  /* Error recovery pending */
  32 #define CLP_RC_SETPCIFN_BUSY    0x0108  /* Fn busy */
  33 #define CLP_RC_LISTPCI_BADRT    0x010a  /* Resume token not recognized */
  34 #define CLP_RC_QUERYPCIFG_PFGID 0x010b  /* Unrecognized PFGID */
  35
  36 /* request or response block header length */
  37 #define LIST_PCI_HDR_LEN        32
  38
  39 /* Number of function handles fitting in response block */
  40 #define CLP_FH_LIST_NR_ENTRIES                          \
  41         ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN)          \
  42                 / sizeof(struct clp_fh_list_entry))
  43
  44 #define CLP_SET_ENABLE_PCI_FN   0       /* Yes, 0 enables it */
  45 #define CLP_SET_DISABLE_PCI_FN  1       /* Yes, 1 disables it */
  46 #define CLP_SET_ENABLE_MIO      2
  47 #define CLP_SET_DISABLE_MIO     3
  48
  49 #define CLP_UTIL_STR_LEN        64
  50 #define CLP_PFIP_NR_SEGMENTS    4
  51
  52 extern bool zpci_unique_uid;
  53
  54 /* List PCI functions request */
  55 struct clp_req_list_pci {
  56         struct clp_req_hdr hdr;
  57         u64 resume_token;
  58         u64 reserved2;
  59 } __packed;
  60
  61 /* List PCI functions response */
  62 struct clp_rsp_list_pci {
  63         struct clp_rsp_hdr hdr;
  64         u64 resume_token;
  65         u32 reserved2;
  66         u16 max_fn;
  67         u8                      : 7;
  68         u8 uid_checking         : 1;
  69         u8 entry_size;
  70         struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
  71 } __packed;
  72
  73 /* Query PCI function request */
  74 struct clp_req_query_pci {
  75         struct clp_req_hdr hdr;
  76         u32 fh;                         /* function handle */
  77         u32 reserved2;
  78         u64 reserved3;
  79 } __packed;
  80
  81 /* Query PCI function response */
  82 struct clp_rsp_query_pci {
  83         struct clp_rsp_hdr hdr;
  84         u16 vfn;                        /* virtual fn number */
  85         u16                     :  6;
  86         u16 mio_addr_avail      :  1;
  87         u16 util_str_avail      :  1;   /* utility string available? */
  88         u16 pfgid               :  8;   /* pci function group id */
  89         u32 fid;                        /* pci function id */
  90         u8 bar_size[PCI_BAR_COUNT];
  91         u16 pchid;
  92         __le32 bar[PCI_BAR_COUNT];
  93         u8 pfip[CLP_PFIP_NR_SEGMENTS];  /* pci function internal path */
  94         u32                     : 16;
  95         u8 fmb_len;
  96         u8 pft;                         /* pci function type */
  97         u64 sdma;                       /* start dma as */
  98         u64 edma;                       /* end dma as */
  99         u32 reserved[11];
 100         u32 uid;                        /* user defined id */
 101         u8 util_str[CLP_UTIL_STR_LEN];  /* utility string */
 102         u32 reserved2[16];
 103         u32 mio_valid : 6;
 104         u32 : 26;
 105         u32 : 32;
 106         struct {
 107                 u64 wb;
 108                 u64 wt;
 109         } addr[PCI_BAR_COUNT];
 110         u32 reserved3[6];
 111 } __packed;
 112
 113 /* Query PCI function group request */
 114 struct clp_req_query_pci_grp {
 115         struct clp_req_hdr hdr;
 116         u32 reserved2           : 24;
 117         u32 pfgid               :  8;   /* function group id */
 118         u32 reserved3;
 119         u64 reserved4;
 120 } __packed;
 121
 122 /* Query PCI function group response */
 123 struct clp_rsp_query_pci_grp {
 124         struct clp_rsp_hdr hdr;
 125         u16                     :  4;
 126         u16 noi                 : 12;   /* number of interrupts */
 127         u8 version;
 128         u8                      :  6;
 129         u8 frame                :  1;
 130         u8 refresh              :  1;   /* TLB refresh mode */
 131         u16 reserved2;
 132         u16 mui;
 133         u16                     : 16;
 134         u16 maxfaal;
 135         u16                     :  4;
 136         u16 dnoi                : 12;
 137         u16 maxcpu;
 138         u64 dasm;                       /* dma address space mask */
 139         u64 msia;                       /* MSI address */
 140         u64 reserved4;
 141         u64 reserved5;
 142 } __packed;
 143
 144 /* Set PCI function request */
 145 struct clp_req_set_pci {
 146         struct clp_req_hdr hdr;
 147         u32 fh;                         /* function handle */
 148         u16 reserved2;
 149         u8 oc;                          /* operation controls */
 150         u8 ndas;                        /* number of dma spaces */
 151         u64 reserved3;
 152 } __packed;
 153
 154 /* Set PCI function response */
 155 struct clp_rsp_set_pci {
 156         struct clp_rsp_hdr hdr;
 157         u32 fh;                         /* function handle */
 158         u32 reserved3;
 159         u64 reserved4;
 160 } __packed;
 161
 162 /* Combined request/response block structures used by clp insn */
 163 struct clp_req_rsp_list_pci {
 164         struct clp_req_list_pci request;
 165         struct clp_rsp_list_pci response;
 166 } __packed;
 167
 168 struct clp_req_rsp_set_pci {
 169         struct clp_req_set_pci request;
 170         struct clp_rsp_set_pci response;
 171 } __packed;
 172
 173 struct clp_req_rsp_query_pci {
 174         struct clp_req_query_pci request;
 175         struct clp_rsp_query_pci response;
 176 } __packed;
 177
 178 struct clp_req_rsp_query_pci_grp {
 179         struct clp_req_query_pci_grp request;
 180         struct clp_rsp_query_pci_grp response;
 181 } __packed;
 182
 183 #endif