arch/sh/kernel/cpu/sh4/setup-sh4-202.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH4-202 Setup
   4  *
   5  *  Copyright (C) 2006  Paul Mundt
   6  *  Copyright (C) 2009  Magnus Damm
   7  */
   8 #include <linux/platform_device.h>
   9 #include <linux/init.h>
  10 #include <linux/serial.h>
  11 #include <linux/serial_sci.h>
  12 #include <linux/sh_timer.h>
  13 #include <linux/sh_intc.h>
  14 #include <linux/io.h>
  15
  16 static struct plat_sci_port scif0_platform_data = {
  17         .scscr          = SCSCR_REIE,
  18         .type           = PORT_SCIF,
  19 };
  20
  21 static struct resource scif0_resources[] = {
  22         DEFINE_RES_MEM(0xffe80000, 0x100),
  23         DEFINE_RES_IRQ(evt2irq(0x700)),
  24         DEFINE_RES_IRQ(evt2irq(0x720)),
  25         DEFINE_RES_IRQ(evt2irq(0x760)),
  26         DEFINE_RES_IRQ(evt2irq(0x740)),
  27 };
  28
  29 static struct platform_device scif0_device = {
  30         .name           = "sh-sci",
  31         .id             = 0,
  32         .resource       = scif0_resources,
  33         .num_resources  = ARRAY_SIZE(scif0_resources),
  34         .dev            = {
  35                 .platform_data  = &scif0_platform_data,
  36         },
  37 };
  38
  39 static struct sh_timer_config tmu0_platform_data = {
  40         .channels_mask = 7,
  41 };
  42
  43 static struct resource tmu0_resources[] = {
  44         DEFINE_RES_MEM(0xffd80000, 0x30),
  45         DEFINE_RES_IRQ(evt2irq(0x400)),
  46         DEFINE_RES_IRQ(evt2irq(0x420)),
  47         DEFINE_RES_IRQ(evt2irq(0x440)),
  48 };
  49
  50 static struct platform_device tmu0_device = {
  51         .name           = "sh-tmu",
  52         .id             = 0,
  53         .dev = {
  54                 .platform_data  = &tmu0_platform_data,
  55         },
  56         .resource       = tmu0_resources,
  57         .num_resources  = ARRAY_SIZE(tmu0_resources),
  58 };
  59
  60 static struct platform_device *sh4202_devices[] __initdata = {
  61         &scif0_device,
  62         &tmu0_device,
  63 };
  64
  65 static int __init sh4202_devices_setup(void)
  66 {
  67         return platform_add_devices(sh4202_devices,
  68                                     ARRAY_SIZE(sh4202_devices));
  69 }
  70 arch_initcall(sh4202_devices_setup);
  71
  72 static struct platform_device *sh4202_early_devices[] __initdata = {
  73         &scif0_device,
  74         &tmu0_device,
  75 };
  76
  77 void __init plat_early_device_setup(void)
  78 {
  79         early_platform_add_devices(sh4202_early_devices,
  80                                    ARRAY_SIZE(sh4202_early_devices));
  81 }
  82
  83 enum {
  84         UNUSED = 0,
  85
  86         /* interrupt sources */
  87         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
  88         HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
  89 };
  90
  91 static struct intc_vect vectors[] __initdata = {
  92         INTC_VECT(HUDI, 0x600),
  93         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  94         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  95         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
  96         INTC_VECT(RTC, 0x4c0),
  97         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
  98         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
  99         INTC_VECT(WDT, 0x560),
 100 };
 101
 102 static struct intc_prio_reg prio_registers[] __initdata = {
 103         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 104         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
 105         { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
 106         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 107 };
 108
 109 static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
 110                          NULL, prio_registers, NULL);
 111
 112 static struct intc_vect vectors_irlm[] __initdata = {
 113         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 114         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 115 };
 116
 117 static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
 118                          NULL, prio_registers, NULL);
 119
 120 void __init plat_irq_setup(void)
 121 {
 122         register_intc_controller(&intc_desc);
 123 }
 124
 125 #define INTC_ICR        0xffd00000UL
 126 #define INTC_ICR_IRLM   (1<<7)
 127
 128 void __init plat_irq_setup_pins(int mode)
 129 {
 130         switch (mode) {
 131         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 132                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 133                 register_intc_controller(&intc_desc_irlm);
 134                 break;
 135         default:
 136                 BUG();
 137         }
 138 }