arch/sh/kernel/cpu/sh4a/setup-sh7723.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH7723 Setup
   4  *
   5  *  Copyright (C) 2008  Paul Mundt
   6  */
   7 #include <linux/platform_device.h>
   8 #include <linux/init.h>
   9 #include <linux/serial.h>
  10 #include <linux/mm.h>
  11 #include <linux/serial_sci.h>
  12 #include <linux/uio_driver.h>
  13 #include <linux/usb/r8a66597.h>
  14 #include <linux/sh_timer.h>
  15 #include <linux/sh_intc.h>
  16 #include <linux/io.h>
  17 #include <asm/clock.h>
  18 #include <asm/mmzone.h>
  19 #include <cpu/sh7723.h>
  20
  21 /* Serial */
  22 static struct plat_sci_port scif0_platform_data = {
  23         .scscr          = SCSCR_REIE,
  24         .type           = PORT_SCIF,
  25         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
  26 };
  27
  28 static struct resource scif0_resources[] = {
  29         DEFINE_RES_MEM(0xffe00000, 0x100),
  30         DEFINE_RES_IRQ(evt2irq(0xc00)),
  31 };
  32
  33 static struct platform_device scif0_device = {
  34         .name           = "sh-sci",
  35         .id             = 0,
  36         .resource       = scif0_resources,
  37         .num_resources  = ARRAY_SIZE(scif0_resources),
  38         .dev            = {
  39                 .platform_data  = &scif0_platform_data,
  40         },
  41 };
  42
  43 static struct plat_sci_port scif1_platform_data = {
  44         .scscr          = SCSCR_REIE,
  45         .type           = PORT_SCIF,
  46         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
  47 };
  48
  49 static struct resource scif1_resources[] = {
  50         DEFINE_RES_MEM(0xffe10000, 0x100),
  51         DEFINE_RES_IRQ(evt2irq(0xc20)),
  52 };
  53
  54 static struct platform_device scif1_device = {
  55         .name           = "sh-sci",
  56         .id             = 1,
  57         .resource       = scif1_resources,
  58         .num_resources  = ARRAY_SIZE(scif1_resources),
  59         .dev            = {
  60                 .platform_data  = &scif1_platform_data,
  61         },
  62 };
  63
  64 static struct plat_sci_port scif2_platform_data = {
  65         .scscr          = SCSCR_REIE,
  66         .type           = PORT_SCIF,
  67         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
  68 };
  69
  70 static struct resource scif2_resources[] = {
  71         DEFINE_RES_MEM(0xffe20000, 0x100),
  72         DEFINE_RES_IRQ(evt2irq(0xc40)),
  73 };
  74
  75 static struct platform_device scif2_device = {
  76         .name           = "sh-sci",
  77         .id             = 2,
  78         .resource       = scif2_resources,
  79         .num_resources  = ARRAY_SIZE(scif2_resources),
  80         .dev            = {
  81                 .platform_data  = &scif2_platform_data,
  82         },
  83 };
  84
  85 static struct plat_sci_port scif3_platform_data = {
  86         .sampling_rate  = 8,
  87         .type           = PORT_SCIFA,
  88 };
  89
  90 static struct resource scif3_resources[] = {
  91         DEFINE_RES_MEM(0xa4e30000, 0x100),
  92         DEFINE_RES_IRQ(evt2irq(0x900)),
  93 };
  94
  95 static struct platform_device scif3_device = {
  96         .name           = "sh-sci",
  97         .id             = 3,
  98         .resource       = scif3_resources,
  99         .num_resources  = ARRAY_SIZE(scif3_resources),
 100         .dev            = {
 101                 .platform_data  = &scif3_platform_data,
 102         },
 103 };
 104
 105 static struct plat_sci_port scif4_platform_data = {
 106         .sampling_rate  = 8,
 107         .type           = PORT_SCIFA,
 108 };
 109
 110 static struct resource scif4_resources[] = {
 111         DEFINE_RES_MEM(0xa4e40000, 0x100),
 112         DEFINE_RES_IRQ(evt2irq(0xd00)),
 113 };
 114
 115 static struct platform_device scif4_device = {
 116         .name           = "sh-sci",
 117         .id             = 4,
 118         .resource       = scif4_resources,
 119         .num_resources  = ARRAY_SIZE(scif4_resources),
 120         .dev            = {
 121                 .platform_data  = &scif4_platform_data,
 122         },
 123 };
 124
 125 static struct plat_sci_port scif5_platform_data = {
 126         .sampling_rate  = 8,
 127         .type           = PORT_SCIFA,
 128 };
 129
 130 static struct resource scif5_resources[] = {
 131         DEFINE_RES_MEM(0xa4e50000, 0x100),
 132         DEFINE_RES_IRQ(evt2irq(0xfa0)),
 133 };
 134
 135 static struct platform_device scif5_device = {
 136         .name           = "sh-sci",
 137         .id             = 5,
 138         .resource       = scif5_resources,
 139         .num_resources  = ARRAY_SIZE(scif5_resources),
 140         .dev            = {
 141                 .platform_data  = &scif5_platform_data,
 142         },
 143 };
 144
 145 static struct uio_info vpu_platform_data = {
 146         .name = "VPU5",
 147         .version = "0",
 148         .irq = evt2irq(0x980),
 149 };
 150
 151 static struct resource vpu_resources[] = {
 152         [0] = {
 153                 .name   = "VPU",
 154                 .start  = 0xfe900000,
 155                 .end    = 0xfe902807,
 156                 .flags  = IORESOURCE_MEM,
 157         },
 158         [1] = {
 159                 /* place holder for contiguous memory */
 160         },
 161 };
 162
 163 static struct platform_device vpu_device = {
 164         .name           = "uio_pdrv_genirq",
 165         .id             = 0,
 166         .dev = {
 167                 .platform_data  = &vpu_platform_data,
 168         },
 169         .resource       = vpu_resources,
 170         .num_resources  = ARRAY_SIZE(vpu_resources),
 171 };
 172
 173 static struct uio_info veu0_platform_data = {
 174         .name = "VEU2H",
 175         .version = "0",
 176         .irq = evt2irq(0x8c0),
 177 };
 178
 179 static struct resource veu0_resources[] = {
 180         [0] = {
 181                 .name   = "VEU2H0",
 182                 .start  = 0xfe920000,
 183                 .end    = 0xfe92027b,
 184                 .flags  = IORESOURCE_MEM,
 185         },
 186         [1] = {
 187                 /* place holder for contiguous memory */
 188         },
 189 };
 190
 191 static struct platform_device veu0_device = {
 192         .name           = "uio_pdrv_genirq",
 193         .id             = 1,
 194         .dev = {
 195                 .platform_data  = &veu0_platform_data,
 196         },
 197         .resource       = veu0_resources,
 198         .num_resources  = ARRAY_SIZE(veu0_resources),
 199 };
 200
 201 static struct uio_info veu1_platform_data = {
 202         .name = "VEU2H",
 203         .version = "0",
 204         .irq = evt2irq(0x560),
 205 };
 206
 207 static struct resource veu1_resources[] = {
 208         [0] = {
 209                 .name   = "VEU2H1",
 210                 .start  = 0xfe924000,
 211                 .end    = 0xfe92427b,
 212                 .flags  = IORESOURCE_MEM,
 213         },
 214         [1] = {
 215                 /* place holder for contiguous memory */
 216         },
 217 };
 218
 219 static struct platform_device veu1_device = {
 220         .name           = "uio_pdrv_genirq",
 221         .id             = 2,
 222         .dev = {
 223                 .platform_data  = &veu1_platform_data,
 224         },
 225         .resource       = veu1_resources,
 226         .num_resources  = ARRAY_SIZE(veu1_resources),
 227 };
 228
 229 static struct sh_timer_config cmt_platform_data = {
 230         .channels_mask = 0x20,
 231 };
 232
 233 static struct resource cmt_resources[] = {
 234         DEFINE_RES_MEM(0x044a0000, 0x70),
 235         DEFINE_RES_IRQ(evt2irq(0xf00)),
 236 };
 237
 238 static struct platform_device cmt_device = {
 239         .name           = "sh-cmt-32",
 240         .id             = 0,
 241         .dev = {
 242                 .platform_data  = &cmt_platform_data,
 243         },
 244         .resource       = cmt_resources,
 245         .num_resources  = ARRAY_SIZE(cmt_resources),
 246 };
 247
 248 static struct sh_timer_config tmu0_platform_data = {
 249         .channels_mask = 7,
 250 };
 251
 252 static struct resource tmu0_resources[] = {
 253         DEFINE_RES_MEM(0xffd80000, 0x2c),
 254         DEFINE_RES_IRQ(evt2irq(0x400)),
 255         DEFINE_RES_IRQ(evt2irq(0x420)),
 256         DEFINE_RES_IRQ(evt2irq(0x440)),
 257 };
 258
 259 static struct platform_device tmu0_device = {
 260         .name           = "sh-tmu",
 261         .id             = 0,
 262         .dev = {
 263                 .platform_data  = &tmu0_platform_data,
 264         },
 265         .resource       = tmu0_resources,
 266         .num_resources  = ARRAY_SIZE(tmu0_resources),
 267 };
 268
 269 static struct sh_timer_config tmu1_platform_data = {
 270         .channels_mask = 7,
 271 };
 272
 273 static struct resource tmu1_resources[] = {
 274         DEFINE_RES_MEM(0xffd90000, 0x2c),
 275         DEFINE_RES_IRQ(evt2irq(0x920)),
 276         DEFINE_RES_IRQ(evt2irq(0x940)),
 277         DEFINE_RES_IRQ(evt2irq(0x960)),
 278 };
 279
 280 static struct platform_device tmu1_device = {
 281         .name           = "sh-tmu",
 282         .id             = 1,
 283         .dev = {
 284                 .platform_data  = &tmu1_platform_data,
 285         },
 286         .resource       = tmu1_resources,
 287         .num_resources  = ARRAY_SIZE(tmu1_resources),
 288 };
 289
 290 static struct resource rtc_resources[] = {
 291         [0] = {
 292                 .start  = 0xa465fec0,
 293                 .end    = 0xa465fec0 + 0x58 - 1,
 294                 .flags  = IORESOURCE_IO,
 295         },
 296         [1] = {
 297                 /* Period IRQ */
 298                 .start  = evt2irq(0xaa0),
 299                 .flags  = IORESOURCE_IRQ,
 300         },
 301         [2] = {
 302                 /* Carry IRQ */
 303                 .start  = evt2irq(0xac0),
 304                 .flags  = IORESOURCE_IRQ,
 305         },
 306         [3] = {
 307                 /* Alarm IRQ */
 308                 .start  = evt2irq(0xa80),
 309                 .flags  = IORESOURCE_IRQ,
 310         },
 311 };
 312
 313 static struct platform_device rtc_device = {
 314         .name           = "sh-rtc",
 315         .id             = -1,
 316         .num_resources  = ARRAY_SIZE(rtc_resources),
 317         .resource       = rtc_resources,
 318 };
 319
 320 static struct r8a66597_platdata r8a66597_data = {
 321         .on_chip = 1,
 322 };
 323
 324 static struct resource sh7723_usb_host_resources[] = {
 325         [0] = {
 326                 .start  = 0xa4d80000,
 327                 .end    = 0xa4d800ff,
 328                 .flags  = IORESOURCE_MEM,
 329         },
 330         [1] = {
 331                 .start  = evt2irq(0xa20),
 332                 .end    = evt2irq(0xa20),
 333                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 334         },
 335 };
 336
 337 static struct platform_device sh7723_usb_host_device = {
 338         .name           = "r8a66597_hcd",
 339         .id             = 0,
 340         .dev = {
 341                 .dma_mask               = NULL,         /*  not use dma */
 342                 .coherent_dma_mask      = 0xffffffff,
 343                 .platform_data          = &r8a66597_data,
 344         },
 345         .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
 346         .resource       = sh7723_usb_host_resources,
 347 };
 348
 349 static struct resource iic_resources[] = {
 350         [0] = {
 351                 .name   = "IIC",
 352                 .start  = 0x04470000,
 353                 .end    = 0x04470017,
 354                 .flags  = IORESOURCE_MEM,
 355         },
 356         [1] = {
 357                 .start  = evt2irq(0xe00),
 358                 .end    = evt2irq(0xe60),
 359                 .flags  = IORESOURCE_IRQ,
 360        },
 361 };
 362
 363 static struct platform_device iic_device = {
 364         .name           = "i2c-sh_mobile",
 365         .id             = 0, /* "i2c0" clock */
 366         .num_resources  = ARRAY_SIZE(iic_resources),
 367         .resource       = iic_resources,
 368 };
 369
 370 static struct platform_device *sh7723_devices[] __initdata = {
 371         &scif0_device,
 372         &scif1_device,
 373         &scif2_device,
 374         &scif3_device,
 375         &scif4_device,
 376         &scif5_device,
 377         &cmt_device,
 378         &tmu0_device,
 379         &tmu1_device,
 380         &rtc_device,
 381         &iic_device,
 382         &sh7723_usb_host_device,
 383         &vpu_device,
 384         &veu0_device,
 385         &veu1_device,
 386 };
 387
 388 static int __init sh7723_devices_setup(void)
 389 {
 390         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 391         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 392         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 393
 394         return platform_add_devices(sh7723_devices,
 395                                     ARRAY_SIZE(sh7723_devices));
 396 }
 397 arch_initcall(sh7723_devices_setup);
 398
 399 static struct platform_device *sh7723_early_devices[] __initdata = {
 400         &scif0_device,
 401         &scif1_device,
 402         &scif2_device,
 403         &scif3_device,
 404         &scif4_device,
 405         &scif5_device,
 406         &cmt_device,
 407         &tmu0_device,
 408         &tmu1_device,
 409 };
 410
 411 void __init plat_early_device_setup(void)
 412 {
 413         early_platform_add_devices(sh7723_early_devices,
 414                                    ARRAY_SIZE(sh7723_early_devices));
 415 }
 416
 417 #define RAMCR_CACHE_L2FC        0x0002
 418 #define RAMCR_CACHE_L2E         0x0001
 419 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
 420
 421 void l2_cache_init(void)
 422 {
 423         /* Enable L2 cache */
 424         __raw_writel(L2_CACHE_ENABLE, RAMCR);
 425 }
 426
 427 enum {
 428         UNUSED=0,
 429         ENABLED,
 430         DISABLED,
 431
 432         /* interrupt sources */
 433         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 434         HUDI,
 435         DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
 436         _2DG_TRI,_2DG_INI,_2DG_CEI,
 437         DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
 438         VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
 439         SCIFA_SCIFA0,
 440         VPU_VPUI,
 441         TPU_TPUI,
 442         ADC_ADI,
 443         USB_USI0,
 444         RTC_ATI,RTC_PRI,RTC_CUI,
 445         DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
 446         DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
 447         KEYSC_KEYI,
 448         SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
 449         MSIOF_MSIOFI0,MSIOF_MSIOFI1,
 450         SCIFA_SCIFA1,
 451         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
 452         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
 453         CMT_CMTI,
 454         TSIF_TSIFI,
 455         SIU_SIUI,
 456         SCIFA_SCIFA2,
 457         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
 458         IRDA_IRDAI,
 459         ATAPI_ATAPII,
 460         VEU2H1_VEU2HI,
 461         LCDC_LCDCI,
 462         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
 463
 464         /* interrupt groups */
 465         DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
 466         SDHI1, RTC, DMAC1B, SDHI0,
 467 };
 468
 469 static struct intc_vect vectors[] __initdata = {
 470         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 471         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 472         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 473         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 474
 475         INTC_VECT(DMAC1A_DEI0,0x700),
 476         INTC_VECT(DMAC1A_DEI1,0x720),
 477         INTC_VECT(DMAC1A_DEI2,0x740),
 478         INTC_VECT(DMAC1A_DEI3,0x760),
 479
 480         INTC_VECT(_2DG_TRI, 0x780),
 481         INTC_VECT(_2DG_INI, 0x7A0),
 482         INTC_VECT(_2DG_CEI, 0x7C0),
 483
 484         INTC_VECT(DMAC0A_DEI0,0x800),
 485         INTC_VECT(DMAC0A_DEI1,0x820),
 486         INTC_VECT(DMAC0A_DEI2,0x840),
 487         INTC_VECT(DMAC0A_DEI3,0x860),
 488
 489         INTC_VECT(VIO_CEUI,0x880),
 490         INTC_VECT(VIO_BEUI,0x8A0),
 491         INTC_VECT(VIO_VEU2HI,0x8C0),
 492         INTC_VECT(VIO_VOUI,0x8E0),
 493
 494         INTC_VECT(SCIFA_SCIFA0,0x900),
 495         INTC_VECT(VPU_VPUI,0x980),
 496         INTC_VECT(TPU_TPUI,0x9A0),
 497         INTC_VECT(ADC_ADI,0x9E0),
 498         INTC_VECT(USB_USI0,0xA20),
 499
 500         INTC_VECT(RTC_ATI,0xA80),
 501         INTC_VECT(RTC_PRI,0xAA0),
 502         INTC_VECT(RTC_CUI,0xAC0),
 503
 504         INTC_VECT(DMAC1B_DEI4,0xB00),
 505         INTC_VECT(DMAC1B_DEI5,0xB20),
 506         INTC_VECT(DMAC1B_DADERR,0xB40),
 507
 508         INTC_VECT(DMAC0B_DEI4,0xB80),
 509         INTC_VECT(DMAC0B_DEI5,0xBA0),
 510         INTC_VECT(DMAC0B_DADERR,0xBC0),
 511
 512         INTC_VECT(KEYSC_KEYI,0xBE0),
 513         INTC_VECT(SCIF_SCIF0,0xC00),
 514         INTC_VECT(SCIF_SCIF1,0xC20),
 515         INTC_VECT(SCIF_SCIF2,0xC40),
 516         INTC_VECT(MSIOF_MSIOFI0,0xC80),
 517         INTC_VECT(MSIOF_MSIOFI1,0xCA0),
 518         INTC_VECT(SCIFA_SCIFA1,0xD00),
 519
 520         INTC_VECT(FLCTL_FLSTEI,0xD80),
 521         INTC_VECT(FLCTL_FLTENDI,0xDA0),
 522         INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
 523         INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
 524
 525         INTC_VECT(I2C_ALI,0xE00),
 526         INTC_VECT(I2C_TACKI,0xE20),
 527         INTC_VECT(I2C_WAITI,0xE40),
 528         INTC_VECT(I2C_DTEI,0xE60),
 529
 530         INTC_VECT(SDHI0, 0xE80),
 531         INTC_VECT(SDHI0, 0xEA0),
 532         INTC_VECT(SDHI0, 0xEC0),
 533
 534         INTC_VECT(CMT_CMTI,0xF00),
 535         INTC_VECT(TSIF_TSIFI,0xF20),
 536         INTC_VECT(SIU_SIUI,0xF80),
 537         INTC_VECT(SCIFA_SCIFA2,0xFA0),
 538
 539         INTC_VECT(TMU0_TUNI0,0x400),
 540         INTC_VECT(TMU0_TUNI1,0x420),
 541         INTC_VECT(TMU0_TUNI2,0x440),
 542
 543         INTC_VECT(IRDA_IRDAI,0x480),
 544         INTC_VECT(ATAPI_ATAPII,0x4A0),
 545
 546         INTC_VECT(SDHI1, 0x4E0),
 547         INTC_VECT(SDHI1, 0x500),
 548         INTC_VECT(SDHI1, 0x520),
 549
 550         INTC_VECT(VEU2H1_VEU2HI,0x560),
 551         INTC_VECT(LCDC_LCDCI,0x580),
 552
 553         INTC_VECT(TMU1_TUNI0,0x920),
 554         INTC_VECT(TMU1_TUNI1,0x940),
 555         INTC_VECT(TMU1_TUNI2,0x960),
 556
 557 };
 558
 559 static struct intc_group groups[] __initdata = {
 560         INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
 561         INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
 562         INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
 563         INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
 564         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
 565         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
 566         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
 567         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
 568         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
 569 };
 570
 571 static struct intc_mask_reg mask_registers[] __initdata = {
 572         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 573           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
 574             0, ENABLED, ENABLED, ENABLED } },
 575         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 576           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
 577         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 578           { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
 579         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 580           { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
 581         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 582           { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
 583         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 584           { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
 585         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 586           { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
 587         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 588           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 589             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
 590         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 591           { 0, ENABLED, ENABLED, ENABLED,
 592             0, 0, SCIFA_SCIFA2, SIU_SIUI } },
 593         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 594           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
 595         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 596           { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
 597         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 598           { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
 599         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
 600           { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
 601         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 602           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 603 };
 604
 605 static struct intc_prio_reg prio_registers[] __initdata = {
 606         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
 607         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
 608         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
 609         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 610         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
 611         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
 612         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
 613         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
 614         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
 615         { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
 616         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
 617         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
 618         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 619           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 620 };
 621
 622 static struct intc_sense_reg sense_registers[] __initdata = {
 623         { 0xa414001c, 16, 2, /* ICR1 */
 624           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 625 };
 626
 627 static struct intc_mask_reg ack_registers[] __initdata = {
 628         { 0xa4140024, 0, 8, /* INTREQ00 */
 629           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 630 };
 631
 632 static struct intc_desc intc_desc __initdata = {
 633         .name = "sh7723",
 634         .force_enable = ENABLED,
 635         .force_disable = DISABLED,
 636         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 637                            prio_registers, sense_registers, ack_registers),
 638 };
 639
 640 void __init plat_irq_setup(void)
 641 {
 642         register_intc_controller(&intc_desc);
 643 }