arch/sh/kernel/cpu/sh5/probe.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * arch/sh/kernel/cpu/sh5/probe.c
   4  *
   5  * CPU Subtype Probing for SH-5.
   6  *
   7  * Copyright (C) 2000, 2001  Paolo Alberelli
   8  * Copyright (C) 2003 - 2007  Paul Mundt
   9  */
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/string.h>
  13 #include <asm/processor.h>
  14 #include <asm/cache.h>
  15 #include <asm/tlb.h>
  16
  17 void cpu_probe(void)
  18 {
  19         unsigned long long cir;
  20
  21         /*
  22          * Do peeks in real mode to avoid having to set up a mapping for
  23          * the WPC registers. On SH5-101 cut2, such a mapping would be
  24          * exposed to an address translation erratum which would make it
  25          * hard to set up correctly.
  26          */
  27         cir = peek_real_address_q(0x0d000008);
  28         if ((cir & 0xffff) == 0x5103)
  29                 boot_cpu_data.type = CPU_SH5_103;
  30         else if (((cir >> 32) & 0xffff) == 0x51e2)
  31                 /* CPU.VCR aliased at CIR address on SH5-101 */
  32                 boot_cpu_data.type = CPU_SH5_101;
  33
  34         boot_cpu_data.family = CPU_FAMILY_SH5;
  35
  36         /*
  37          * First, setup some sane values for the I-cache.
  38          */
  39         boot_cpu_data.icache.ways               = 4;
  40         boot_cpu_data.icache.sets               = 256;
  41         boot_cpu_data.icache.linesz             = L1_CACHE_BYTES;
  42         boot_cpu_data.icache.way_incr           = (1 << 13);
  43         boot_cpu_data.icache.entry_shift        = 5;
  44         boot_cpu_data.icache.way_size           = boot_cpu_data.icache.sets *
  45                                                   boot_cpu_data.icache.linesz;
  46         boot_cpu_data.icache.entry_mask         = 0x1fe0;
  47         boot_cpu_data.icache.flags              = 0;
  48
  49         /*
  50          * Next, setup some sane values for the D-cache.
  51          *
  52          * On the SH5, these are pretty consistent with the I-cache settings,
  53          * so we just copy over the existing definitions.. these can be fixed
  54          * up later, especially if we add runtime CPU probing.
  55          *
  56          * Though in the meantime it saves us from having to duplicate all of
  57          * the above definitions..
  58          */
  59         boot_cpu_data.dcache            = boot_cpu_data.icache;
  60
  61         /*
  62          * Setup any cache-related flags here
  63          */
  64 #if defined(CONFIG_CACHE_WRITETHROUGH)
  65         set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags));
  66 #elif defined(CONFIG_CACHE_WRITEBACK)
  67         set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags));
  68 #endif
  69
  70         /* Setup some I/D TLB defaults */
  71         sh64_tlb_init();
  72 }