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ata: start separating SATA specific code from libata-core.c
[linux/fpc-iii.git] / drivers / iommu / dmar.c
blob071bb42bbbc5bef6eba8584ec50ce24eeea06993
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2006, Intel Corporation.
4 *
5 * Copyright (C) 2006-2008 Intel Corporation
6 * Author: Ashok Raj <ashok.raj@intel.com>
7 * Author: Shaohua Li <shaohua.li@intel.com>
8 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
9 *
10 * This file implements early detection/parsing of Remapping Devices
11 * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
12 * tables.
13 *
14 * These routines are used by both DMA-remapping and Interrupt-remapping
15 */
16
17 #define pr_fmt(fmt) "DMAR: " fmt
18
19 #include <linux/pci.h>
20 #include <linux/dmar.h>
21 #include <linux/iova.h>
22 #include <linux/intel-iommu.h>
23 #include <linux/timer.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/tboot.h>
27 #include <linux/dmi.h>
28 #include <linux/slab.h>
29 #include <linux/iommu.h>
30 #include <linux/numa.h>
31 #include <asm/irq_remapping.h>
32 #include <asm/iommu_table.h>
33
34 #include "irq_remapping.h"
35
36 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
37 struct dmar_res_callback {
38 dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED];
39 void *arg[ACPI_DMAR_TYPE_RESERVED];
40 bool ignore_unhandled;
41 bool print_entry;
42 };
43
44 /*
45 * Assumptions:
46 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
47 * before IO devices managed by that unit.
48 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
49 * after IO devices managed by that unit.
50 * 3) Hotplug events are rare.
51 *
52 * Locking rules for DMA and interrupt remapping related global data structures:
53 * 1) Use dmar_global_lock in process context
54 * 2) Use RCU in interrupt context
55 */
56 DECLARE_RWSEM(dmar_global_lock);
57 LIST_HEAD(dmar_drhd_units);
58
59 struct acpi_table_header * __initdata dmar_tbl;
60 static int dmar_dev_scope_status = 1;
61 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
62
63 static int alloc_iommu(struct dmar_drhd_unit *drhd);
64 static void free_iommu(struct intel_iommu *iommu);
65
66 extern const struct iommu_ops intel_iommu_ops;
67
68 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
69 {
70 /*
71 * add INCLUDE_ALL at the tail, so scan the list will find it at
72 * the very end.
73 */
74 if (drhd->include_all)
75 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
76 else
77 list_add_rcu(&drhd->list, &dmar_drhd_units);
78 }
79
80 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
81 {
82 struct acpi_dmar_device_scope *scope;
83
84 *cnt = 0;
85 while (start < end) {
86 scope = start;
87 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
88 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
89 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
90 (*cnt)++;
91 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
92 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
93 pr_warn("Unsupported device scope\n");
94 }
95 start += scope->length;
96 }
97 if (*cnt == 0)
98 return NULL;
99
100 return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
101 }
102
103 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
104 {
105 int i;
106 struct device *tmp_dev;
107
108 if (*devices && *cnt) {
109 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
110 put_device(tmp_dev);
111 kfree(*devices);
112 }
113
114 *devices = NULL;
115 *cnt = 0;
116 }
117
118 /* Optimize out kzalloc()/kfree() for normal cases */
119 static char dmar_pci_notify_info_buf[64];
120
121 static struct dmar_pci_notify_info *
122 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
123 {
124 int level = 0;
125 size_t size;
126 struct pci_dev *tmp;
127 struct dmar_pci_notify_info *info;
128
129 BUG_ON(dev->is_virtfn);
130
131 /* Only generate path[] for device addition event */
132 if (event == BUS_NOTIFY_ADD_DEVICE)
133 for (tmp = dev; tmp; tmp = tmp->bus->self)
134 level++;
135
136 size = struct_size(info, path, level);
137 if (size <= sizeof(dmar_pci_notify_info_buf)) {
138 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
139 } else {
140 info = kzalloc(size, GFP_KERNEL);
141 if (!info) {
142 pr_warn("Out of memory when allocating notify_info "
143 "for %s.\n", pci_name(dev));
144 if (dmar_dev_scope_status == 0)
145 dmar_dev_scope_status = -ENOMEM;
146 return NULL;
147 }
148 }
149
150 info->event = event;
151 info->dev = dev;
152 info->seg = pci_domain_nr(dev->bus);
153 info->level = level;
154 if (event == BUS_NOTIFY_ADD_DEVICE) {
155 for (tmp = dev; tmp; tmp = tmp->bus->self) {
156 level--;
157 info->path[level].bus = tmp->bus->number;
158 info->path[level].device = PCI_SLOT(tmp->devfn);
159 info->path[level].function = PCI_FUNC(tmp->devfn);
160 if (pci_is_root_bus(tmp->bus))
161 info->bus = tmp->bus->number;
162 }
163 }
164
165 return info;
166 }
167
168 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
169 {
170 if ((void *)info != dmar_pci_notify_info_buf)
171 kfree(info);
172 }
173
174 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
175 struct acpi_dmar_pci_path *path, int count)
176 {
177 int i;
178
179 if (info->bus != bus)
180 goto fallback;
181 if (info->level != count)
182 goto fallback;
183
184 for (i = 0; i < count; i++) {
185 if (path[i].device != info->path[i].device ||
186 path[i].function != info->path[i].function)
187 goto fallback;
188 }
189
190 return true;
191
192 fallback:
193
194 if (count != 1)
195 return false;
196
197 i = info->level - 1;
198 if (bus == info->path[i].bus &&
199 path[0].device == info->path[i].device &&
200 path[0].function == info->path[i].function) {
201 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
202 bus, path[0].device, path[0].function);
203 return true;
204 }
205
206 return false;
207 }
208
209 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
210 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
211 void *start, void*end, u16 segment,
212 struct dmar_dev_scope *devices,
213 int devices_cnt)
214 {
215 int i, level;
216 struct device *tmp, *dev = &info->dev->dev;
217 struct acpi_dmar_device_scope *scope;
218 struct acpi_dmar_pci_path *path;
219
220 if (segment != info->seg)
221 return 0;
222
223 for (; start < end; start += scope->length) {
224 scope = start;
225 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
226 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
227 continue;
228
229 path = (struct acpi_dmar_pci_path *)(scope + 1);
230 level = (scope->length - sizeof(*scope)) / sizeof(*path);
231 if (!dmar_match_pci_path(info, scope->bus, path, level))
232 continue;
233
234 /*
235 * We expect devices with endpoint scope to have normal PCI
236 * headers, and devices with bridge scope to have bridge PCI
237 * headers. However PCI NTB devices may be listed in the
238 * DMAR table with bridge scope, even though they have a
239 * normal PCI header. NTB devices are identified by class
240 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
241 * for this special case.
242 */
243 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
244 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
245 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
246 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
247 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) {
248 pr_warn("Device scope type does not match for %s\n",
249 pci_name(info->dev));
250 return -EINVAL;
251 }
252
253 for_each_dev_scope(devices, devices_cnt, i, tmp)
254 if (tmp == NULL) {
255 devices[i].bus = info->dev->bus->number;
256 devices[i].devfn = info->dev->devfn;
257 rcu_assign_pointer(devices[i].dev,
258 get_device(dev));
259 return 1;
260 }
261 BUG_ON(i >= devices_cnt);
262 }
263
264 return 0;
265 }
266
267 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
268 struct dmar_dev_scope *devices, int count)
269 {
270 int index;
271 struct device *tmp;
272
273 if (info->seg != segment)
274 return 0;
275
276 for_each_active_dev_scope(devices, count, index, tmp)
277 if (tmp == &info->dev->dev) {
278 RCU_INIT_POINTER(devices[index].dev, NULL);
279 synchronize_rcu();
280 put_device(tmp);
281 return 1;
282 }
283
284 return 0;
285 }
286
287 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
288 {
289 int ret = 0;
290 struct dmar_drhd_unit *dmaru;
291 struct acpi_dmar_hardware_unit *drhd;
292
293 for_each_drhd_unit(dmaru) {
294 if (dmaru->include_all)
295 continue;
296
297 drhd = container_of(dmaru->hdr,
298 struct acpi_dmar_hardware_unit, header);
299 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
300 ((void *)drhd) + drhd->header.length,
301 dmaru->segment,
302 dmaru->devices, dmaru->devices_cnt);
303 if (ret)
304 break;
305 }
306 if (ret >= 0)
307 ret = dmar_iommu_notify_scope_dev(info);
308 if (ret < 0 && dmar_dev_scope_status == 0)
309 dmar_dev_scope_status = ret;
310
311 return ret;
312 }
313
314 static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
315 {
316 struct dmar_drhd_unit *dmaru;
317
318 for_each_drhd_unit(dmaru)
319 if (dmar_remove_dev_scope(info, dmaru->segment,
320 dmaru->devices, dmaru->devices_cnt))
321 break;
322 dmar_iommu_notify_scope_dev(info);
323 }
324
325 static int dmar_pci_bus_notifier(struct notifier_block *nb,
326 unsigned long action, void *data)
327 {
328 struct pci_dev *pdev = to_pci_dev(data);
329 struct dmar_pci_notify_info *info;
330
331 /* Only care about add/remove events for physical functions.
332 * For VFs we actually do the lookup based on the corresponding
333 * PF in device_to_iommu() anyway. */
334 if (pdev->is_virtfn)
335 return NOTIFY_DONE;
336 if (action != BUS_NOTIFY_ADD_DEVICE &&
337 action != BUS_NOTIFY_REMOVED_DEVICE)
338 return NOTIFY_DONE;
339
340 info = dmar_alloc_pci_notify_info(pdev, action);
341 if (!info)
342 return NOTIFY_DONE;
343
344 down_write(&dmar_global_lock);
345 if (action == BUS_NOTIFY_ADD_DEVICE)
346 dmar_pci_bus_add_dev(info);
347 else if (action == BUS_NOTIFY_REMOVED_DEVICE)
348 dmar_pci_bus_del_dev(info);
349 up_write(&dmar_global_lock);
350
351 dmar_free_pci_notify_info(info);
352
353 return NOTIFY_OK;
354 }
355
356 static struct notifier_block dmar_pci_bus_nb = {
357 .notifier_call = dmar_pci_bus_notifier,
358 .priority = INT_MIN,
359 };
360
361 static struct dmar_drhd_unit *
362 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
363 {
364 struct dmar_drhd_unit *dmaru;
365
366 list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list)
367 if (dmaru->segment == drhd->segment &&
368 dmaru->reg_base_addr == drhd->address)
369 return dmaru;
370
371 return NULL;
372 }
373
374 /**
375 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
376 * structure which uniquely represent one DMA remapping hardware unit
377 * present in the platform
378 */
379 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
380 {
381 struct acpi_dmar_hardware_unit *drhd;
382 struct dmar_drhd_unit *dmaru;
383 int ret;
384
385 drhd = (struct acpi_dmar_hardware_unit *)header;
386 dmaru = dmar_find_dmaru(drhd);
387 if (dmaru)
388 goto out;
389
390 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
391 if (!dmaru)
392 return -ENOMEM;
393
394 /*
395 * If header is allocated from slab by ACPI _DSM method, we need to
396 * copy the content because the memory buffer will be freed on return.
397 */
398 dmaru->hdr = (void *)(dmaru + 1);
399 memcpy(dmaru->hdr, header, header->length);
400 dmaru->reg_base_addr = drhd->address;
401 dmaru->segment = drhd->segment;
402 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
403 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
404 ((void *)drhd) + drhd->header.length,
405 &dmaru->devices_cnt);
406 if (dmaru->devices_cnt && dmaru->devices == NULL) {
407 kfree(dmaru);
408 return -ENOMEM;
409 }
410
411 ret = alloc_iommu(dmaru);
412 if (ret) {
413 dmar_free_dev_scope(&dmaru->devices,
414 &dmaru->devices_cnt);
415 kfree(dmaru);
416 return ret;
417 }
418 dmar_register_drhd_unit(dmaru);
419
420 out:
421 if (arg)
422 (*(int *)arg)++;
423
424 return 0;
425 }
426
427 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
428 {
429 if (dmaru->devices && dmaru->devices_cnt)
430 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
431 if (dmaru->iommu)
432 free_iommu(dmaru->iommu);
433 kfree(dmaru);
434 }
435
436 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
437 void *arg)
438 {
439 struct acpi_dmar_andd *andd = (void *)header;
440
441 /* Check for NUL termination within the designated length */
442 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
443 WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND,
444 "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
445 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
446 dmi_get_system_info(DMI_BIOS_VENDOR),
447 dmi_get_system_info(DMI_BIOS_VERSION),
448 dmi_get_system_info(DMI_PRODUCT_VERSION));
449 return -EINVAL;
450 }
451 pr_info("ANDD device: %x name: %s\n", andd->device_number,
452 andd->device_name);
453
454 return 0;
455 }
456
457 #ifdef CONFIG_ACPI_NUMA
458 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
459 {
460 struct acpi_dmar_rhsa *rhsa;
461 struct dmar_drhd_unit *drhd;
462
463 rhsa = (struct acpi_dmar_rhsa *)header;
464 for_each_drhd_unit(drhd) {
465 if (drhd->reg_base_addr == rhsa->base_address) {
466 int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
467
468 if (!node_online(node))
469 node = NUMA_NO_NODE;
470 drhd->iommu->node = node;
471 return 0;
472 }
473 }
474 WARN_TAINT(
475 1, TAINT_FIRMWARE_WORKAROUND,
476 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
477 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
478 drhd->reg_base_addr,
479 dmi_get_system_info(DMI_BIOS_VENDOR),
480 dmi_get_system_info(DMI_BIOS_VERSION),
481 dmi_get_system_info(DMI_PRODUCT_VERSION));
482
483 return 0;
484 }
485 #else
486 #define dmar_parse_one_rhsa dmar_res_noop
487 #endif
488
489 static void
490 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
491 {
492 struct acpi_dmar_hardware_unit *drhd;
493 struct acpi_dmar_reserved_memory *rmrr;
494 struct acpi_dmar_atsr *atsr;
495 struct acpi_dmar_rhsa *rhsa;
496
497 switch (header->type) {
498 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
499 drhd = container_of(header, struct acpi_dmar_hardware_unit,
500 header);
501 pr_info("DRHD base: %#016Lx flags: %#x\n",
502 (unsigned long long)drhd->address, drhd->flags);
503 break;
504 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
505 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
506 header);
507 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
508 (unsigned long long)rmrr->base_address,
509 (unsigned long long)rmrr->end_address);
510 break;
511 case ACPI_DMAR_TYPE_ROOT_ATS:
512 atsr = container_of(header, struct acpi_dmar_atsr, header);
513 pr_info("ATSR flags: %#x\n", atsr->flags);
514 break;
515 case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
516 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
517 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
518 (unsigned long long)rhsa->base_address,
519 rhsa->proximity_domain);
520 break;
521 case ACPI_DMAR_TYPE_NAMESPACE:
522 /* We don't print this here because we need to sanity-check
523 it first. So print it in dmar_parse_one_andd() instead. */
524 break;
525 }
526 }
527
528 /**
529 * dmar_table_detect - checks to see if the platform supports DMAR devices
530 */
531 static int __init dmar_table_detect(void)
532 {
533 acpi_status status = AE_OK;
534
535 /* if we could find DMAR table, then there are DMAR devices */
536 status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
537
538 if (ACPI_SUCCESS(status) && !dmar_tbl) {
539 pr_warn("Unable to map DMAR\n");
540 status = AE_NOT_FOUND;
541 }
542
543 return ACPI_SUCCESS(status) ? 0 : -ENOENT;
544 }
545
546 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
547 size_t len, struct dmar_res_callback *cb)
548 {
549 struct acpi_dmar_header *iter, *next;
550 struct acpi_dmar_header *end = ((void *)start) + len;
551
552 for (iter = start; iter < end; iter = next) {
553 next = (void *)iter + iter->length;
554 if (iter->length == 0) {
555 /* Avoid looping forever on bad ACPI tables */
556 pr_debug(FW_BUG "Invalid 0-length structure\n");
557 break;
558 } else if (next > end) {
559 /* Avoid passing table end */
560 pr_warn(FW_BUG "Record passes table end\n");
561 return -EINVAL;
562 }
563
564 if (cb->print_entry)
565 dmar_table_print_dmar_entry(iter);
566
567 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
568 /* continue for forward compatibility */
569 pr_debug("Unknown DMAR structure type %d\n",
570 iter->type);
571 } else if (cb->cb[iter->type]) {
572 int ret;
573
574 ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
575 if (ret)
576 return ret;
577 } else if (!cb->ignore_unhandled) {
578 pr_warn("No handler for DMAR structure type %d\n",
579 iter->type);
580 return -EINVAL;
581 }
582 }
583
584 return 0;
585 }
586
587 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
588 struct dmar_res_callback *cb)
589 {
590 return dmar_walk_remapping_entries((void *)(dmar + 1),
591 dmar->header.length - sizeof(*dmar), cb);
592 }
593
594 /**
595 * parse_dmar_table - parses the DMA reporting table
596 */
597 static int __init
598 parse_dmar_table(void)
599 {
600 struct acpi_table_dmar *dmar;
601 int drhd_count = 0;
602 int ret;
603 struct dmar_res_callback cb = {
604 .print_entry = true,
605 .ignore_unhandled = true,
606 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
607 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
608 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
609 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
610 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
611 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
612 };
613
614 /*
615 * Do it again, earlier dmar_tbl mapping could be mapped with
616 * fixed map.
617 */
618 dmar_table_detect();
619
620 /*
621 * ACPI tables may not be DMA protected by tboot, so use DMAR copy
622 * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
623 */
624 dmar_tbl = tboot_get_dmar_table(dmar_tbl);
625
626 dmar = (struct acpi_table_dmar *)dmar_tbl;
627 if (!dmar)
628 return -ENODEV;
629
630 if (dmar->width < PAGE_SHIFT - 1) {
631 pr_warn("Invalid DMAR haw\n");
632 return -EINVAL;
633 }
634
635 pr_info("Host address width %d\n", dmar->width + 1);
636 ret = dmar_walk_dmar_table(dmar, &cb);
637 if (ret == 0 && drhd_count == 0)
638 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
639
640 return ret;
641 }
642
643 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
644 int cnt, struct pci_dev *dev)
645 {
646 int index;
647 struct device *tmp;
648
649 while (dev) {
650 for_each_active_dev_scope(devices, cnt, index, tmp)
651 if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
652 return 1;
653
654 /* Check our parent */
655 dev = dev->bus->self;
656 }
657
658 return 0;
659 }
660
661 struct dmar_drhd_unit *
662 dmar_find_matched_drhd_unit(struct pci_dev *dev)
663 {
664 struct dmar_drhd_unit *dmaru;
665 struct acpi_dmar_hardware_unit *drhd;
666
667 dev = pci_physfn(dev);
668
669 rcu_read_lock();
670 for_each_drhd_unit(dmaru) {
671 drhd = container_of(dmaru->hdr,
672 struct acpi_dmar_hardware_unit,
673 header);
674
675 if (dmaru->include_all &&
676 drhd->segment == pci_domain_nr(dev->bus))
677 goto out;
678
679 if (dmar_pci_device_match(dmaru->devices,
680 dmaru->devices_cnt, dev))
681 goto out;
682 }
683 dmaru = NULL;
684 out:
685 rcu_read_unlock();
686
687 return dmaru;
688 }
689
690 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
691 struct acpi_device *adev)
692 {
693 struct dmar_drhd_unit *dmaru;
694 struct acpi_dmar_hardware_unit *drhd;
695 struct acpi_dmar_device_scope *scope;
696 struct device *tmp;
697 int i;
698 struct acpi_dmar_pci_path *path;
699
700 for_each_drhd_unit(dmaru) {
701 drhd = container_of(dmaru->hdr,
702 struct acpi_dmar_hardware_unit,
703 header);
704
705 for (scope = (void *)(drhd + 1);
706 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
707 scope = ((void *)scope) + scope->length) {
708 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
709 continue;
710 if (scope->enumeration_id != device_number)
711 continue;
712
713 path = (void *)(scope + 1);
714 pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
715 dev_name(&adev->dev), dmaru->reg_base_addr,
716 scope->bus, path->device, path->function);
717 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
718 if (tmp == NULL) {
719 dmaru->devices[i].bus = scope->bus;
720 dmaru->devices[i].devfn = PCI_DEVFN(path->device,
721 path->function);
722 rcu_assign_pointer(dmaru->devices[i].dev,
723 get_device(&adev->dev));
724 return;
725 }
726 BUG_ON(i >= dmaru->devices_cnt);
727 }
728 }
729 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
730 device_number, dev_name(&adev->dev));
731 }
732
733 static int __init dmar_acpi_dev_scope_init(void)
734 {
735 struct acpi_dmar_andd *andd;
736
737 if (dmar_tbl == NULL)
738 return -ENODEV;
739
740 for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
741 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
742 andd = ((void *)andd) + andd->header.length) {
743 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
744 acpi_handle h;
745 struct acpi_device *adev;
746
747 if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
748 andd->device_name,
749 &h))) {
750 pr_err("Failed to find handle for ACPI object %s\n",
751 andd->device_name);
752 continue;
753 }
754 if (acpi_bus_get_device(h, &adev)) {
755 pr_err("Failed to get device for ACPI object %s\n",
756 andd->device_name);
757 continue;
758 }
759 dmar_acpi_insert_dev_scope(andd->device_number, adev);
760 }
761 }
762 return 0;
763 }
764
765 int __init dmar_dev_scope_init(void)
766 {
767 struct pci_dev *dev = NULL;
768 struct dmar_pci_notify_info *info;
769
770 if (dmar_dev_scope_status != 1)
771 return dmar_dev_scope_status;
772
773 if (list_empty(&dmar_drhd_units)) {
774 dmar_dev_scope_status = -ENODEV;
775 } else {
776 dmar_dev_scope_status = 0;
777
778 dmar_acpi_dev_scope_init();
779
780 for_each_pci_dev(dev) {
781 if (dev->is_virtfn)
782 continue;
783
784 info = dmar_alloc_pci_notify_info(dev,
785 BUS_NOTIFY_ADD_DEVICE);
786 if (!info) {
787 return dmar_dev_scope_status;
788 } else {
789 dmar_pci_bus_add_dev(info);
790 dmar_free_pci_notify_info(info);
791 }
792 }
793 }
794
795 return dmar_dev_scope_status;
796 }
797
798 void __init dmar_register_bus_notifier(void)
799 {
800 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
801 }
802
803
804 int __init dmar_table_init(void)
805 {
806 static int dmar_table_initialized;
807 int ret;
808
809 if (dmar_table_initialized == 0) {
810 ret = parse_dmar_table();
811 if (ret < 0) {
812 if (ret != -ENODEV)
813 pr_info("Parse DMAR table failure.\n");
814 } else if (list_empty(&dmar_drhd_units)) {
815 pr_info("No DMAR devices found\n");
816 ret = -ENODEV;
817 }
818
819 if (ret < 0)
820 dmar_table_initialized = ret;
821 else
822 dmar_table_initialized = 1;
823 }
824
825 return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
826 }
827
828 static void warn_invalid_dmar(u64 addr, const char *message)
829 {
830 WARN_TAINT_ONCE(
831 1, TAINT_FIRMWARE_WORKAROUND,
832 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
833 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
834 addr, message,
835 dmi_get_system_info(DMI_BIOS_VENDOR),
836 dmi_get_system_info(DMI_BIOS_VERSION),
837 dmi_get_system_info(DMI_PRODUCT_VERSION));
838 }
839
840 static int __ref
841 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
842 {
843 struct acpi_dmar_hardware_unit *drhd;
844 void __iomem *addr;
845 u64 cap, ecap;
846
847 drhd = (void *)entry;
848 if (!drhd->address) {
849 warn_invalid_dmar(0, "");
850 return -EINVAL;
851 }
852
853 if (arg)
854 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
855 else
856 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
857 if (!addr) {
858 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
859 return -EINVAL;
860 }
861
862 cap = dmar_readq(addr + DMAR_CAP_REG);
863 ecap = dmar_readq(addr + DMAR_ECAP_REG);
864
865 if (arg)
866 iounmap(addr);
867 else
868 early_iounmap(addr, VTD_PAGE_SIZE);
869
870 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
871 warn_invalid_dmar(drhd->address, " returns all ones");
872 return -EINVAL;
873 }
874
875 return 0;
876 }
877
878 int __init detect_intel_iommu(void)
879 {
880 int ret;
881 struct dmar_res_callback validate_drhd_cb = {
882 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
883 .ignore_unhandled = true,
884 };
885
886 down_write(&dmar_global_lock);
887 ret = dmar_table_detect();
888 if (!ret)
889 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
890 &validate_drhd_cb);
891 if (!ret && !no_iommu && !iommu_detected && !dmar_disabled) {
892 iommu_detected = 1;
893 /* Make sure ACS will be enabled */
894 pci_request_acs();
895 }
896
897 #ifdef CONFIG_X86
898 if (!ret) {
899 x86_init.iommu.iommu_init = intel_iommu_init;
900 x86_platform.iommu_shutdown = intel_iommu_shutdown;
901 }
902
903 #endif
904
905 if (dmar_tbl) {
906 acpi_put_table(dmar_tbl);
907 dmar_tbl = NULL;
908 }
909 up_write(&dmar_global_lock);
910
911 return ret ? ret : 1;
912 }
913
914 static void unmap_iommu(struct intel_iommu *iommu)
915 {
916 iounmap(iommu->reg);
917 release_mem_region(iommu->reg_phys, iommu->reg_size);
918 }
919
920 /**
921 * map_iommu: map the iommu's registers
922 * @iommu: the iommu to map
923 * @phys_addr: the physical address of the base resgister
924 *
925 * Memory map the iommu's registers. Start w/ a single page, and
926 * possibly expand if that turns out to be insufficent.
927 */
928 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
929 {
930 int map_size, err=0;
931
932 iommu->reg_phys = phys_addr;
933 iommu->reg_size = VTD_PAGE_SIZE;
934
935 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
936 pr_err("Can't reserve memory\n");
937 err = -EBUSY;
938 goto out;
939 }
940
941 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
942 if (!iommu->reg) {
943 pr_err("Can't map the region\n");
944 err = -ENOMEM;
945 goto release;
946 }
947
948 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
949 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
950
951 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
952 err = -EINVAL;
953 warn_invalid_dmar(phys_addr, " returns all ones");
954 goto unmap;
955 }
956
957 /* the registers might be more than one page */
958 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
959 cap_max_fault_reg_offset(iommu->cap));
960 map_size = VTD_PAGE_ALIGN(map_size);
961 if (map_size > iommu->reg_size) {
962 iounmap(iommu->reg);
963 release_mem_region(iommu->reg_phys, iommu->reg_size);
964 iommu->reg_size = map_size;
965 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
966 iommu->name)) {
967 pr_err("Can't reserve memory\n");
968 err = -EBUSY;
969 goto out;
970 }
971 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
972 if (!iommu->reg) {
973 pr_err("Can't map the region\n");
974 err = -ENOMEM;
975 goto release;
976 }
977 }
978 err = 0;
979 goto out;
980
981 unmap:
982 iounmap(iommu->reg);
983 release:
984 release_mem_region(iommu->reg_phys, iommu->reg_size);
985 out:
986 return err;
987 }
988
989 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
990 {
991 iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
992 DMAR_UNITS_SUPPORTED);
993 if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
994 iommu->seq_id = -1;
995 } else {
996 set_bit(iommu->seq_id, dmar_seq_ids);
997 sprintf(iommu->name, "dmar%d", iommu->seq_id);
998 }
999
1000 return iommu->seq_id;
1001 }
1002
1003 static void dmar_free_seq_id(struct intel_iommu *iommu)
1004 {
1005 if (iommu->seq_id >= 0) {
1006 clear_bit(iommu->seq_id, dmar_seq_ids);
1007 iommu->seq_id = -1;
1008 }
1009 }
1010
1011 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1012 {
1013 struct intel_iommu *iommu;
1014 u32 ver, sts;
1015 int agaw = 0;
1016 int msagaw = 0;
1017 int err;
1018
1019 if (!drhd->reg_base_addr) {
1020 warn_invalid_dmar(0, "");
1021 return -EINVAL;
1022 }
1023
1024 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1025 if (!iommu)
1026 return -ENOMEM;
1027
1028 if (dmar_alloc_seq_id(iommu) < 0) {
1029 pr_err("Failed to allocate seq_id\n");
1030 err = -ENOSPC;
1031 goto error;
1032 }
1033
1034 err = map_iommu(iommu, drhd->reg_base_addr);
1035 if (err) {
1036 pr_err("Failed to map %s\n", iommu->name);
1037 goto error_free_seq_id;
1038 }
1039
1040 err = -EINVAL;
1041 agaw = iommu_calculate_agaw(iommu);
1042 if (agaw < 0) {
1043 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1044 iommu->seq_id);
1045 goto err_unmap;
1046 }
1047 msagaw = iommu_calculate_max_sagaw(iommu);
1048 if (msagaw < 0) {
1049 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1050 iommu->seq_id);
1051 goto err_unmap;
1052 }
1053 iommu->agaw = agaw;
1054 iommu->msagaw = msagaw;
1055 iommu->segment = drhd->segment;
1056
1057 iommu->node = NUMA_NO_NODE;
1058
1059 ver = readl(iommu->reg + DMAR_VER_REG);
1060 pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1061 iommu->name,
1062 (unsigned long long)drhd->reg_base_addr,
1063 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1064 (unsigned long long)iommu->cap,
1065 (unsigned long long)iommu->ecap);
1066
1067 /* Reflect status in gcmd */
1068 sts = readl(iommu->reg + DMAR_GSTS_REG);
1069 if (sts & DMA_GSTS_IRES)
1070 iommu->gcmd |= DMA_GCMD_IRE;
1071 if (sts & DMA_GSTS_TES)
1072 iommu->gcmd |= DMA_GCMD_TE;
1073 if (sts & DMA_GSTS_QIES)
1074 iommu->gcmd |= DMA_GCMD_QIE;
1075
1076 raw_spin_lock_init(&iommu->register_lock);
1077
1078 if (intel_iommu_enabled) {
1079 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1080 intel_iommu_groups,
1081 "%s", iommu->name);
1082 if (err)
1083 goto err_unmap;
1084
1085 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
1086
1087 err = iommu_device_register(&iommu->iommu);
1088 if (err)
1089 goto err_unmap;
1090 }
1091
1092 drhd->iommu = iommu;
1093
1094 return 0;
1095
1096 err_unmap:
1097 unmap_iommu(iommu);
1098 error_free_seq_id:
1099 dmar_free_seq_id(iommu);
1100 error:
1101 kfree(iommu);
1102 return err;
1103 }
1104
1105 static void free_iommu(struct intel_iommu *iommu)
1106 {
1107 if (intel_iommu_enabled) {
1108 iommu_device_unregister(&iommu->iommu);
1109 iommu_device_sysfs_remove(&iommu->iommu);
1110 }
1111
1112 if (iommu->irq) {
1113 if (iommu->pr_irq) {
1114 free_irq(iommu->pr_irq, iommu);
1115 dmar_free_hwirq(iommu->pr_irq);
1116 iommu->pr_irq = 0;
1117 }
1118 free_irq(iommu->irq, iommu);
1119 dmar_free_hwirq(iommu->irq);
1120 iommu->irq = 0;
1121 }
1122
1123 if (iommu->qi) {
1124 free_page((unsigned long)iommu->qi->desc);
1125 kfree(iommu->qi->desc_status);
1126 kfree(iommu->qi);
1127 }
1128
1129 if (iommu->reg)
1130 unmap_iommu(iommu);
1131
1132 dmar_free_seq_id(iommu);
1133 kfree(iommu);
1134 }
1135
1136 /*
1137 * Reclaim all the submitted descriptors which have completed its work.
1138 */
1139 static inline void reclaim_free_desc(struct q_inval *qi)
1140 {
1141 while (qi->desc_status[qi->free_tail] == QI_DONE ||
1142 qi->desc_status[qi->free_tail] == QI_ABORT) {
1143 qi->desc_status[qi->free_tail] = QI_FREE;
1144 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1145 qi->free_cnt++;
1146 }
1147 }
1148
1149 static int qi_check_fault(struct intel_iommu *iommu, int index)
1150 {
1151 u32 fault;
1152 int head, tail;
1153 struct q_inval *qi = iommu->qi;
1154 int wait_index = (index + 1) % QI_LENGTH;
1155 int shift = qi_shift(iommu);
1156
1157 if (qi->desc_status[wait_index] == QI_ABORT)
1158 return -EAGAIN;
1159
1160 fault = readl(iommu->reg + DMAR_FSTS_REG);
1161
1162 /*
1163 * If IQE happens, the head points to the descriptor associated
1164 * with the error. No new descriptors are fetched until the IQE
1165 * is cleared.
1166 */
1167 if (fault & DMA_FSTS_IQE) {
1168 head = readl(iommu->reg + DMAR_IQH_REG);
1169 if ((head >> shift) == index) {
1170 struct qi_desc *desc = qi->desc + head;
1171
1172 /*
1173 * desc->qw2 and desc->qw3 are either reserved or
1174 * used by software as private data. We won't print
1175 * out these two qw's for security consideration.
1176 */
1177 pr_err("VT-d detected invalid descriptor: qw0 = %llx, qw1 = %llx\n",
1178 (unsigned long long)desc->qw0,
1179 (unsigned long long)desc->qw1);
1180 memcpy(desc, qi->desc + (wait_index << shift),
1181 1 << shift);
1182 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1183 return -EINVAL;
1184 }
1185 }
1186
1187 /*
1188 * If ITE happens, all pending wait_desc commands are aborted.
1189 * No new descriptors are fetched until the ITE is cleared.
1190 */
1191 if (fault & DMA_FSTS_ITE) {
1192 head = readl(iommu->reg + DMAR_IQH_REG);
1193 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1194 head |= 1;
1195 tail = readl(iommu->reg + DMAR_IQT_REG);
1196 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1197
1198 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1199
1200 do {
1201 if (qi->desc_status[head] == QI_IN_USE)
1202 qi->desc_status[head] = QI_ABORT;
1203 head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1204 } while (head != tail);
1205
1206 if (qi->desc_status[wait_index] == QI_ABORT)
1207 return -EAGAIN;
1208 }
1209
1210 if (fault & DMA_FSTS_ICE)
1211 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1212
1213 return 0;
1214 }
1215
1216 /*
1217 * Submit the queued invalidation descriptor to the remapping
1218 * hardware unit and wait for its completion.
1219 */
1220 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
1221 {
1222 int rc;
1223 struct q_inval *qi = iommu->qi;
1224 int offset, shift, length;
1225 struct qi_desc wait_desc;
1226 int wait_index, index;
1227 unsigned long flags;
1228
1229 if (!qi)
1230 return 0;
1231
1232 restart:
1233 rc = 0;
1234
1235 raw_spin_lock_irqsave(&qi->q_lock, flags);
1236 while (qi->free_cnt < 3) {
1237 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1238 cpu_relax();
1239 raw_spin_lock_irqsave(&qi->q_lock, flags);
1240 }
1241
1242 index = qi->free_head;
1243 wait_index = (index + 1) % QI_LENGTH;
1244 shift = qi_shift(iommu);
1245 length = 1 << shift;
1246
1247 qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1248
1249 offset = index << shift;
1250 memcpy(qi->desc + offset, desc, length);
1251 wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
1252 QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1253 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]);
1254 wait_desc.qw2 = 0;
1255 wait_desc.qw3 = 0;
1256
1257 offset = wait_index << shift;
1258 memcpy(qi->desc + offset, &wait_desc, length);
1259
1260 qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1261 qi->free_cnt -= 2;
1262
1263 /*
1264 * update the HW tail register indicating the presence of
1265 * new descriptors.
1266 */
1267 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);
1268
1269 while (qi->desc_status[wait_index] != QI_DONE) {
1270 /*
1271 * We will leave the interrupts disabled, to prevent interrupt
1272 * context to queue another cmd while a cmd is already submitted
1273 * and waiting for completion on this cpu. This is to avoid
1274 * a deadlock where the interrupt context can wait indefinitely
1275 * for free slots in the queue.
1276 */
1277 rc = qi_check_fault(iommu, index);
1278 if (rc)
1279 break;
1280
1281 raw_spin_unlock(&qi->q_lock);
1282 cpu_relax();
1283 raw_spin_lock(&qi->q_lock);
1284 }
1285
1286 qi->desc_status[index] = QI_DONE;
1287
1288 reclaim_free_desc(qi);
1289 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1290
1291 if (rc == -EAGAIN)
1292 goto restart;
1293
1294 return rc;
1295 }
1296
1297 /*
1298 * Flush the global interrupt entry cache.
1299 */
1300 void qi_global_iec(struct intel_iommu *iommu)
1301 {
1302 struct qi_desc desc;
1303
1304 desc.qw0 = QI_IEC_TYPE;
1305 desc.qw1 = 0;
1306 desc.qw2 = 0;
1307 desc.qw3 = 0;
1308
1309 /* should never fail */
1310 qi_submit_sync(&desc, iommu);
1311 }
1312
1313 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1314 u64 type)
1315 {
1316 struct qi_desc desc;
1317
1318 desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1319 | QI_CC_GRAN(type) | QI_CC_TYPE;
1320 desc.qw1 = 0;
1321 desc.qw2 = 0;
1322 desc.qw3 = 0;
1323
1324 qi_submit_sync(&desc, iommu);
1325 }
1326
1327 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1328 unsigned int size_order, u64 type)
1329 {
1330 u8 dw = 0, dr = 0;
1331
1332 struct qi_desc desc;
1333 int ih = 0;
1334
1335 if (cap_write_drain(iommu->cap))
1336 dw = 1;
1337
1338 if (cap_read_drain(iommu->cap))
1339 dr = 1;
1340
1341 desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1342 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1343 desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1344 | QI_IOTLB_AM(size_order);
1345 desc.qw2 = 0;
1346 desc.qw3 = 0;
1347
1348 qi_submit_sync(&desc, iommu);
1349 }
1350
1351 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1352 u16 qdep, u64 addr, unsigned mask)
1353 {
1354 struct qi_desc desc;
1355
1356 if (mask) {
1357 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1358 desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1359 } else
1360 desc.qw1 = QI_DEV_IOTLB_ADDR(addr);
1361
1362 if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1363 qdep = 0;
1364
1365 desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1366 QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1367 desc.qw2 = 0;
1368 desc.qw3 = 0;
1369
1370 qi_submit_sync(&desc, iommu);
1371 }
1372
1373 /* PASID-based IOTLB invalidation */
1374 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
1375 unsigned long npages, bool ih)
1376 {
1377 struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
1378
1379 /*
1380 * npages == -1 means a PASID-selective invalidation, otherwise,
1381 * a positive value for Page-selective-within-PASID invalidation.
1382 * 0 is not a valid input.
1383 */
1384 if (WARN_ON(!npages)) {
1385 pr_err("Invalid input npages = %ld\n", npages);
1386 return;
1387 }
1388
1389 if (npages == -1) {
1390 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1391 QI_EIOTLB_DID(did) |
1392 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
1393 QI_EIOTLB_TYPE;
1394 desc.qw1 = 0;
1395 } else {
1396 int mask = ilog2(__roundup_pow_of_two(npages));
1397 unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
1398
1399 if (WARN_ON_ONCE(!ALIGN(addr, align)))
1400 addr &= ~(align - 1);
1401
1402 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1403 QI_EIOTLB_DID(did) |
1404 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
1405 QI_EIOTLB_TYPE;
1406 desc.qw1 = QI_EIOTLB_ADDR(addr) |
1407 QI_EIOTLB_IH(ih) |
1408 QI_EIOTLB_AM(mask);
1409 }
1410
1411 qi_submit_sync(&desc, iommu);
1412 }
1413
1414 /*
1415 * Disable Queued Invalidation interface.
1416 */
1417 void dmar_disable_qi(struct intel_iommu *iommu)
1418 {
1419 unsigned long flags;
1420 u32 sts;
1421 cycles_t start_time = get_cycles();
1422
1423 if (!ecap_qis(iommu->ecap))
1424 return;
1425
1426 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1427
1428 sts = readl(iommu->reg + DMAR_GSTS_REG);
1429 if (!(sts & DMA_GSTS_QIES))
1430 goto end;
1431
1432 /*
1433 * Give a chance to HW to complete the pending invalidation requests.
1434 */
1435 while ((readl(iommu->reg + DMAR_IQT_REG) !=
1436 readl(iommu->reg + DMAR_IQH_REG)) &&
1437 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1438 cpu_relax();
1439
1440 iommu->gcmd &= ~DMA_GCMD_QIE;
1441 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1442
1443 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1444 !(sts & DMA_GSTS_QIES), sts);
1445 end:
1446 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1447 }
1448
1449 /*
1450 * Enable queued invalidation.
1451 */
1452 static void __dmar_enable_qi(struct intel_iommu *iommu)
1453 {
1454 u32 sts;
1455 unsigned long flags;
1456 struct q_inval *qi = iommu->qi;
1457 u64 val = virt_to_phys(qi->desc);
1458
1459 qi->free_head = qi->free_tail = 0;
1460 qi->free_cnt = QI_LENGTH;
1461
1462 /*
1463 * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability
1464 * is present.
1465 */
1466 if (ecap_smts(iommu->ecap))
1467 val |= (1 << 11) | 1;
1468
1469 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1470
1471 /* write zero to the tail reg */
1472 writel(0, iommu->reg + DMAR_IQT_REG);
1473
1474 dmar_writeq(iommu->reg + DMAR_IQA_REG, val);
1475
1476 iommu->gcmd |= DMA_GCMD_QIE;
1477 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1478
1479 /* Make sure hardware complete it */
1480 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1481
1482 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1483 }
1484
1485 /*
1486 * Enable Queued Invalidation interface. This is a must to support
1487 * interrupt-remapping. Also used by DMA-remapping, which replaces
1488 * register based IOTLB invalidation.
1489 */
1490 int dmar_enable_qi(struct intel_iommu *iommu)
1491 {
1492 struct q_inval *qi;
1493 struct page *desc_page;
1494
1495 if (!ecap_qis(iommu->ecap))
1496 return -ENOENT;
1497
1498 /*
1499 * queued invalidation is already setup and enabled.
1500 */
1501 if (iommu->qi)
1502 return 0;
1503
1504 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1505 if (!iommu->qi)
1506 return -ENOMEM;
1507
1508 qi = iommu->qi;
1509
1510 /*
1511 * Need two pages to accommodate 256 descriptors of 256 bits each
1512 * if the remapping hardware supports scalable mode translation.
1513 */
1514 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
1515 !!ecap_smts(iommu->ecap));
1516 if (!desc_page) {
1517 kfree(qi);
1518 iommu->qi = NULL;
1519 return -ENOMEM;
1520 }
1521
1522 qi->desc = page_address(desc_page);
1523
1524 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC);
1525 if (!qi->desc_status) {
1526 free_page((unsigned long) qi->desc);
1527 kfree(qi);
1528 iommu->qi = NULL;
1529 return -ENOMEM;
1530 }
1531
1532 raw_spin_lock_init(&qi->q_lock);
1533
1534 __dmar_enable_qi(iommu);
1535
1536 return 0;
1537 }
1538
1539 /* iommu interrupt handling. Most stuff are MSI-like. */
1540
1541 enum faulttype {
1542 DMA_REMAP,
1543 INTR_REMAP,
1544 UNKNOWN,
1545 };
1546
1547 static const char *dma_remap_fault_reasons[] =
1548 {
1549 "Software",
1550 "Present bit in root entry is clear",
1551 "Present bit in context entry is clear",
1552 "Invalid context entry",
1553 "Access beyond MGAW",
1554 "PTE Write access is not set",
1555 "PTE Read access is not set",
1556 "Next page table ptr is invalid",
1557 "Root table address invalid",
1558 "Context table ptr is invalid",
1559 "non-zero reserved fields in RTP",
1560 "non-zero reserved fields in CTP",
1561 "non-zero reserved fields in PTE",
1562 "PCE for translation request specifies blocking",
1563 };
1564
1565 static const char * const dma_remap_sm_fault_reasons[] = {
1566 "SM: Invalid Root Table Address",
1567 "SM: TTM 0 for request with PASID",
1568 "SM: TTM 0 for page group request",
1569 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1570 "SM: Error attempting to access Root Entry",
1571 "SM: Present bit in Root Entry is clear",
1572 "SM: Non-zero reserved field set in Root Entry",
1573 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1574 "SM: Error attempting to access Context Entry",
1575 "SM: Present bit in Context Entry is clear",
1576 "SM: Non-zero reserved field set in the Context Entry",
1577 "SM: Invalid Context Entry",
1578 "SM: DTE field in Context Entry is clear",
1579 "SM: PASID Enable field in Context Entry is clear",
1580 "SM: PASID is larger than the max in Context Entry",
1581 "SM: PRE field in Context-Entry is clear",
1582 "SM: RID_PASID field error in Context-Entry",
1583 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1584 "SM: Error attempting to access the PASID Directory Entry",
1585 "SM: Present bit in Directory Entry is clear",
1586 "SM: Non-zero reserved field set in PASID Directory Entry",
1587 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1588 "SM: Error attempting to access PASID Table Entry",
1589 "SM: Present bit in PASID Table Entry is clear",
1590 "SM: Non-zero reserved field set in PASID Table Entry",
1591 "SM: Invalid Scalable-Mode PASID Table Entry",
1592 "SM: ERE field is clear in PASID Table Entry",
1593 "SM: SRE field is clear in PASID Table Entry",
1594 "Unknown", "Unknown",/* 0x5E-0x5F */
1595 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */
1596 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */
1597 "SM: Error attempting to access first-level paging entry",
1598 "SM: Present bit in first-level paging entry is clear",
1599 "SM: Non-zero reserved field set in first-level paging entry",
1600 "SM: Error attempting to access FL-PML4 entry",
1601 "SM: First-level entry address beyond MGAW in Nested translation",
1602 "SM: Read permission error in FL-PML4 entry in Nested translation",
1603 "SM: Read permission error in first-level paging entry in Nested translation",
1604 "SM: Write permission error in first-level paging entry in Nested translation",
1605 "SM: Error attempting to access second-level paging entry",
1606 "SM: Read/Write permission error in second-level paging entry",
1607 "SM: Non-zero reserved field set in second-level paging entry",
1608 "SM: Invalid second-level page table pointer",
1609 "SM: A/D bit update needed in second-level entry when set up in no snoop",
1610 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1611 "SM: Address in first-level translation is not canonical",
1612 "SM: U/S set 0 for first-level translation with user privilege",
1613 "SM: No execute permission for request with PASID and ER=1",
1614 "SM: Address beyond the DMA hardware max",
1615 "SM: Second-level entry address beyond the max",
1616 "SM: No write permission for Write/AtomicOp request",
1617 "SM: No read permission for Read/AtomicOp request",
1618 "SM: Invalid address-interrupt address",
1619 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */
1620 "SM: A/D bit update needed in first-level entry when set up in no snoop",
1621 };
1622
1623 static const char *irq_remap_fault_reasons[] =
1624 {
1625 "Detected reserved fields in the decoded interrupt-remapped request",
1626 "Interrupt index exceeded the interrupt-remapping table size",
1627 "Present field in the IRTE entry is clear",
1628 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1629 "Detected reserved fields in the IRTE entry",
1630 "Blocked a compatibility format interrupt request",
1631 "Blocked an interrupt request due to source-id verification failure",
1632 };
1633
1634 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1635 {
1636 if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1637 ARRAY_SIZE(irq_remap_fault_reasons))) {
1638 *fault_type = INTR_REMAP;
1639 return irq_remap_fault_reasons[fault_reason - 0x20];
1640 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 <
1641 ARRAY_SIZE(dma_remap_sm_fault_reasons))) {
1642 *fault_type = DMA_REMAP;
1643 return dma_remap_sm_fault_reasons[fault_reason - 0x30];
1644 } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1645 *fault_type = DMA_REMAP;
1646 return dma_remap_fault_reasons[fault_reason];
1647 } else {
1648 *fault_type = UNKNOWN;
1649 return "Unknown";
1650 }
1651 }
1652
1653
1654 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1655 {
1656 if (iommu->irq == irq)
1657 return DMAR_FECTL_REG;
1658 else if (iommu->pr_irq == irq)
1659 return DMAR_PECTL_REG;
1660 else
1661 BUG();
1662 }
1663
1664 void dmar_msi_unmask(struct irq_data *data)
1665 {
1666 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1667 int reg = dmar_msi_reg(iommu, data->irq);
1668 unsigned long flag;
1669
1670 /* unmask it */
1671 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1672 writel(0, iommu->reg + reg);
1673 /* Read a reg to force flush the post write */
1674 readl(iommu->reg + reg);
1675 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1676 }
1677
1678 void dmar_msi_mask(struct irq_data *data)
1679 {
1680 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1681 int reg = dmar_msi_reg(iommu, data->irq);
1682 unsigned long flag;
1683
1684 /* mask it */
1685 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1686 writel(DMA_FECTL_IM, iommu->reg + reg);
1687 /* Read a reg to force flush the post write */
1688 readl(iommu->reg + reg);
1689 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1690 }
1691
1692 void dmar_msi_write(int irq, struct msi_msg *msg)
1693 {
1694 struct intel_iommu *iommu = irq_get_handler_data(irq);
1695 int reg = dmar_msi_reg(iommu, irq);
1696 unsigned long flag;
1697
1698 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1699 writel(msg->data, iommu->reg + reg + 4);
1700 writel(msg->address_lo, iommu->reg + reg + 8);
1701 writel(msg->address_hi, iommu->reg + reg + 12);
1702 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1703 }
1704
1705 void dmar_msi_read(int irq, struct msi_msg *msg)
1706 {
1707 struct intel_iommu *iommu = irq_get_handler_data(irq);
1708 int reg = dmar_msi_reg(iommu, irq);
1709 unsigned long flag;
1710
1711 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1712 msg->data = readl(iommu->reg + reg + 4);
1713 msg->address_lo = readl(iommu->reg + reg + 8);
1714 msg->address_hi = readl(iommu->reg + reg + 12);
1715 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1716 }
1717
1718 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1719 u8 fault_reason, int pasid, u16 source_id,
1720 unsigned long long addr)
1721 {
1722 const char *reason;
1723 int fault_type;
1724
1725 reason = dmar_get_fault_reason(fault_reason, &fault_type);
1726
1727 if (fault_type == INTR_REMAP)
1728 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n",
1729 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1730 PCI_FUNC(source_id & 0xFF), addr >> 48,
1731 fault_reason, reason);
1732 else
1733 pr_err("[%s] Request device [%02x:%02x.%d] PASID %x fault addr %llx [fault reason %02d] %s\n",
1734 type ? "DMA Read" : "DMA Write",
1735 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1736 PCI_FUNC(source_id & 0xFF), pasid, addr,
1737 fault_reason, reason);
1738 return 0;
1739 }
1740
1741 #define PRIMARY_FAULT_REG_LEN (16)
1742 irqreturn_t dmar_fault(int irq, void *dev_id)
1743 {
1744 struct intel_iommu *iommu = dev_id;
1745 int reg, fault_index;
1746 u32 fault_status;
1747 unsigned long flag;
1748 static DEFINE_RATELIMIT_STATE(rs,
1749 DEFAULT_RATELIMIT_INTERVAL,
1750 DEFAULT_RATELIMIT_BURST);
1751
1752 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1753 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1754 if (fault_status && __ratelimit(&rs))
1755 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1756
1757 /* TBD: ignore advanced fault log currently */
1758 if (!(fault_status & DMA_FSTS_PPF))
1759 goto unlock_exit;
1760
1761 fault_index = dma_fsts_fault_record_index(fault_status);
1762 reg = cap_fault_reg_offset(iommu->cap);
1763 while (1) {
1764 /* Disable printing, simply clear the fault when ratelimited */
1765 bool ratelimited = !__ratelimit(&rs);
1766 u8 fault_reason;
1767 u16 source_id;
1768 u64 guest_addr;
1769 int type, pasid;
1770 u32 data;
1771 bool pasid_present;
1772
1773 /* highest 32 bits */
1774 data = readl(iommu->reg + reg +
1775 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1776 if (!(data & DMA_FRCD_F))
1777 break;
1778
1779 if (!ratelimited) {
1780 fault_reason = dma_frcd_fault_reason(data);
1781 type = dma_frcd_type(data);
1782
1783 pasid = dma_frcd_pasid_value(data);
1784 data = readl(iommu->reg + reg +
1785 fault_index * PRIMARY_FAULT_REG_LEN + 8);
1786 source_id = dma_frcd_source_id(data);
1787
1788 pasid_present = dma_frcd_pasid_present(data);
1789 guest_addr = dmar_readq(iommu->reg + reg +
1790 fault_index * PRIMARY_FAULT_REG_LEN);
1791 guest_addr = dma_frcd_page_addr(guest_addr);
1792 }
1793
1794 /* clear the fault */
1795 writel(DMA_FRCD_F, iommu->reg + reg +
1796 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1797
1798 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1799
1800 if (!ratelimited)
1801 /* Using pasid -1 if pasid is not present */
1802 dmar_fault_do_one(iommu, type, fault_reason,
1803 pasid_present ? pasid : -1,
1804 source_id, guest_addr);
1805
1806 fault_index++;
1807 if (fault_index >= cap_num_fault_regs(iommu->cap))
1808 fault_index = 0;
1809 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1810 }
1811
1812 writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO,
1813 iommu->reg + DMAR_FSTS_REG);
1814
1815 unlock_exit:
1816 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1817 return IRQ_HANDLED;
1818 }
1819
1820 int dmar_set_interrupt(struct intel_iommu *iommu)
1821 {
1822 int irq, ret;
1823
1824 /*
1825 * Check if the fault interrupt is already initialized.
1826 */
1827 if (iommu->irq)
1828 return 0;
1829
1830 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
1831 if (irq > 0) {
1832 iommu->irq = irq;
1833 } else {
1834 pr_err("No free IRQ vectors\n");
1835 return -EINVAL;
1836 }
1837
1838 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
1839 if (ret)
1840 pr_err("Can't request irq\n");
1841 return ret;
1842 }
1843
1844 int __init enable_drhd_fault_handling(void)
1845 {
1846 struct dmar_drhd_unit *drhd;
1847 struct intel_iommu *iommu;
1848
1849 /*
1850 * Enable fault control interrupt.
1851 */
1852 for_each_iommu(iommu, drhd) {
1853 u32 fault_status;
1854 int ret = dmar_set_interrupt(iommu);
1855
1856 if (ret) {
1857 pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
1858 (unsigned long long)drhd->reg_base_addr, ret);
1859 return -1;
1860 }
1861
1862 /*
1863 * Clear any previous faults.
1864 */
1865 dmar_fault(iommu->irq, iommu);
1866 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1867 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1868 }
1869
1870 return 0;
1871 }
1872
1873 /*
1874 * Re-enable Queued Invalidation interface.
1875 */
1876 int dmar_reenable_qi(struct intel_iommu *iommu)
1877 {
1878 if (!ecap_qis(iommu->ecap))
1879 return -ENOENT;
1880
1881 if (!iommu->qi)
1882 return -ENOENT;
1883
1884 /*
1885 * First disable queued invalidation.
1886 */
1887 dmar_disable_qi(iommu);
1888 /*
1889 * Then enable queued invalidation again. Since there is no pending
1890 * invalidation requests now, it's safe to re-enable queued
1891 * invalidation.
1892 */
1893 __dmar_enable_qi(iommu);
1894
1895 return 0;
1896 }
1897
1898 /*
1899 * Check interrupt remapping support in DMAR table description.
1900 */
1901 int __init dmar_ir_support(void)
1902 {
1903 struct acpi_table_dmar *dmar;
1904 dmar = (struct acpi_table_dmar *)dmar_tbl;
1905 if (!dmar)
1906 return 0;
1907 return dmar->flags & 0x1;
1908 }
1909
1910 /* Check whether DMAR units are in use */
1911 static inline bool dmar_in_use(void)
1912 {
1913 return irq_remapping_enabled || intel_iommu_enabled;
1914 }
1915
1916 static int __init dmar_free_unused_resources(void)
1917 {
1918 struct dmar_drhd_unit *dmaru, *dmaru_n;
1919
1920 if (dmar_in_use())
1921 return 0;
1922
1923 if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1924 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
1925
1926 down_write(&dmar_global_lock);
1927 list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1928 list_del(&dmaru->list);
1929 dmar_free_drhd(dmaru);
1930 }
1931 up_write(&dmar_global_lock);
1932
1933 return 0;
1934 }
1935
1936 late_initcall(dmar_free_unused_resources);
1937 IOMMU_INIT_POST(detect_intel_iommu);
1938
1939 /*
1940 * DMAR Hotplug Support
1941 * For more details, please refer to Intel(R) Virtualization Technology
1942 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
1943 * "Remapping Hardware Unit Hot Plug".
1944 */
1945 static guid_t dmar_hp_guid =
1946 GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B,
1947 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF);
1948
1949 /*
1950 * Currently there's only one revision and BIOS will not check the revision id,
1951 * so use 0 for safety.
1952 */
1953 #define DMAR_DSM_REV_ID 0
1954 #define DMAR_DSM_FUNC_DRHD 1
1955 #define DMAR_DSM_FUNC_ATSR 2
1956 #define DMAR_DSM_FUNC_RHSA 3
1957
1958 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
1959 {
1960 return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func);
1961 }
1962
1963 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
1964 dmar_res_handler_t handler, void *arg)
1965 {
1966 int ret = -ENODEV;
1967 union acpi_object *obj;
1968 struct acpi_dmar_header *start;
1969 struct dmar_res_callback callback;
1970 static int res_type[] = {
1971 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
1972 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
1973 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
1974 };
1975
1976 if (!dmar_detect_dsm(handle, func))
1977 return 0;
1978
1979 obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID,
1980 func, NULL, ACPI_TYPE_BUFFER);
1981 if (!obj)
1982 return -ENODEV;
1983
1984 memset(&callback, 0, sizeof(callback));
1985 callback.cb[res_type[func]] = handler;
1986 callback.arg[res_type[func]] = arg;
1987 start = (struct acpi_dmar_header *)obj->buffer.pointer;
1988 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
1989
1990 ACPI_FREE(obj);
1991
1992 return ret;
1993 }
1994
1995 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
1996 {
1997 int ret;
1998 struct dmar_drhd_unit *dmaru;
1999
2000 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2001 if (!dmaru)
2002 return -ENODEV;
2003
2004 ret = dmar_ir_hotplug(dmaru, true);
2005 if (ret == 0)
2006 ret = dmar_iommu_hotplug(dmaru, true);
2007
2008 return ret;
2009 }
2010
2011 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
2012 {
2013 int i, ret;
2014 struct device *dev;
2015 struct dmar_drhd_unit *dmaru;
2016
2017 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2018 if (!dmaru)
2019 return 0;
2020
2021 /*
2022 * All PCI devices managed by this unit should have been destroyed.
2023 */
2024 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
2025 for_each_active_dev_scope(dmaru->devices,
2026 dmaru->devices_cnt, i, dev)
2027 return -EBUSY;
2028 }
2029
2030 ret = dmar_ir_hotplug(dmaru, false);
2031 if (ret == 0)
2032 ret = dmar_iommu_hotplug(dmaru, false);
2033
2034 return ret;
2035 }
2036
2037 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
2038 {
2039 struct dmar_drhd_unit *dmaru;
2040
2041 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2042 if (dmaru) {
2043 list_del_rcu(&dmaru->list);
2044 synchronize_rcu();
2045 dmar_free_drhd(dmaru);
2046 }
2047
2048 return 0;
2049 }
2050
2051 static int dmar_hotplug_insert(acpi_handle handle)
2052 {
2053 int ret;
2054 int drhd_count = 0;
2055
2056 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2057 &dmar_validate_one_drhd, (void *)1);
2058 if (ret)
2059 goto out;
2060
2061 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2062 &dmar_parse_one_drhd, (void *)&drhd_count);
2063 if (ret == 0 && drhd_count == 0) {
2064 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
2065 goto out;
2066 } else if (ret) {
2067 goto release_drhd;
2068 }
2069
2070 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
2071 &dmar_parse_one_rhsa, NULL);
2072 if (ret)
2073 goto release_drhd;
2074
2075 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2076 &dmar_parse_one_atsr, NULL);
2077 if (ret)
2078 goto release_atsr;
2079
2080 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2081 &dmar_hp_add_drhd, NULL);
2082 if (!ret)
2083 return 0;
2084
2085 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2086 &dmar_hp_remove_drhd, NULL);
2087 release_atsr:
2088 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2089 &dmar_release_one_atsr, NULL);
2090 release_drhd:
2091 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2092 &dmar_hp_release_drhd, NULL);
2093 out:
2094 return ret;
2095 }
2096
2097 static int dmar_hotplug_remove(acpi_handle handle)
2098 {
2099 int ret;
2100
2101 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2102 &dmar_check_one_atsr, NULL);
2103 if (ret)
2104 return ret;
2105
2106 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2107 &dmar_hp_remove_drhd, NULL);
2108 if (ret == 0) {
2109 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2110 &dmar_release_one_atsr, NULL));
2111 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2112 &dmar_hp_release_drhd, NULL));
2113 } else {
2114 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2115 &dmar_hp_add_drhd, NULL);
2116 }
2117
2118 return ret;
2119 }
2120
2121 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
2122 void *context, void **retval)
2123 {
2124 acpi_handle *phdl = retval;
2125
2126 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2127 *phdl = handle;
2128 return AE_CTRL_TERMINATE;
2129 }
2130
2131 return AE_OK;
2132 }
2133
2134 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2135 {
2136 int ret;
2137 acpi_handle tmp = NULL;
2138 acpi_status status;
2139
2140 if (!dmar_in_use())
2141 return 0;
2142
2143 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2144 tmp = handle;
2145 } else {
2146 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2147 ACPI_UINT32_MAX,
2148 dmar_get_dsm_handle,
2149 NULL, NULL, &tmp);
2150 if (ACPI_FAILURE(status)) {
2151 pr_warn("Failed to locate _DSM method.\n");
2152 return -ENXIO;
2153 }
2154 }
2155 if (tmp == NULL)
2156 return 0;
2157
2158 down_write(&dmar_global_lock);
2159 if (insert)
2160 ret = dmar_hotplug_insert(tmp);
2161 else
2162 ret = dmar_hotplug_remove(tmp);
2163 up_write(&dmar_global_lock);
2164
2165 return ret;
2166 }
2167
2168 int dmar_device_add(acpi_handle handle)
2169 {
2170 return dmar_device_hotplug(handle, true);
2171 }
2172
2173 int dmar_device_remove(acpi_handle handle)
2174 {
2175 return dmar_device_hotplug(handle, false);
2176 }
2177
2178 /*
2179 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2180 *
2181 * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in
2182 * the ACPI DMAR table. This means that the platform boot firmware has made
2183 * sure no device can issue DMA outside of RMRR regions.
2184 */
2185 bool dmar_platform_optin(void)
2186 {
2187 struct acpi_table_dmar *dmar;
2188 acpi_status status;
2189 bool ret;
2190
2191 status = acpi_get_table(ACPI_SIG_DMAR, 0,
2192 (struct acpi_table_header **)&dmar);
2193 if (ACPI_FAILURE(status))
2194 return false;
2195
2196 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN);
2197 acpi_put_table((struct acpi_table_header *)dmar);
2198
2199 return ret;
2200 }
2201 EXPORT_SYMBOL_GPL(dmar_platform_optin);
Linux with added FPC-III support