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ata: start separating SATA specific code from libata-core.c
[linux/fpc-iii.git] / drivers / pci / controller / pcie-mobiveil.c
blob3a696ca45bfa5614ff4a1a3faaddcd4d153bb63c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Mobiveil PCIe Host controller
4 *
5 * Copyright (c) 2018 Mobiveil Inc.
6 * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/msi.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_pci.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25
26 #include "../pci.h"
27
28 /* register offsets and bit positions */
29
30 /*
31 * translation tables are grouped into windows, each window registers are
32 * grouped into blocks of 4 or 16 registers each
33 */
34 #define PAB_REG_BLOCK_SIZE 16
35 #define PAB_EXT_REG_BLOCK_SIZE 4
36
37 #define PAB_REG_ADDR(offset, win) \
38 (offset + (win * PAB_REG_BLOCK_SIZE))
39 #define PAB_EXT_REG_ADDR(offset, win) \
40 (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
41
42 #define LTSSM_STATUS 0x0404
43 #define LTSSM_STATUS_L0_MASK 0x3f
44 #define LTSSM_STATUS_L0 0x2d
45
46 #define PAB_CTRL 0x0808
47 #define AMBA_PIO_ENABLE_SHIFT 0
48 #define PEX_PIO_ENABLE_SHIFT 1
49 #define PAGE_SEL_SHIFT 13
50 #define PAGE_SEL_MASK 0x3f
51 #define PAGE_LO_MASK 0x3ff
52 #define PAGE_SEL_OFFSET_SHIFT 10
53
54 #define PAB_AXI_PIO_CTRL 0x0840
55 #define APIO_EN_MASK 0xf
56
57 #define PAB_PEX_PIO_CTRL 0x08c0
58 #define PIO_ENABLE_SHIFT 0
59
60 #define PAB_INTP_AMBA_MISC_ENB 0x0b0c
61 #define PAB_INTP_AMBA_MISC_STAT 0x0b1c
62 #define PAB_INTP_INTX_MASK 0x01e0
63 #define PAB_INTP_MSI_MASK 0x8
64
65 #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
66 #define WIN_ENABLE_SHIFT 0
67 #define WIN_TYPE_SHIFT 1
68 #define WIN_TYPE_MASK 0x3
69 #define WIN_SIZE_MASK 0xfffffc00
70
71 #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
72
73 #define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
74 #define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
75 #define AXI_WINDOW_ALIGN_MASK 3
76
77 #define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
78 #define PAB_BUS_SHIFT 24
79 #define PAB_DEVICE_SHIFT 19
80 #define PAB_FUNCTION_SHIFT 16
81
82 #define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
83 #define PAB_INTP_AXI_PIO_CLASS 0x474
84
85 #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
86 #define AMAP_CTRL_EN_SHIFT 0
87 #define AMAP_CTRL_TYPE_SHIFT 1
88 #define AMAP_CTRL_TYPE_MASK 3
89
90 #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
91 #define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
92 #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
93 #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
94 #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
95
96 /* starting offset of INTX bits in status register */
97 #define PAB_INTX_START 5
98
99 /* supported number of MSI interrupts */
100 #define PCI_NUM_MSI 16
101
102 /* MSI registers */
103 #define MSI_BASE_LO_OFFSET 0x04
104 #define MSI_BASE_HI_OFFSET 0x08
105 #define MSI_SIZE_OFFSET 0x0c
106 #define MSI_ENABLE_OFFSET 0x14
107 #define MSI_STATUS_OFFSET 0x18
108 #define MSI_DATA_OFFSET 0x20
109 #define MSI_ADDR_L_OFFSET 0x24
110 #define MSI_ADDR_H_OFFSET 0x28
111
112 /* outbound and inbound window definitions */
113 #define WIN_NUM_0 0
114 #define WIN_NUM_1 1
115 #define CFG_WINDOW_TYPE 0
116 #define IO_WINDOW_TYPE 1
117 #define MEM_WINDOW_TYPE 2
118 #define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
119 #define MAX_PIO_WINDOWS 8
120
121 /* Parameters for the waiting for link up routine */
122 #define LINK_WAIT_MAX_RETRIES 10
123 #define LINK_WAIT_MIN 90000
124 #define LINK_WAIT_MAX 100000
125
126 #define PAGED_ADDR_BNDRY 0xc00
127 #define OFFSET_TO_PAGE_ADDR(off) \
128 ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
129 #define OFFSET_TO_PAGE_IDX(off) \
130 ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
131
132 struct mobiveil_msi { /* MSI information */
133 struct mutex lock; /* protect bitmap variable */
134 struct irq_domain *msi_domain;
135 struct irq_domain *dev_domain;
136 phys_addr_t msi_pages_phys;
137 int num_of_vectors;
138 DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
139 };
140
141 struct mobiveil_pcie {
142 struct platform_device *pdev;
143 void __iomem *config_axi_slave_base; /* endpoint config base */
144 void __iomem *csr_axi_slave_base; /* root port config base */
145 void __iomem *apb_csr_base; /* MSI register base */
146 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
147 struct irq_domain *intx_domain;
148 raw_spinlock_t intx_mask_lock;
149 int irq;
150 int apio_wins;
151 int ppio_wins;
152 int ob_wins_configured; /* configured outbound windows */
153 int ib_wins_configured; /* configured inbound windows */
154 struct resource *ob_io_res;
155 char root_bus_nr;
156 struct mobiveil_msi msi;
157 };
158
159 /*
160 * mobiveil_pcie_sel_page - routine to access paged register
161 *
162 * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
163 * for this scheme to work extracted higher 6 bits of the offset will be
164 * written to pg_sel field of PAB_CTRL register and rest of the lower 10
165 * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
166 */
167 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
168 {
169 u32 val;
170
171 val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
172 val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
173 val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
174
175 writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
176 }
177
178 static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
179 {
180 if (off < PAGED_ADDR_BNDRY) {
181 /* For directly accessed registers, clear the pg_sel field */
182 mobiveil_pcie_sel_page(pcie, 0);
183 return pcie->csr_axi_slave_base + off;
184 }
185
186 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
187 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
188 }
189
190 static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
191 {
192 if ((uintptr_t)addr & (size - 1)) {
193 *val = 0;
194 return PCIBIOS_BAD_REGISTER_NUMBER;
195 }
196
197 switch (size) {
198 case 4:
199 *val = readl(addr);
200 break;
201 case 2:
202 *val = readw(addr);
203 break;
204 case 1:
205 *val = readb(addr);
206 break;
207 default:
208 *val = 0;
209 return PCIBIOS_BAD_REGISTER_NUMBER;
210 }
211
212 return PCIBIOS_SUCCESSFUL;
213 }
214
215 static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
216 {
217 if ((uintptr_t)addr & (size - 1))
218 return PCIBIOS_BAD_REGISTER_NUMBER;
219
220 switch (size) {
221 case 4:
222 writel(val, addr);
223 break;
224 case 2:
225 writew(val, addr);
226 break;
227 case 1:
228 writeb(val, addr);
229 break;
230 default:
231 return PCIBIOS_BAD_REGISTER_NUMBER;
232 }
233
234 return PCIBIOS_SUCCESSFUL;
235 }
236
237 static u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
238 {
239 void *addr;
240 u32 val;
241 int ret;
242
243 addr = mobiveil_pcie_comp_addr(pcie, off);
244
245 ret = mobiveil_pcie_read(addr, size, &val);
246 if (ret)
247 dev_err(&pcie->pdev->dev, "read CSR address failed\n");
248
249 return val;
250 }
251
252 static void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
253 size_t size)
254 {
255 void *addr;
256 int ret;
257
258 addr = mobiveil_pcie_comp_addr(pcie, off);
259
260 ret = mobiveil_pcie_write(addr, size, val);
261 if (ret)
262 dev_err(&pcie->pdev->dev, "write CSR address failed\n");
263 }
264
265 static u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
266 {
267 return mobiveil_csr_read(pcie, off, 0x4);
268 }
269
270 static void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
271 {
272 mobiveil_csr_write(pcie, val, off, 0x4);
273 }
274
275 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
276 {
277 return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
278 LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
279 }
280
281 static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
282 {
283 struct mobiveil_pcie *pcie = bus->sysdata;
284
285 /* Only one device down on each root port */
286 if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
287 return false;
288
289 /*
290 * Do not read more than one device on the bus directly
291 * attached to RC
292 */
293 if ((bus->primary == pcie->root_bus_nr) && (PCI_SLOT(devfn) > 0))
294 return false;
295
296 return true;
297 }
298
299 /*
300 * mobiveil_pcie_map_bus - routine to get the configuration base of either
301 * root port or endpoint
302 */
303 static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
304 unsigned int devfn, int where)
305 {
306 struct mobiveil_pcie *pcie = bus->sysdata;
307 u32 value;
308
309 if (!mobiveil_pcie_valid_device(bus, devfn))
310 return NULL;
311
312 /* RC config access */
313 if (bus->number == pcie->root_bus_nr)
314 return pcie->csr_axi_slave_base + where;
315
316 /*
317 * EP config access (in Config/APIO space)
318 * Program PEX Address base (31..16 bits) with appropriate value
319 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
320 * Relies on pci_lock serialization
321 */
322 value = bus->number << PAB_BUS_SHIFT |
323 PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
324 PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
325
326 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
327
328 return pcie->config_axi_slave_base + where;
329 }
330
331 static struct pci_ops mobiveil_pcie_ops = {
332 .map_bus = mobiveil_pcie_map_bus,
333 .read = pci_generic_config_read,
334 .write = pci_generic_config_write,
335 };
336
337 static void mobiveil_pcie_isr(struct irq_desc *desc)
338 {
339 struct irq_chip *chip = irq_desc_get_chip(desc);
340 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
341 struct device *dev = &pcie->pdev->dev;
342 struct mobiveil_msi *msi = &pcie->msi;
343 u32 msi_data, msi_addr_lo, msi_addr_hi;
344 u32 intr_status, msi_status;
345 unsigned long shifted_status;
346 u32 bit, virq, val, mask;
347
348 /*
349 * The core provides a single interrupt for both INTx/MSI messages.
350 * So we'll read both INTx and MSI status
351 */
352
353 chained_irq_enter(chip, desc);
354
355 /* read INTx status */
356 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
357 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
358 intr_status = val & mask;
359
360 /* Handle INTx */
361 if (intr_status & PAB_INTP_INTX_MASK) {
362 shifted_status = mobiveil_csr_readl(pcie,
363 PAB_INTP_AMBA_MISC_STAT);
364 shifted_status &= PAB_INTP_INTX_MASK;
365 shifted_status >>= PAB_INTX_START;
366 do {
367 for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
368 virq = irq_find_mapping(pcie->intx_domain,
369 bit + 1);
370 if (virq)
371 generic_handle_irq(virq);
372 else
373 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
374 bit);
375
376 /* clear interrupt handled */
377 mobiveil_csr_writel(pcie,
378 1 << (PAB_INTX_START + bit),
379 PAB_INTP_AMBA_MISC_STAT);
380 }
381
382 shifted_status = mobiveil_csr_readl(pcie,
383 PAB_INTP_AMBA_MISC_STAT);
384 shifted_status &= PAB_INTP_INTX_MASK;
385 shifted_status >>= PAB_INTX_START;
386 } while (shifted_status != 0);
387 }
388
389 /* read extra MSI status register */
390 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
391
392 /* handle MSI interrupts */
393 while (msi_status & 1) {
394 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
395
396 /*
397 * MSI_STATUS_OFFSET register gets updated to zero
398 * once we pop not only the MSI data but also address
399 * from MSI hardware FIFO. So keeping these following
400 * two dummy reads.
401 */
402 msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
403 MSI_ADDR_L_OFFSET);
404 msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
405 MSI_ADDR_H_OFFSET);
406 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
407 msi_data, msi_addr_hi, msi_addr_lo);
408
409 virq = irq_find_mapping(msi->dev_domain, msi_data);
410 if (virq)
411 generic_handle_irq(virq);
412
413 msi_status = readl_relaxed(pcie->apb_csr_base +
414 MSI_STATUS_OFFSET);
415 }
416
417 /* Clear the interrupt status */
418 mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
419 chained_irq_exit(chip, desc);
420 }
421
422 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
423 {
424 struct device *dev = &pcie->pdev->dev;
425 struct platform_device *pdev = pcie->pdev;
426 struct device_node *node = dev->of_node;
427 struct resource *res;
428
429 /* map config resource */
430 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
431 "config_axi_slave");
432 pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
433 if (IS_ERR(pcie->config_axi_slave_base))
434 return PTR_ERR(pcie->config_axi_slave_base);
435 pcie->ob_io_res = res;
436
437 /* map csr resource */
438 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
439 "csr_axi_slave");
440 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
441 if (IS_ERR(pcie->csr_axi_slave_base))
442 return PTR_ERR(pcie->csr_axi_slave_base);
443 pcie->pcie_reg_base = res->start;
444
445 /* map MSI config resource */
446 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
447 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
448 if (IS_ERR(pcie->apb_csr_base))
449 return PTR_ERR(pcie->apb_csr_base);
450
451 /* read the number of windows requested */
452 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
453 pcie->apio_wins = MAX_PIO_WINDOWS;
454
455 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
456 pcie->ppio_wins = MAX_PIO_WINDOWS;
457
458 pcie->irq = platform_get_irq(pdev, 0);
459 if (pcie->irq <= 0) {
460 dev_err(dev, "failed to map IRQ: %d\n", pcie->irq);
461 return -ENODEV;
462 }
463
464 return 0;
465 }
466
467 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
468 u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
469 {
470 u32 value;
471 u64 size64 = ~(size - 1);
472
473 if (win_num >= pcie->ppio_wins) {
474 dev_err(&pcie->pdev->dev,
475 "ERROR: max inbound windows reached !\n");
476 return;
477 }
478
479 value = mobiveil_csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
480 value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
481 value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
482 (lower_32_bits(size64) & WIN_SIZE_MASK);
483 mobiveil_csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
484
485 mobiveil_csr_writel(pcie, upper_32_bits(size64),
486 PAB_EXT_PEX_AMAP_SIZEN(win_num));
487
488 mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr),
489 PAB_PEX_AMAP_AXI_WIN(win_num));
490 mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
491 PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
492
493 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
494 PAB_PEX_AMAP_PEX_WIN_L(win_num));
495 mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
496 PAB_PEX_AMAP_PEX_WIN_H(win_num));
497
498 pcie->ib_wins_configured++;
499 }
500
501 /*
502 * routine to program the outbound windows
503 */
504 static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
505 u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
506 {
507 u32 value;
508 u64 size64 = ~(size - 1);
509
510 if (win_num >= pcie->apio_wins) {
511 dev_err(&pcie->pdev->dev,
512 "ERROR: max outbound windows reached !\n");
513 return;
514 }
515
516 /*
517 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
518 * to 4 KB in PAB_AXI_AMAP_CTRL register
519 */
520 value = mobiveil_csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
521 value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
522 value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
523 (lower_32_bits(size64) & WIN_SIZE_MASK);
524 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
525
526 mobiveil_csr_writel(pcie, upper_32_bits(size64),
527 PAB_EXT_AXI_AMAP_SIZE(win_num));
528
529 /*
530 * program AXI window base with appropriate value in
531 * PAB_AXI_AMAP_AXI_WIN0 register
532 */
533 mobiveil_csr_writel(pcie,
534 lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
535 PAB_AXI_AMAP_AXI_WIN(win_num));
536 mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
537 PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
538
539 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
540 PAB_AXI_AMAP_PEX_WIN_L(win_num));
541 mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
542 PAB_AXI_AMAP_PEX_WIN_H(win_num));
543
544 pcie->ob_wins_configured++;
545 }
546
547 static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
548 {
549 int retries;
550
551 /* check if the link is up or not */
552 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
553 if (mobiveil_pcie_link_up(pcie))
554 return 0;
555
556 usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
557 }
558
559 dev_err(&pcie->pdev->dev, "link never came up\n");
560
561 return -ETIMEDOUT;
562 }
563
564 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
565 {
566 phys_addr_t msg_addr = pcie->pcie_reg_base;
567 struct mobiveil_msi *msi = &pcie->msi;
568
569 pcie->msi.num_of_vectors = PCI_NUM_MSI;
570 msi->msi_pages_phys = (phys_addr_t)msg_addr;
571
572 writel_relaxed(lower_32_bits(msg_addr),
573 pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
574 writel_relaxed(upper_32_bits(msg_addr),
575 pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
576 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
577 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
578 }
579
580 static int mobiveil_host_init(struct mobiveil_pcie *pcie)
581 {
582 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
583 u32 value, pab_ctrl, type;
584 struct resource_entry *win;
585
586 /* setup bus numbers */
587 value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
588 value &= 0xff000000;
589 value |= 0x00ff0100;
590 mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
591
592 /*
593 * program Bus Master Enable Bit in Command Register in PAB Config
594 * Space
595 */
596 value = mobiveil_csr_readl(pcie, PCI_COMMAND);
597 value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
598 mobiveil_csr_writel(pcie, value, PCI_COMMAND);
599
600 /*
601 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
602 * register
603 */
604 pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
605 pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
606 mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
607
608 mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
609 PAB_INTP_AMBA_MISC_ENB);
610
611 /*
612 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
613 * PAB_AXI_PIO_CTRL Register
614 */
615 value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
616 value |= APIO_EN_MASK;
617 mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
618
619 /* Enable PCIe PIO master */
620 value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
621 value |= 1 << PIO_ENABLE_SHIFT;
622 mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
623
624 /*
625 * we'll program one outbound window for config reads and
626 * another default inbound window for all the upstream traffic
627 * rest of the outbound windows will be configured according to
628 * the "ranges" field defined in device tree
629 */
630
631 /* config outbound translation window */
632 program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0,
633 CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
634
635 /* memory inbound translation window */
636 program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
637
638 /* Get the I/O and memory ranges from DT */
639 resource_list_for_each_entry(win, &bridge->windows) {
640 if (resource_type(win->res) == IORESOURCE_MEM)
641 type = MEM_WINDOW_TYPE;
642 else if (resource_type(win->res) == IORESOURCE_IO)
643 type = IO_WINDOW_TYPE;
644 else
645 continue;
646
647 /* configure outbound translation window */
648 program_ob_windows(pcie, pcie->ob_wins_configured,
649 win->res->start,
650 win->res->start - win->offset,
651 type, resource_size(win->res));
652 }
653
654 /* fixup for PCIe class register */
655 value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
656 value &= 0xff;
657 value |= (PCI_CLASS_BRIDGE_PCI << 16);
658 mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
659
660 /* setup MSI hardware registers */
661 mobiveil_pcie_enable_msi(pcie);
662
663 return 0;
664 }
665
666 static void mobiveil_mask_intx_irq(struct irq_data *data)
667 {
668 struct irq_desc *desc = irq_to_desc(data->irq);
669 struct mobiveil_pcie *pcie;
670 unsigned long flags;
671 u32 mask, shifted_val;
672
673 pcie = irq_desc_get_chip_data(desc);
674 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
675 raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
676 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
677 shifted_val &= ~mask;
678 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
679 raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
680 }
681
682 static void mobiveil_unmask_intx_irq(struct irq_data *data)
683 {
684 struct irq_desc *desc = irq_to_desc(data->irq);
685 struct mobiveil_pcie *pcie;
686 unsigned long flags;
687 u32 shifted_val, mask;
688
689 pcie = irq_desc_get_chip_data(desc);
690 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
691 raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
692 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
693 shifted_val |= mask;
694 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
695 raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
696 }
697
698 static struct irq_chip intx_irq_chip = {
699 .name = "mobiveil_pcie:intx",
700 .irq_enable = mobiveil_unmask_intx_irq,
701 .irq_disable = mobiveil_mask_intx_irq,
702 .irq_mask = mobiveil_mask_intx_irq,
703 .irq_unmask = mobiveil_unmask_intx_irq,
704 };
705
706 /* routine to setup the INTx related data */
707 static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
708 irq_hw_number_t hwirq)
709 {
710 irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
711 irq_set_chip_data(irq, domain->host_data);
712
713 return 0;
714 }
715
716 /* INTx domain operations structure */
717 static const struct irq_domain_ops intx_domain_ops = {
718 .map = mobiveil_pcie_intx_map,
719 };
720
721 static struct irq_chip mobiveil_msi_irq_chip = {
722 .name = "Mobiveil PCIe MSI",
723 .irq_mask = pci_msi_mask_irq,
724 .irq_unmask = pci_msi_unmask_irq,
725 };
726
727 static struct msi_domain_info mobiveil_msi_domain_info = {
728 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
729 MSI_FLAG_PCI_MSIX),
730 .chip = &mobiveil_msi_irq_chip,
731 };
732
733 static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
734 {
735 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
736 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
737
738 msg->address_lo = lower_32_bits(addr);
739 msg->address_hi = upper_32_bits(addr);
740 msg->data = data->hwirq;
741
742 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
743 (int)data->hwirq, msg->address_hi, msg->address_lo);
744 }
745
746 static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
747 const struct cpumask *mask, bool force)
748 {
749 return -EINVAL;
750 }
751
752 static struct irq_chip mobiveil_msi_bottom_irq_chip = {
753 .name = "Mobiveil MSI",
754 .irq_compose_msi_msg = mobiveil_compose_msi_msg,
755 .irq_set_affinity = mobiveil_msi_set_affinity,
756 };
757
758 static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
759 unsigned int virq,
760 unsigned int nr_irqs, void *args)
761 {
762 struct mobiveil_pcie *pcie = domain->host_data;
763 struct mobiveil_msi *msi = &pcie->msi;
764 unsigned long bit;
765
766 WARN_ON(nr_irqs != 1);
767 mutex_lock(&msi->lock);
768
769 bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
770 if (bit >= msi->num_of_vectors) {
771 mutex_unlock(&msi->lock);
772 return -ENOSPC;
773 }
774
775 set_bit(bit, msi->msi_irq_in_use);
776
777 mutex_unlock(&msi->lock);
778
779 irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
780 domain->host_data, handle_level_irq, NULL, NULL);
781 return 0;
782 }
783
784 static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
785 unsigned int virq,
786 unsigned int nr_irqs)
787 {
788 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
789 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
790 struct mobiveil_msi *msi = &pcie->msi;
791
792 mutex_lock(&msi->lock);
793
794 if (!test_bit(d->hwirq, msi->msi_irq_in_use))
795 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
796 d->hwirq);
797 else
798 __clear_bit(d->hwirq, msi->msi_irq_in_use);
799
800 mutex_unlock(&msi->lock);
801 }
802 static const struct irq_domain_ops msi_domain_ops = {
803 .alloc = mobiveil_irq_msi_domain_alloc,
804 .free = mobiveil_irq_msi_domain_free,
805 };
806
807 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
808 {
809 struct device *dev = &pcie->pdev->dev;
810 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
811 struct mobiveil_msi *msi = &pcie->msi;
812
813 mutex_init(&pcie->msi.lock);
814 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
815 &msi_domain_ops, pcie);
816 if (!msi->dev_domain) {
817 dev_err(dev, "failed to create IRQ domain\n");
818 return -ENOMEM;
819 }
820
821 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
822 &mobiveil_msi_domain_info,
823 msi->dev_domain);
824 if (!msi->msi_domain) {
825 dev_err(dev, "failed to create MSI domain\n");
826 irq_domain_remove(msi->dev_domain);
827 return -ENOMEM;
828 }
829
830 return 0;
831 }
832
833 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
834 {
835 struct device *dev = &pcie->pdev->dev;
836 struct device_node *node = dev->of_node;
837 int ret;
838
839 /* setup INTx */
840 pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
841 &intx_domain_ops, pcie);
842
843 if (!pcie->intx_domain) {
844 dev_err(dev, "Failed to get a INTx IRQ domain\n");
845 return -ENOMEM;
846 }
847
848 raw_spin_lock_init(&pcie->intx_mask_lock);
849
850 /* setup MSI */
851 ret = mobiveil_allocate_msi_domains(pcie);
852 if (ret)
853 return ret;
854
855 return 0;
856 }
857
858 static int mobiveil_pcie_probe(struct platform_device *pdev)
859 {
860 struct mobiveil_pcie *pcie;
861 struct pci_bus *bus;
862 struct pci_bus *child;
863 struct pci_host_bridge *bridge;
864 struct device *dev = &pdev->dev;
865 int ret;
866
867 /* allocate the PCIe port */
868 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
869 if (!bridge)
870 return -ENOMEM;
871
872 pcie = pci_host_bridge_priv(bridge);
873
874 pcie->pdev = pdev;
875
876 ret = mobiveil_pcie_parse_dt(pcie);
877 if (ret) {
878 dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
879 return ret;
880 }
881
882 /* parse the host bridge base addresses from the device tree file */
883 ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
884 &bridge->dma_ranges, NULL);
885 if (ret) {
886 dev_err(dev, "Getting bridge resources failed\n");
887 return ret;
888 }
889
890 /*
891 * configure all inbound and outbound windows and prepare the RC for
892 * config access
893 */
894 ret = mobiveil_host_init(pcie);
895 if (ret) {
896 dev_err(dev, "Failed to initialize host\n");
897 return ret;
898 }
899
900 /* initialize the IRQ domains */
901 ret = mobiveil_pcie_init_irq_domain(pcie);
902 if (ret) {
903 dev_err(dev, "Failed creating IRQ Domain\n");
904 return ret;
905 }
906
907 irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
908
909 /* Initialize bridge */
910 bridge->dev.parent = dev;
911 bridge->sysdata = pcie;
912 bridge->busnr = pcie->root_bus_nr;
913 bridge->ops = &mobiveil_pcie_ops;
914 bridge->map_irq = of_irq_parse_and_map_pci;
915 bridge->swizzle_irq = pci_common_swizzle;
916
917 ret = mobiveil_bringup_link(pcie);
918 if (ret) {
919 dev_info(dev, "link bring-up failed\n");
920 return ret;
921 }
922
923 /* setup the kernel resources for the newly added PCIe root bus */
924 ret = pci_scan_root_bus_bridge(bridge);
925 if (ret)
926 return ret;
927
928 bus = bridge->bus;
929
930 pci_assign_unassigned_bus_resources(bus);
931 list_for_each_entry(child, &bus->children, node)
932 pcie_bus_configure_settings(child);
933 pci_bus_add_devices(bus);
934
935 return 0;
936 }
937
938 static const struct of_device_id mobiveil_pcie_of_match[] = {
939 {.compatible = "mbvl,gpex40-pcie",},
940 {},
941 };
942
943 MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
944
945 static struct platform_driver mobiveil_pcie_driver = {
946 .probe = mobiveil_pcie_probe,
947 .driver = {
948 .name = "mobiveil-pcie",
949 .of_match_table = mobiveil_pcie_of_match,
950 .suppress_bind_attrs = true,
951 },
952 };
953
954 builtin_platform_driver(mobiveil_pcie_driver);
955
956 MODULE_LICENSE("GPL v2");
957 MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
958 MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
Linux with added FPC-III support