drivers/net/dsa/bcm_sf2.c

   1 /*
   2  * Broadcom Starfighter 2 DSA switch driver
   3  *
   4  * Copyright (C) 2014, Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/list.h>
  13 #include <linux/module.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/of.h>
  18 #include <linux/phy.h>
  19 #include <linux/phy_fixed.h>
  20 #include <linux/mii.h>
  21 #include <linux/of.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26 #include <net/dsa.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/if_bridge.h>
  29 #include <linux/brcmphy.h>
  30 #include <linux/etherdevice.h>
  31 #include <net/switchdev.h>
  32 #include <linux/platform_data/b53.h>
  33
  34 #include "bcm_sf2.h"
  35 #include "bcm_sf2_regs.h"
  36 #include "b53/b53_priv.h"
  37 #include "b53/b53_regs.h"
  38
  39 static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
  40 {
  41         return DSA_TAG_PROTO_BRCM;
  42 }
  43
  44 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
  45 {
  46         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
  47         unsigned int i;
  48         u32 reg;
  49
  50         /* Enable the IMP Port to be in the same VLAN as the other ports
  51          * on a per-port basis such that we only have Port i and IMP in
  52          * the same VLAN.
  53          */
  54         for (i = 0; i < priv->hw_params.num_ports; i++) {
  55                 if (!((1 << i) & ds->enabled_port_mask))
  56                         continue;
  57
  58                 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
  59                 reg |= (1 << cpu_port);
  60                 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
  61         }
  62 }
  63
  64 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
  65 {
  66         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
  67         u32 reg, val;
  68
  69         /* Enable the port memories */
  70         reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
  71         reg &= ~P_TXQ_PSM_VDD(port);
  72         core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
  73
  74         /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
  75         reg = core_readl(priv, CORE_IMP_CTL);
  76         reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
  77         reg &= ~(RX_DIS | TX_DIS);
  78         core_writel(priv, reg, CORE_IMP_CTL);
  79
  80         /* Enable forwarding */
  81         core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
  82
  83         /* Enable IMP port in dumb mode */
  84         reg = core_readl(priv, CORE_SWITCH_CTRL);
  85         reg |= MII_DUMB_FWDG_EN;
  86         core_writel(priv, reg, CORE_SWITCH_CTRL);
  87
  88         /* Resolve which bit controls the Broadcom tag */
  89         switch (port) {
  90         case 8:
  91                 val = BRCM_HDR_EN_P8;
  92                 break;
  93         case 7:
  94                 val = BRCM_HDR_EN_P7;
  95                 break;
  96         case 5:
  97                 val = BRCM_HDR_EN_P5;
  98                 break;
  99         default:
 100                 val = 0;
 101                 break;
 102         }
 103
 104         /* Enable Broadcom tags for IMP port */
 105         reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
 106         reg |= val;
 107         core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
 108
 109         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 110          * allow us to tag outgoing frames
 111          */
 112         reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
 113         reg &= ~(1 << port);
 114         core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
 115
 116         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 117          * allow delivering frames to the per-port net_devices
 118          */
 119         reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
 120         reg &= ~(1 << port);
 121         core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
 122
 123         /* Force link status for IMP port */
 124         reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
 125         reg |= (MII_SW_OR | LINK_STS);
 126         core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
 127 }
 128
 129 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
 130 {
 131         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 132         u32 reg;
 133
 134         reg = core_readl(priv, CORE_EEE_EN_CTRL);
 135         if (enable)
 136                 reg |= 1 << port;
 137         else
 138                 reg &= ~(1 << port);
 139         core_writel(priv, reg, CORE_EEE_EN_CTRL);
 140 }
 141
 142 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
 143 {
 144         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 145         u32 reg;
 146
 147         reg = reg_readl(priv, REG_SPHY_CNTRL);
 148         if (enable) {
 149                 reg |= PHY_RESET;
 150                 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
 151                 reg_writel(priv, reg, REG_SPHY_CNTRL);
 152                 udelay(21);
 153                 reg = reg_readl(priv, REG_SPHY_CNTRL);
 154                 reg &= ~PHY_RESET;
 155         } else {
 156                 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
 157                 reg_writel(priv, reg, REG_SPHY_CNTRL);
 158                 mdelay(1);
 159                 reg |= CK25_DIS;
 160         }
 161         reg_writel(priv, reg, REG_SPHY_CNTRL);
 162
 163         /* Use PHY-driven LED signaling */
 164         if (!enable) {
 165                 reg = reg_readl(priv, REG_LED_CNTRL(0));
 166                 reg |= SPDLNK_SRC_SEL;
 167                 reg_writel(priv, reg, REG_LED_CNTRL(0));
 168         }
 169 }
 170
 171 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
 172                                             int port)
 173 {
 174         unsigned int off;
 175
 176         switch (port) {
 177         case 7:
 178                 off = P7_IRQ_OFF;
 179                 break;
 180         case 0:
 181                 /* Port 0 interrupts are located on the first bank */
 182                 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
 183                 return;
 184         default:
 185                 off = P_IRQ_OFF(port);
 186                 break;
 187         }
 188
 189         intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
 190 }
 191
 192 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
 193                                              int port)
 194 {
 195         unsigned int off;
 196
 197         switch (port) {
 198         case 7:
 199                 off = P7_IRQ_OFF;
 200                 break;
 201         case 0:
 202                 /* Port 0 interrupts are located on the first bank */
 203                 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
 204                 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
 205                 return;
 206         default:
 207                 off = P_IRQ_OFF(port);
 208                 break;
 209         }
 210
 211         intrl2_1_mask_set(priv, P_IRQ_MASK(off));
 212         intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
 213 }
 214
 215 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
 216                               struct phy_device *phy)
 217 {
 218         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 219         s8 cpu_port = ds->dst[ds->index].cpu_port;
 220         u32 reg;
 221
 222         /* Clear the memory power down */
 223         reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
 224         reg &= ~P_TXQ_PSM_VDD(port);
 225         core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
 226
 227         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 228         core_writel(priv, 0, CORE_G_PCTL_PORT(port));
 229
 230         /* Re-enable the GPHY and re-apply workarounds */
 231         if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
 232                 bcm_sf2_gphy_enable_set(ds, true);
 233                 if (phy) {
 234                         /* if phy_stop() has been called before, phy
 235                          * will be in halted state, and phy_start()
 236                          * will call resume.
 237                          *
 238                          * the resume path does not configure back
 239                          * autoneg settings, and since we hard reset
 240                          * the phy manually here, we need to reset the
 241                          * state machine also.
 242                          */
 243                         phy->state = PHY_READY;
 244                         phy_init_hw(phy);
 245                 }
 246         }
 247
 248         /* Enable MoCA port interrupts to get notified */
 249         if (port == priv->moca_port)
 250                 bcm_sf2_port_intr_enable(priv, port);
 251
 252         /* Set this port, and only this one to be in the default VLAN,
 253          * if member of a bridge, restore its membership prior to
 254          * bringing down this port.
 255          */
 256         reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
 257         reg &= ~PORT_VLAN_CTRL_MASK;
 258         reg |= (1 << port);
 259         reg |= priv->dev->ports[port].vlan_ctl_mask;
 260         core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
 261
 262         bcm_sf2_imp_vlan_setup(ds, cpu_port);
 263
 264         /* If EEE was enabled, restore it */
 265         if (priv->port_sts[port].eee.eee_enabled)
 266                 bcm_sf2_eee_enable_set(ds, port, true);
 267
 268         return 0;
 269 }
 270
 271 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
 272                                  struct phy_device *phy)
 273 {
 274         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 275         u32 off, reg;
 276
 277         if (priv->wol_ports_mask & (1 << port))
 278                 return;
 279
 280         if (port == priv->moca_port)
 281                 bcm_sf2_port_intr_disable(priv, port);
 282
 283         if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
 284                 bcm_sf2_gphy_enable_set(ds, false);
 285
 286         if (dsa_is_cpu_port(ds, port))
 287                 off = CORE_IMP_CTL;
 288         else
 289                 off = CORE_G_PCTL_PORT(port);
 290
 291         reg = core_readl(priv, off);
 292         reg |= RX_DIS | TX_DIS;
 293         core_writel(priv, reg, off);
 294
 295         /* Power down the port memory */
 296         reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
 297         reg |= P_TXQ_PSM_VDD(port);
 298         core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
 299 }
 300
 301 /* Returns 0 if EEE was not enabled, or 1 otherwise
 302  */
 303 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
 304                             struct phy_device *phy)
 305 {
 306         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 307         struct ethtool_eee *p = &priv->port_sts[port].eee;
 308         int ret;
 309
 310         p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
 311
 312         ret = phy_init_eee(phy, 0);
 313         if (ret)
 314                 return 0;
 315
 316         bcm_sf2_eee_enable_set(ds, port, true);
 317
 318         return 1;
 319 }
 320
 321 static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
 322                               struct ethtool_eee *e)
 323 {
 324         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 325         struct ethtool_eee *p = &priv->port_sts[port].eee;
 326         u32 reg;
 327
 328         reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
 329         e->eee_enabled = p->eee_enabled;
 330         e->eee_active = !!(reg & (1 << port));
 331
 332         return 0;
 333 }
 334
 335 static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
 336                               struct phy_device *phydev,
 337                               struct ethtool_eee *e)
 338 {
 339         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 340         struct ethtool_eee *p = &priv->port_sts[port].eee;
 341
 342         p->eee_enabled = e->eee_enabled;
 343
 344         if (!p->eee_enabled) {
 345                 bcm_sf2_eee_enable_set(ds, port, false);
 346         } else {
 347                 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
 348                 if (!p->eee_enabled)
 349                         return -EOPNOTSUPP;
 350         }
 351
 352         return 0;
 353 }
 354
 355 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
 356                                int regnum, u16 val)
 357 {
 358         int ret = 0;
 359         u32 reg;
 360
 361         reg = reg_readl(priv, REG_SWITCH_CNTRL);
 362         reg |= MDIO_MASTER_SEL;
 363         reg_writel(priv, reg, REG_SWITCH_CNTRL);
 364
 365         /* Page << 8 | offset */
 366         reg = 0x70;
 367         reg <<= 2;
 368         core_writel(priv, addr, reg);
 369
 370         /* Page << 8 | offset */
 371         reg = 0x80 << 8 | regnum << 1;
 372         reg <<= 2;
 373
 374         if (op)
 375                 ret = core_readl(priv, reg);
 376         else
 377                 core_writel(priv, val, reg);
 378
 379         reg = reg_readl(priv, REG_SWITCH_CNTRL);
 380         reg &= ~MDIO_MASTER_SEL;
 381         reg_writel(priv, reg, REG_SWITCH_CNTRL);
 382
 383         return ret & 0xffff;
 384 }
 385
 386 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
 387 {
 388         struct bcm_sf2_priv *priv = bus->priv;
 389
 390         /* Intercept reads from Broadcom pseudo-PHY address, else, send
 391          * them to our master MDIO bus controller
 392          */
 393         if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
 394                 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
 395         else
 396                 return mdiobus_read(priv->master_mii_bus, addr, regnum);
 397 }
 398
 399 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
 400                                  u16 val)
 401 {
 402         struct bcm_sf2_priv *priv = bus->priv;
 403
 404         /* Intercept writes to the Broadcom pseudo-PHY address, else,
 405          * send them to our master MDIO bus controller
 406          */
 407         if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
 408                 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
 409         else
 410                 mdiobus_write(priv->master_mii_bus, addr, regnum, val);
 411
 412         return 0;
 413 }
 414
 415 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
 416 {
 417         struct bcm_sf2_priv *priv = dev_id;
 418
 419         priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
 420                                 ~priv->irq0_mask;
 421         intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
 422
 423         return IRQ_HANDLED;
 424 }
 425
 426 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
 427 {
 428         struct bcm_sf2_priv *priv = dev_id;
 429
 430         priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
 431                                 ~priv->irq1_mask;
 432         intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
 433
 434         if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
 435                 priv->port_sts[7].link = 1;
 436         if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
 437                 priv->port_sts[7].link = 0;
 438
 439         return IRQ_HANDLED;
 440 }
 441
 442 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
 443 {
 444         unsigned int timeout = 1000;
 445         u32 reg;
 446
 447         reg = core_readl(priv, CORE_WATCHDOG_CTRL);
 448         reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
 449         core_writel(priv, reg, CORE_WATCHDOG_CTRL);
 450
 451         do {
 452                 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
 453                 if (!(reg & SOFTWARE_RESET))
 454                         break;
 455
 456                 usleep_range(1000, 2000);
 457         } while (timeout-- > 0);
 458
 459         if (timeout == 0)
 460                 return -ETIMEDOUT;
 461
 462         return 0;
 463 }
 464
 465 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
 466 {
 467         intrl2_0_mask_set(priv, 0xffffffff);
 468         intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
 469         intrl2_1_mask_set(priv, 0xffffffff);
 470         intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
 471 }
 472
 473 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
 474                                    struct device_node *dn)
 475 {
 476         struct device_node *port;
 477         const char *phy_mode_str;
 478         int mode;
 479         unsigned int port_num;
 480         int ret;
 481
 482         priv->moca_port = -1;
 483
 484         for_each_available_child_of_node(dn, port) {
 485                 if (of_property_read_u32(port, "reg", &port_num))
 486                         continue;
 487
 488                 /* Internal PHYs get assigned a specific 'phy-mode' property
 489                  * value: "internal" to help flag them before MDIO probing
 490                  * has completed, since they might be turned off at that
 491                  * time
 492                  */
 493                 mode = of_get_phy_mode(port);
 494                 if (mode < 0) {
 495                         ret = of_property_read_string(port, "phy-mode",
 496                                                       &phy_mode_str);
 497                         if (ret < 0)
 498                                 continue;
 499
 500                         if (!strcasecmp(phy_mode_str, "internal"))
 501                                 priv->int_phy_mask |= 1 << port_num;
 502                 }
 503
 504                 if (mode == PHY_INTERFACE_MODE_MOCA)
 505                         priv->moca_port = port_num;
 506         }
 507 }
 508
 509 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
 510 {
 511         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 512         struct device_node *dn;
 513         static int index;
 514         int err;
 515
 516         /* Find our integrated MDIO bus node */
 517         dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
 518         priv->master_mii_bus = of_mdio_find_bus(dn);
 519         if (!priv->master_mii_bus)
 520                 return -EPROBE_DEFER;
 521
 522         get_device(&priv->master_mii_bus->dev);
 523         priv->master_mii_dn = dn;
 524
 525         priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
 526         if (!priv->slave_mii_bus)
 527                 return -ENOMEM;
 528
 529         priv->slave_mii_bus->priv = priv;
 530         priv->slave_mii_bus->name = "sf2 slave mii";
 531         priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
 532         priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
 533         snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
 534                  index++);
 535         priv->slave_mii_bus->dev.of_node = dn;
 536
 537         /* Include the pseudo-PHY address to divert reads towards our
 538          * workaround. This is only required for 7445D0, since 7445E0
 539          * disconnects the internal switch pseudo-PHY such that we can use the
 540          * regular SWITCH_MDIO master controller instead.
 541          *
 542          * Here we flag the pseudo PHY as needing special treatment and would
 543          * otherwise make all other PHY read/writes go to the master MDIO bus
 544          * controller that comes with this switch backed by the "mdio-unimac"
 545          * driver.
 546          */
 547         if (of_machine_is_compatible("brcm,bcm7445d0"))
 548                 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
 549         else
 550                 priv->indir_phy_mask = 0;
 551
 552         ds->phys_mii_mask = priv->indir_phy_mask;
 553         ds->slave_mii_bus = priv->slave_mii_bus;
 554         priv->slave_mii_bus->parent = ds->dev->parent;
 555         priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
 556
 557         if (dn)
 558                 err = of_mdiobus_register(priv->slave_mii_bus, dn);
 559         else
 560                 err = mdiobus_register(priv->slave_mii_bus);
 561
 562         if (err)
 563                 of_node_put(dn);
 564
 565         return err;
 566 }
 567
 568 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
 569 {
 570         mdiobus_unregister(priv->slave_mii_bus);
 571         if (priv->master_mii_dn)
 572                 of_node_put(priv->master_mii_dn);
 573 }
 574
 575 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
 576 {
 577         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 578
 579         /* The BCM7xxx PHY driver expects to find the integrated PHY revision
 580          * in bits 15:8 and the patch level in bits 7:0 which is exactly what
 581          * the REG_PHY_REVISION register layout is.
 582          */
 583
 584         return priv->hw_params.gphy_rev;
 585 }
 586
 587 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
 588                                    struct phy_device *phydev)
 589 {
 590         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 591         u32 id_mode_dis = 0, port_mode;
 592         const char *str = NULL;
 593         u32 reg;
 594
 595         switch (phydev->interface) {
 596         case PHY_INTERFACE_MODE_RGMII:
 597                 str = "RGMII (no delay)";
 598                 id_mode_dis = 1;
 599         case PHY_INTERFACE_MODE_RGMII_TXID:
 600                 if (!str)
 601                         str = "RGMII (TX delay)";
 602                 port_mode = EXT_GPHY;
 603                 break;
 604         case PHY_INTERFACE_MODE_MII:
 605                 str = "MII";
 606                 port_mode = EXT_EPHY;
 607                 break;
 608         case PHY_INTERFACE_MODE_REVMII:
 609                 str = "Reverse MII";
 610                 port_mode = EXT_REVMII;
 611                 break;
 612         default:
 613                 /* All other PHYs: internal and MoCA */
 614                 goto force_link;
 615         }
 616
 617         /* If the link is down, just disable the interface to conserve power */
 618         if (!phydev->link) {
 619                 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
 620                 reg &= ~RGMII_MODE_EN;
 621                 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
 622                 goto force_link;
 623         }
 624
 625         /* Clear id_mode_dis bit, and the existing port mode, but
 626          * make sure we enable the RGMII block for data to pass
 627          */
 628         reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
 629         reg &= ~ID_MODE_DIS;
 630         reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
 631         reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
 632
 633         reg |= port_mode | RGMII_MODE_EN;
 634         if (id_mode_dis)
 635                 reg |= ID_MODE_DIS;
 636
 637         if (phydev->pause) {
 638                 if (phydev->asym_pause)
 639                         reg |= TX_PAUSE_EN;
 640                 reg |= RX_PAUSE_EN;
 641         }
 642
 643         reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
 644
 645         pr_info("Port %d configured for %s\n", port, str);
 646
 647 force_link:
 648         /* Force link settings detected from the PHY */
 649         reg = SW_OVERRIDE;
 650         switch (phydev->speed) {
 651         case SPEED_1000:
 652                 reg |= SPDSTS_1000 << SPEED_SHIFT;
 653                 break;
 654         case SPEED_100:
 655                 reg |= SPDSTS_100 << SPEED_SHIFT;
 656                 break;
 657         }
 658
 659         if (phydev->link)
 660                 reg |= LINK_STS;
 661         if (phydev->duplex == DUPLEX_FULL)
 662                 reg |= DUPLX_MODE;
 663
 664         core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
 665 }
 666
 667 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
 668                                          struct fixed_phy_status *status)
 669 {
 670         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 671         u32 duplex, pause;
 672         u32 reg;
 673
 674         duplex = core_readl(priv, CORE_DUPSTS);
 675         pause = core_readl(priv, CORE_PAUSESTS);
 676
 677         status->link = 0;
 678
 679         /* MoCA port is special as we do not get link status from CORE_LNKSTS,
 680          * which means that we need to force the link at the port override
 681          * level to get the data to flow. We do use what the interrupt handler
 682          * did determine before.
 683          *
 684          * For the other ports, we just force the link status, since this is
 685          * a fixed PHY device.
 686          */
 687         if (port == priv->moca_port) {
 688                 status->link = priv->port_sts[port].link;
 689                 /* For MoCA interfaces, also force a link down notification
 690                  * since some version of the user-space daemon (mocad) use
 691                  * cmd->autoneg to force the link, which messes up the PHY
 692                  * state machine and make it go in PHY_FORCING state instead.
 693                  */
 694                 if (!status->link)
 695                         netif_carrier_off(ds->ports[port].netdev);
 696                 status->duplex = 1;
 697         } else {
 698                 status->link = 1;
 699                 status->duplex = !!(duplex & (1 << port));
 700         }
 701
 702         reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
 703         reg |= SW_OVERRIDE;
 704         if (status->link)
 705                 reg |= LINK_STS;
 706         else
 707                 reg &= ~LINK_STS;
 708         core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
 709
 710         if ((pause & (1 << port)) &&
 711             (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
 712                 status->asym_pause = 1;
 713                 status->pause = 1;
 714         }
 715
 716         if (pause & (1 << port))
 717                 status->pause = 1;
 718 }
 719
 720 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
 721 {
 722         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 723         unsigned int port;
 724
 725         bcm_sf2_intr_disable(priv);
 726
 727         /* Disable all ports physically present including the IMP
 728          * port, the other ones have already been disabled during
 729          * bcm_sf2_sw_setup
 730          */
 731         for (port = 0; port < DSA_MAX_PORTS; port++) {
 732                 if ((1 << port) & ds->enabled_port_mask ||
 733                     dsa_is_cpu_port(ds, port))
 734                         bcm_sf2_port_disable(ds, port, NULL);
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
 741 {
 742         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 743         unsigned int port;
 744         int ret;
 745
 746         ret = bcm_sf2_sw_rst(priv);
 747         if (ret) {
 748                 pr_err("%s: failed to software reset switch\n", __func__);
 749                 return ret;
 750         }
 751
 752         if (priv->hw_params.num_gphy == 1)
 753                 bcm_sf2_gphy_enable_set(ds, true);
 754
 755         for (port = 0; port < DSA_MAX_PORTS; port++) {
 756                 if ((1 << port) & ds->enabled_port_mask)
 757                         bcm_sf2_port_setup(ds, port, NULL);
 758                 else if (dsa_is_cpu_port(ds, port))
 759                         bcm_sf2_imp_setup(ds, port);
 760         }
 761
 762         return 0;
 763 }
 764
 765 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
 766                                struct ethtool_wolinfo *wol)
 767 {
 768         struct net_device *p = ds->dst[ds->index].master_netdev;
 769         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 770         struct ethtool_wolinfo pwol;
 771
 772         /* Get the parent device WoL settings */
 773         p->ethtool_ops->get_wol(p, &pwol);
 774
 775         /* Advertise the parent device supported settings */
 776         wol->supported = pwol.supported;
 777         memset(&wol->sopass, 0, sizeof(wol->sopass));
 778
 779         if (pwol.wolopts & WAKE_MAGICSECURE)
 780                 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
 781
 782         if (priv->wol_ports_mask & (1 << port))
 783                 wol->wolopts = pwol.wolopts;
 784         else
 785                 wol->wolopts = 0;
 786 }
 787
 788 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
 789                               struct ethtool_wolinfo *wol)
 790 {
 791         struct net_device *p = ds->dst[ds->index].master_netdev;
 792         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 793         s8 cpu_port = ds->dst[ds->index].cpu_port;
 794         struct ethtool_wolinfo pwol;
 795
 796         p->ethtool_ops->get_wol(p, &pwol);
 797         if (wol->wolopts & ~pwol.supported)
 798                 return -EINVAL;
 799
 800         if (wol->wolopts)
 801                 priv->wol_ports_mask |= (1 << port);
 802         else
 803                 priv->wol_ports_mask &= ~(1 << port);
 804
 805         /* If we have at least one port enabled, make sure the CPU port
 806          * is also enabled. If the CPU port is the last one enabled, we disable
 807          * it since this configuration does not make sense.
 808          */
 809         if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
 810                 priv->wol_ports_mask |= (1 << cpu_port);
 811         else
 812                 priv->wol_ports_mask &= ~(1 << cpu_port);
 813
 814         return p->ethtool_ops->set_wol(p, wol);
 815 }
 816
 817 static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
 818 {
 819         unsigned int timeout = 10;
 820         u32 reg;
 821
 822         do {
 823                 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
 824                 if (!(reg & ARLA_VTBL_STDN))
 825                         return 0;
 826
 827                 usleep_range(1000, 2000);
 828         } while (timeout--);
 829
 830         return -ETIMEDOUT;
 831 }
 832
 833 static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
 834 {
 835         core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
 836
 837         return bcm_sf2_vlan_op_wait(priv);
 838 }
 839
 840 static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
 841 {
 842         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 843         unsigned int port;
 844
 845         /* Clear all VLANs */
 846         bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
 847
 848         for (port = 0; port < priv->hw_params.num_ports; port++) {
 849                 if (!((1 << port) & ds->enabled_port_mask))
 850                         continue;
 851
 852                 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
 853         }
 854 }
 855
 856 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
 857 {
 858         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 859         unsigned int port;
 860
 861         /* Enable all valid ports and disable those unused */
 862         for (port = 0; port < priv->hw_params.num_ports; port++) {
 863                 /* IMP port receives special treatment */
 864                 if ((1 << port) & ds->enabled_port_mask)
 865                         bcm_sf2_port_setup(ds, port, NULL);
 866                 else if (dsa_is_cpu_port(ds, port))
 867                         bcm_sf2_imp_setup(ds, port);
 868                 else
 869                         bcm_sf2_port_disable(ds, port, NULL);
 870         }
 871
 872         bcm_sf2_sw_configure_vlan(ds);
 873
 874         return 0;
 875 }
 876
 877 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
 878  * register basis so we need to translate that into an address that the
 879  * bus-glue understands.
 880  */
 881 #define SF2_PAGE_REG_MKADDR(page, reg)  ((page) << 10 | (reg) << 2)
 882
 883 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
 884                               u8 *val)
 885 {
 886         struct bcm_sf2_priv *priv = dev->priv;
 887
 888         *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
 889
 890         return 0;
 891 }
 892
 893 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
 894                                u16 *val)
 895 {
 896         struct bcm_sf2_priv *priv = dev->priv;
 897
 898         *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
 899
 900         return 0;
 901 }
 902
 903 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
 904                                u32 *val)
 905 {
 906         struct bcm_sf2_priv *priv = dev->priv;
 907
 908         *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
 909
 910         return 0;
 911 }
 912
 913 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
 914                                u64 *val)
 915 {
 916         struct bcm_sf2_priv *priv = dev->priv;
 917
 918         *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
 919
 920         return 0;
 921 }
 922
 923 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
 924                                u8 value)
 925 {
 926         struct bcm_sf2_priv *priv = dev->priv;
 927
 928         core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
 929
 930         return 0;
 931 }
 932
 933 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
 934                                 u16 value)
 935 {
 936         struct bcm_sf2_priv *priv = dev->priv;
 937
 938         core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
 939
 940         return 0;
 941 }
 942
 943 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
 944                                 u32 value)
 945 {
 946         struct bcm_sf2_priv *priv = dev->priv;
 947
 948         core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
 949
 950         return 0;
 951 }
 952
 953 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
 954                                 u64 value)
 955 {
 956         struct bcm_sf2_priv *priv = dev->priv;
 957
 958         core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
 959
 960         return 0;
 961 }
 962
 963 static struct b53_io_ops bcm_sf2_io_ops = {
 964         .read8  = bcm_sf2_core_read8,
 965         .read16 = bcm_sf2_core_read16,
 966         .read32 = bcm_sf2_core_read32,
 967         .read48 = bcm_sf2_core_read64,
 968         .read64 = bcm_sf2_core_read64,
 969         .write8 = bcm_sf2_core_write8,
 970         .write16 = bcm_sf2_core_write16,
 971         .write32 = bcm_sf2_core_write32,
 972         .write48 = bcm_sf2_core_write64,
 973         .write64 = bcm_sf2_core_write64,
 974 };
 975
 976 static int bcm_sf2_sw_probe(struct platform_device *pdev)
 977 {
 978         const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
 979         struct device_node *dn = pdev->dev.of_node;
 980         struct b53_platform_data *pdata;
 981         struct bcm_sf2_priv *priv;
 982         struct b53_device *dev;
 983         struct dsa_switch *ds;
 984         void __iomem **base;
 985         struct resource *r;
 986         unsigned int i;
 987         u32 reg, rev;
 988         int ret;
 989
 990         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 991         if (!priv)
 992                 return -ENOMEM;
 993
 994         dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
 995         if (!dev)
 996                 return -ENOMEM;
 997
 998         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 999         if (!pdata)
1000                 return -ENOMEM;
1001
1002         /* Auto-detection using standard registers will not work, so
1003          * provide an indication of what kind of device we are for
1004          * b53_common to work with
1005          */
1006         pdata->chip_id = BCM7445_DEVICE_ID;
1007         dev->pdata = pdata;
1008
1009         priv->dev = dev;
1010         ds = dev->ds;
1011
1012         /* Override the parts that are non-standard wrt. normal b53 devices */
1013         ds->ops->get_tag_protocol = bcm_sf2_sw_get_tag_protocol;
1014         ds->ops->setup = bcm_sf2_sw_setup;
1015         ds->ops->get_phy_flags = bcm_sf2_sw_get_phy_flags;
1016         ds->ops->adjust_link = bcm_sf2_sw_adjust_link;
1017         ds->ops->fixed_link_update = bcm_sf2_sw_fixed_link_update;
1018         ds->ops->suspend = bcm_sf2_sw_suspend;
1019         ds->ops->resume = bcm_sf2_sw_resume;
1020         ds->ops->get_wol = bcm_sf2_sw_get_wol;
1021         ds->ops->set_wol = bcm_sf2_sw_set_wol;
1022         ds->ops->port_enable = bcm_sf2_port_setup;
1023         ds->ops->port_disable = bcm_sf2_port_disable;
1024         ds->ops->get_eee = bcm_sf2_sw_get_eee;
1025         ds->ops->set_eee = bcm_sf2_sw_set_eee;
1026
1027         /* Avoid having DSA free our slave MDIO bus (checking for
1028          * ds->slave_mii_bus and ds->ops->phy_read being non-NULL)
1029          */
1030         ds->ops->phy_read = NULL;
1031
1032         dev_set_drvdata(&pdev->dev, priv);
1033
1034         spin_lock_init(&priv->indir_lock);
1035         mutex_init(&priv->stats_mutex);
1036
1037         bcm_sf2_identify_ports(priv, dn->child);
1038
1039         priv->irq0 = irq_of_parse_and_map(dn, 0);
1040         priv->irq1 = irq_of_parse_and_map(dn, 1);
1041
1042         base = &priv->core;
1043         for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1044                 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1045                 *base = devm_ioremap_resource(&pdev->dev, r);
1046                 if (IS_ERR(*base)) {
1047                         pr_err("unable to find register: %s\n", reg_names[i]);
1048                         return PTR_ERR(*base);
1049                 }
1050                 base++;
1051         }
1052
1053         ret = bcm_sf2_sw_rst(priv);
1054         if (ret) {
1055                 pr_err("unable to software reset switch: %d\n", ret);
1056                 return ret;
1057         }
1058
1059         ret = bcm_sf2_mdio_register(ds);
1060         if (ret) {
1061                 pr_err("failed to register MDIO bus\n");
1062                 return ret;
1063         }
1064
1065         /* Disable all interrupts and request them */
1066         bcm_sf2_intr_disable(priv);
1067
1068         ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1069                                "switch_0", priv);
1070         if (ret < 0) {
1071                 pr_err("failed to request switch_0 IRQ\n");
1072                 goto out_mdio;
1073         }
1074
1075         ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1076                                "switch_1", priv);
1077         if (ret < 0) {
1078                 pr_err("failed to request switch_1 IRQ\n");
1079                 goto out_mdio;
1080         }
1081
1082         /* Reset the MIB counters */
1083         reg = core_readl(priv, CORE_GMNCFGCFG);
1084         reg |= RST_MIB_CNT;
1085         core_writel(priv, reg, CORE_GMNCFGCFG);
1086         reg &= ~RST_MIB_CNT;
1087         core_writel(priv, reg, CORE_GMNCFGCFG);
1088
1089         /* Get the maximum number of ports for this switch */
1090         priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1091         if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1092                 priv->hw_params.num_ports = DSA_MAX_PORTS;
1093
1094         /* Assume a single GPHY setup if we can't read that property */
1095         if (of_property_read_u32(dn, "brcm,num-gphy",
1096                                  &priv->hw_params.num_gphy))
1097                 priv->hw_params.num_gphy = 1;
1098
1099         rev = reg_readl(priv, REG_SWITCH_REVISION);
1100         priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1101                                         SWITCH_TOP_REV_MASK;
1102         priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1103
1104         rev = reg_readl(priv, REG_PHY_REVISION);
1105         priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1106
1107         ret = b53_switch_register(dev);
1108         if (ret)
1109                 goto out_mdio;
1110
1111         pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1112                 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1113                 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1114                 priv->core, priv->irq0, priv->irq1);
1115
1116         return 0;
1117
1118 out_mdio:
1119         bcm_sf2_mdio_unregister(priv);
1120         return ret;
1121 }
1122
1123 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1124 {
1125         struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1126
1127         /* Disable all ports and interrupts */
1128         priv->wol_ports_mask = 0;
1129         bcm_sf2_sw_suspend(priv->dev->ds);
1130         dsa_unregister_switch(priv->dev->ds);
1131         bcm_sf2_mdio_unregister(priv);
1132
1133         return 0;
1134 }
1135
1136 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1137 {
1138         struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1139
1140         /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1141          * successful MDIO bus scan to occur. If we did turn off the GPHY
1142          * before (e.g: port_disable), this will also power it back on.
1143          *
1144          * Do not rely on kexec_in_progress, just power the PHY on.
1145          */
1146         if (priv->hw_params.num_gphy == 1)
1147                 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1148 }
1149
1150 #ifdef CONFIG_PM_SLEEP
1151 static int bcm_sf2_suspend(struct device *dev)
1152 {
1153         struct platform_device *pdev = to_platform_device(dev);
1154         struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1155
1156         return dsa_switch_suspend(priv->dev->ds);
1157 }
1158
1159 static int bcm_sf2_resume(struct device *dev)
1160 {
1161         struct platform_device *pdev = to_platform_device(dev);
1162         struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1163
1164         return dsa_switch_resume(priv->dev->ds);
1165 }
1166 #endif /* CONFIG_PM_SLEEP */
1167
1168 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1169                          bcm_sf2_suspend, bcm_sf2_resume);
1170
1171 static const struct of_device_id bcm_sf2_of_match[] = {
1172         { .compatible = "brcm,bcm7445-switch-v4.0" },
1173         { /* sentinel */ },
1174 };
1175 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1176
1177 static struct platform_driver bcm_sf2_driver = {
1178         .probe  = bcm_sf2_sw_probe,
1179         .remove = bcm_sf2_sw_remove,
1180         .shutdown = bcm_sf2_sw_shutdown,
1181         .driver = {
1182                 .name = "brcm-sf2",
1183                 .of_match_table = bcm_sf2_of_match,
1184                 .pm = &bcm_sf2_pm_ops,
1185         },
1186 };
1187 module_platform_driver(bcm_sf2_driver);
1188
1189 MODULE_AUTHOR("Broadcom Corporation");
1190 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1191 MODULE_LICENSE("GPL");
1192 MODULE_ALIAS("platform:brcm-sf2");