drivers/net/phy/at803x.c

   1 /*
   2  * drivers/net/phy/at803x.c
   3  *
   4  * Driver for Atheros 803x PHY
   5  *
   6  * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/phy.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/gpio/consumer.h>
  21
  22 #define AT803X_INTR_ENABLE                      0x12
  23 #define AT803X_INTR_ENABLE_AUTONEG_ERR          BIT(15)
  24 #define AT803X_INTR_ENABLE_SPEED_CHANGED        BIT(14)
  25 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED       BIT(13)
  26 #define AT803X_INTR_ENABLE_PAGE_RECEIVED        BIT(12)
  27 #define AT803X_INTR_ENABLE_LINK_FAIL            BIT(11)
  28 #define AT803X_INTR_ENABLE_LINK_SUCCESS         BIT(10)
  29 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE  BIT(5)
  30 #define AT803X_INTR_ENABLE_POLARITY_CHANGED     BIT(1)
  31 #define AT803X_INTR_ENABLE_WOL                  BIT(0)
  32
  33 #define AT803X_INTR_STATUS                      0x13
  34
  35 #define AT803X_SMART_SPEED                      0x14
  36 #define AT803X_LED_CONTROL                      0x18
  37
  38 #define AT803X_DEVICE_ADDR                      0x03
  39 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET         0x804C
  40 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET        0x804B
  41 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET        0x804A
  42 #define AT803X_MMD_ACCESS_CONTROL               0x0D
  43 #define AT803X_MMD_ACCESS_CONTROL_DATA          0x0E
  44 #define AT803X_FUNC_DATA                        0x4003
  45 #define AT803X_REG_CHIP_CONFIG                  0x1f
  46 #define AT803X_BT_BX_REG_SEL                    0x8000
  47
  48 #define AT803X_DEBUG_ADDR                       0x1D
  49 #define AT803X_DEBUG_DATA                       0x1E
  50
  51 #define AT803X_MODE_CFG_MASK                    0x0F
  52 #define AT803X_MODE_CFG_SGMII                   0x01
  53
  54 #define AT803X_PSSR                     0x11    /*PHY-Specific Status Register*/
  55 #define AT803X_PSSR_MR_AN_COMPLETE      0x0200
  56
  57 #define AT803X_DEBUG_REG_0                      0x00
  58 #define AT803X_DEBUG_RX_CLK_DLY_EN              BIT(15)
  59
  60 #define AT803X_DEBUG_REG_5                      0x05
  61 #define AT803X_DEBUG_TX_CLK_DLY_EN              BIT(8)
  62
  63 #define ATH8030_PHY_ID 0x004dd076
  64 #define ATH8031_PHY_ID 0x004dd074
  65 #define ATH8035_PHY_ID 0x004dd072
  66
  67 MODULE_DESCRIPTION("Atheros 803x PHY driver");
  68 MODULE_AUTHOR("Matus Ujhelyi");
  69 MODULE_LICENSE("GPL");
  70
  71 struct at803x_priv {
  72         bool phy_reset:1;
  73         struct gpio_desc *gpiod_reset;
  74 };
  75
  76 struct at803x_context {
  77         u16 bmcr;
  78         u16 advertise;
  79         u16 control1000;
  80         u16 int_enable;
  81         u16 smart_speed;
  82         u16 led_control;
  83 };
  84
  85 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
  86 {
  87         int ret;
  88
  89         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
  90         if (ret < 0)
  91                 return ret;
  92
  93         return phy_read(phydev, AT803X_DEBUG_DATA);
  94 }
  95
  96 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
  97                                  u16 clear, u16 set)
  98 {
  99         u16 val;
 100         int ret;
 101
 102         ret = at803x_debug_reg_read(phydev, reg);
 103         if (ret < 0)
 104                 return ret;
 105
 106         val = ret & 0xffff;
 107         val &= ~clear;
 108         val |= set;
 109
 110         return phy_write(phydev, AT803X_DEBUG_DATA, val);
 111 }
 112
 113 static inline int at803x_enable_rx_delay(struct phy_device *phydev)
 114 {
 115         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
 116                                         AT803X_DEBUG_RX_CLK_DLY_EN);
 117 }
 118
 119 static inline int at803x_enable_tx_delay(struct phy_device *phydev)
 120 {
 121         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
 122                                         AT803X_DEBUG_TX_CLK_DLY_EN);
 123 }
 124
 125 /* save relevant PHY registers to private copy */
 126 static void at803x_context_save(struct phy_device *phydev,
 127                                 struct at803x_context *context)
 128 {
 129         context->bmcr = phy_read(phydev, MII_BMCR);
 130         context->advertise = phy_read(phydev, MII_ADVERTISE);
 131         context->control1000 = phy_read(phydev, MII_CTRL1000);
 132         context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
 133         context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
 134         context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
 135 }
 136
 137 /* restore relevant PHY registers from private copy */
 138 static void at803x_context_restore(struct phy_device *phydev,
 139                                    const struct at803x_context *context)
 140 {
 141         phy_write(phydev, MII_BMCR, context->bmcr);
 142         phy_write(phydev, MII_ADVERTISE, context->advertise);
 143         phy_write(phydev, MII_CTRL1000, context->control1000);
 144         phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
 145         phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
 146         phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
 147 }
 148
 149 static int at803x_set_wol(struct phy_device *phydev,
 150                           struct ethtool_wolinfo *wol)
 151 {
 152         struct net_device *ndev = phydev->attached_dev;
 153         const u8 *mac;
 154         int ret;
 155         u32 value;
 156         unsigned int i, offsets[] = {
 157                 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
 158                 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
 159                 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
 160         };
 161
 162         if (!ndev)
 163                 return -ENODEV;
 164
 165         if (wol->wolopts & WAKE_MAGIC) {
 166                 mac = (const u8 *) ndev->dev_addr;
 167
 168                 if (!is_valid_ether_addr(mac))
 169                         return -EFAULT;
 170
 171                 for (i = 0; i < 3; i++) {
 172                         phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
 173                                   AT803X_DEVICE_ADDR);
 174                         phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
 175                                   offsets[i]);
 176                         phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
 177                                   AT803X_FUNC_DATA);
 178                         phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
 179                                   mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
 180                 }
 181
 182                 value = phy_read(phydev, AT803X_INTR_ENABLE);
 183                 value |= AT803X_INTR_ENABLE_WOL;
 184                 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
 185                 if (ret)
 186                         return ret;
 187                 value = phy_read(phydev, AT803X_INTR_STATUS);
 188         } else {
 189                 value = phy_read(phydev, AT803X_INTR_ENABLE);
 190                 value &= (~AT803X_INTR_ENABLE_WOL);
 191                 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
 192                 if (ret)
 193                         return ret;
 194                 value = phy_read(phydev, AT803X_INTR_STATUS);
 195         }
 196
 197         return ret;
 198 }
 199
 200 static void at803x_get_wol(struct phy_device *phydev,
 201                            struct ethtool_wolinfo *wol)
 202 {
 203         u32 value;
 204
 205         wol->supported = WAKE_MAGIC;
 206         wol->wolopts = 0;
 207
 208         value = phy_read(phydev, AT803X_INTR_ENABLE);
 209         if (value & AT803X_INTR_ENABLE_WOL)
 210                 wol->wolopts |= WAKE_MAGIC;
 211 }
 212
 213 static int at803x_suspend(struct phy_device *phydev)
 214 {
 215         int value;
 216         int wol_enabled;
 217
 218         mutex_lock(&phydev->lock);
 219
 220         value = phy_read(phydev, AT803X_INTR_ENABLE);
 221         wol_enabled = value & AT803X_INTR_ENABLE_WOL;
 222
 223         value = phy_read(phydev, MII_BMCR);
 224
 225         if (wol_enabled)
 226                 value |= BMCR_ISOLATE;
 227         else
 228                 value |= BMCR_PDOWN;
 229
 230         phy_write(phydev, MII_BMCR, value);
 231
 232         mutex_unlock(&phydev->lock);
 233
 234         return 0;
 235 }
 236
 237 static int at803x_resume(struct phy_device *phydev)
 238 {
 239         int value;
 240
 241         mutex_lock(&phydev->lock);
 242
 243         value = phy_read(phydev, MII_BMCR);
 244         value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
 245         phy_write(phydev, MII_BMCR, value);
 246
 247         mutex_unlock(&phydev->lock);
 248
 249         return 0;
 250 }
 251
 252 static int at803x_probe(struct phy_device *phydev)
 253 {
 254         struct device *dev = &phydev->mdio.dev;
 255         struct at803x_priv *priv;
 256         struct gpio_desc *gpiod_reset;
 257
 258         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 259         if (!priv)
 260                 return -ENOMEM;
 261
 262         if (phydev->drv->phy_id != ATH8030_PHY_ID)
 263                 goto does_not_require_reset_workaround;
 264
 265         gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
 266         if (IS_ERR(gpiod_reset))
 267                 return PTR_ERR(gpiod_reset);
 268
 269         priv->gpiod_reset = gpiod_reset;
 270
 271 does_not_require_reset_workaround:
 272         phydev->priv = priv;
 273
 274         return 0;
 275 }
 276
 277 static int at803x_config_init(struct phy_device *phydev)
 278 {
 279         int ret;
 280
 281         ret = genphy_config_init(phydev);
 282         if (ret < 0)
 283                 return ret;
 284
 285         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
 286                         phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 287                 ret = at803x_enable_rx_delay(phydev);
 288                 if (ret < 0)
 289                         return ret;
 290         }
 291
 292         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 293                         phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 294                 ret = at803x_enable_tx_delay(phydev);
 295                 if (ret < 0)
 296                         return ret;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int at803x_ack_interrupt(struct phy_device *phydev)
 303 {
 304         int err;
 305
 306         err = phy_read(phydev, AT803X_INTR_STATUS);
 307
 308         return (err < 0) ? err : 0;
 309 }
 310
 311 static int at803x_config_intr(struct phy_device *phydev)
 312 {
 313         int err;
 314         int value;
 315
 316         value = phy_read(phydev, AT803X_INTR_ENABLE);
 317
 318         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 319                 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
 320                 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
 321                 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
 322                 value |= AT803X_INTR_ENABLE_LINK_FAIL;
 323                 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
 324
 325                 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
 326         }
 327         else
 328                 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
 329
 330         return err;
 331 }
 332
 333 static void at803x_link_change_notify(struct phy_device *phydev)
 334 {
 335         struct at803x_priv *priv = phydev->priv;
 336
 337         /*
 338          * Conduct a hardware reset for AT8030 every time a link loss is
 339          * signalled. This is necessary to circumvent a hardware bug that
 340          * occurs when the cable is unplugged while TX packets are pending
 341          * in the FIFO. In such cases, the FIFO enters an error mode it
 342          * cannot recover from by software.
 343          */
 344         if (phydev->state == PHY_NOLINK) {
 345                 if (priv->gpiod_reset && !priv->phy_reset) {
 346                         struct at803x_context context;
 347
 348                         at803x_context_save(phydev, &context);
 349
 350                         gpiod_set_value(priv->gpiod_reset, 1);
 351                         msleep(1);
 352                         gpiod_set_value(priv->gpiod_reset, 0);
 353                         msleep(1);
 354
 355                         at803x_context_restore(phydev, &context);
 356
 357                         phydev_dbg(phydev, "%s(): phy was reset\n",
 358                                    __func__);
 359                         priv->phy_reset = true;
 360                 }
 361         } else {
 362                 priv->phy_reset = false;
 363         }
 364 }
 365
 366 static int at803x_aneg_done(struct phy_device *phydev)
 367 {
 368         int ccr;
 369
 370         int aneg_done = genphy_aneg_done(phydev);
 371         if (aneg_done != BMSR_ANEGCOMPLETE)
 372                 return aneg_done;
 373
 374         /*
 375          * in SGMII mode, if copper side autoneg is successful,
 376          * also check SGMII side autoneg result
 377          */
 378         ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 379         if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
 380                 return aneg_done;
 381
 382         /* switch to SGMII/fiber page */
 383         phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
 384
 385         /* check if the SGMII link is OK. */
 386         if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
 387                 pr_warn("803x_aneg_done: SGMII link is not ok\n");
 388                 aneg_done = 0;
 389         }
 390         /* switch back to copper page */
 391         phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
 392
 393         return aneg_done;
 394 }
 395
 396 static struct phy_driver at803x_driver[] = {
 397 {
 398         /* ATHEROS 8035 */
 399         .phy_id                 = ATH8035_PHY_ID,
 400         .name                   = "Atheros 8035 ethernet",
 401         .phy_id_mask            = 0xffffffef,
 402         .probe                  = at803x_probe,
 403         .config_init            = at803x_config_init,
 404         .set_wol                = at803x_set_wol,
 405         .get_wol                = at803x_get_wol,
 406         .suspend                = at803x_suspend,
 407         .resume                 = at803x_resume,
 408         .features               = PHY_GBIT_FEATURES,
 409         .flags                  = PHY_HAS_INTERRUPT,
 410         .config_aneg            = genphy_config_aneg,
 411         .read_status            = genphy_read_status,
 412         .ack_interrupt          = at803x_ack_interrupt,
 413         .config_intr            = at803x_config_intr,
 414 }, {
 415         /* ATHEROS 8030 */
 416         .phy_id                 = ATH8030_PHY_ID,
 417         .name                   = "Atheros 8030 ethernet",
 418         .phy_id_mask            = 0xffffffef,
 419         .probe                  = at803x_probe,
 420         .config_init            = at803x_config_init,
 421         .link_change_notify     = at803x_link_change_notify,
 422         .set_wol                = at803x_set_wol,
 423         .get_wol                = at803x_get_wol,
 424         .suspend                = at803x_suspend,
 425         .resume                 = at803x_resume,
 426         .features               = PHY_BASIC_FEATURES,
 427         .flags                  = PHY_HAS_INTERRUPT,
 428         .config_aneg            = genphy_config_aneg,
 429         .read_status            = genphy_read_status,
 430         .ack_interrupt          = at803x_ack_interrupt,
 431         .config_intr            = at803x_config_intr,
 432 }, {
 433         /* ATHEROS 8031 */
 434         .phy_id                 = ATH8031_PHY_ID,
 435         .name                   = "Atheros 8031 ethernet",
 436         .phy_id_mask            = 0xffffffef,
 437         .probe                  = at803x_probe,
 438         .config_init            = at803x_config_init,
 439         .set_wol                = at803x_set_wol,
 440         .get_wol                = at803x_get_wol,
 441         .suspend                = at803x_suspend,
 442         .resume                 = at803x_resume,
 443         .features               = PHY_GBIT_FEATURES,
 444         .flags                  = PHY_HAS_INTERRUPT,
 445         .config_aneg            = genphy_config_aneg,
 446         .read_status            = genphy_read_status,
 447         .aneg_done              = at803x_aneg_done,
 448         .ack_interrupt          = &at803x_ack_interrupt,
 449         .config_intr            = &at803x_config_intr,
 450 } };
 451
 452 module_phy_driver(at803x_driver);
 453
 454 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
 455         { ATH8030_PHY_ID, 0xffffffef },
 456         { ATH8031_PHY_ID, 0xffffffef },
 457         { ATH8035_PHY_ID, 0xffffffef },
 458         { }
 459 };
 460
 461 MODULE_DEVICE_TABLE(mdio, atheros_tbl);