| blob | d71b4b2c077daa410a53951893229ecbac59a892 |
1 * Clock bindings for Freescale i.MX5
3 Required properties:
4 - compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
5 - reg: Address and length of the register set
6 - interrupts: Should contain CCM interrupt
7 - #clock-cells: Should be <1>
9 The clock consumer should specify the desired clock by having the clock
10 ID in its "clocks" phandle cell. The following is a full list of i.MX5
11 clocks and IDs.
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 osc 2
18 ckih1 3
19 ckih2 4
20 ahb 5
21 ipg 6
22 axi_a 7
23 axi_b 8
24 uart_pred 9
25 uart_root 10
26 esdhc_a_pred 11
27 esdhc_b_pred 12
28 esdhc_c_s 13
29 esdhc_d_s 14
30 emi_sel 15
31 emi_slow_podf 16
32 nfc_podf 17
33 ecspi_pred 18
34 ecspi_podf 19
35 usboh3_pred 20
36 usboh3_podf 21
37 usb_phy_pred 22
38 usb_phy_podf 23
39 cpu_podf 24
40 di_pred 25
41 tve_s 27
42 uart1_ipg_gate 28
43 uart1_per_gate 29
44 uart2_ipg_gate 30
45 uart2_per_gate 31
46 uart3_ipg_gate 32
47 uart3_per_gate 33
48 i2c1_gate 34
49 i2c2_gate 35
50 gpt_ipg_gate 36
51 pwm1_ipg_gate 37
52 pwm1_hf_gate 38
53 pwm2_ipg_gate 39
54 pwm2_hf_gate 40
55 gpt_hf_gate 41
56 fec_gate 42
57 usboh3_per_gate 43
58 esdhc1_ipg_gate 44
59 esdhc2_ipg_gate 45
60 esdhc3_ipg_gate 46
61 esdhc4_ipg_gate 47
62 ssi1_ipg_gate 48
63 ssi2_ipg_gate 49
64 ssi3_ipg_gate 50
65 ecspi1_ipg_gate 51
66 ecspi1_per_gate 52
67 ecspi2_ipg_gate 53
68 ecspi2_per_gate 54
69 cspi_ipg_gate 55
70 sdma_gate 56
71 emi_slow_gate 57
72 ipu_s 58
73 ipu_gate 59
74 nfc_gate 60
75 ipu_di1_gate 61
76 vpu_s 62
77 vpu_gate 63
78 vpu_reference_gate 64
79 uart4_ipg_gate 65
80 uart4_per_gate 66
81 uart5_ipg_gate 67
82 uart5_per_gate 68
83 tve_gate 69
84 tve_pred 70
85 esdhc1_per_gate 71
86 esdhc2_per_gate 72
87 esdhc3_per_gate 73
88 esdhc4_per_gate 74
89 usb_phy_gate 75
90 hsi2c_gate 76
91 mipi_hsc1_gate 77
92 mipi_hsc2_gate 78
93 mipi_esc_gate 79
94 mipi_hsp_gate 80
95 ldb_di1_div_3_5 81
96 ldb_di1_div 82
97 ldb_di0_div_3_5 83
98 ldb_di0_div 84
99 ldb_di1_gate 85
100 can2_serial_gate 86
101 can2_ipg_gate 87
102 i2c3_gate 88
103 lp_apm 89
104 periph_apm 90
105 main_bus 91
106 ahb_max 92
107 aips_tz1 93
108 aips_tz2 94
109 tmax1 95
110 tmax2 96
111 tmax3 97
112 spba 98
113 uart_sel 99
114 esdhc_a_sel 100
115 esdhc_b_sel 101
116 esdhc_a_podf 102
117 esdhc_b_podf 103
118 ecspi_sel 104
119 usboh3_sel 105
120 usb_phy_sel 106
121 iim_gate 107
122 usboh3_gate 108
123 emi_fast_gate 109
124 ipu_di0_gate 110
125 gpc_dvfs 111
126 pll1_sw 112
127 pll2_sw 113
128 pll3_sw 114
129 ipu_di0_sel 115
130 ipu_di1_sel 116
131 tve_ext_sel 117
132 mx51_mipi 118
133 pll4_sw 119
134 ldb_di1_sel 120
135 di_pll4_podf 121
136 ldb_di0_sel 122
137 ldb_di0_gate 123
138 usb_phy1_gate 124
139 usb_phy2_gate 125
140 per_lp_apm 126
141 per_pred1 127
142 per_pred2 128
143 per_podf 129
144 per_root 130
145 ssi_apm 131
146 ssi1_root_sel 132
147 ssi2_root_sel 133
148 ssi3_root_sel 134
149 ssi_ext1_sel 135
150 ssi_ext2_sel 136
151 ssi_ext1_com_sel 137
152 ssi_ext2_com_sel 138
153 ssi1_root_pred 139
154 ssi1_root_podf 140
155 ssi2_root_pred 141
156 ssi2_root_podf 142
157 ssi_ext1_pred 143
158 ssi_ext1_podf 144
159 ssi_ext2_pred 145
160 ssi_ext2_podf 146
161 ssi1_root_gate 147
162 ssi2_root_gate 148
163 ssi3_root_gate 149
164 ssi_ext1_gate 150
165 ssi_ext2_gate 151
166 epit1_ipg_gate 152
167 epit1_hf_gate 153
168 epit2_ipg_gate 154
169 epit2_hf_gate 155
170 can_sel 156
171 can1_serial_gate 157
172 can1_ipg_gate 158
173 owire_gate 159
174 gpu3d_s 160
175 gpu2d_s 161
176 gpu3d_gate 162
177 gpu2d_gate 163
178 garb_gate 164
179 cko1_sel 165
180 cko1_podf 166
181 cko1 167
182 cko2_sel 168
183 cko2_podf 169
184 cko2 170
185 srtc_gate 171
186 pata_gate 172
188 Examples (for mx53):
190 clks: ccm@53fd4000{
191 compatible = "fsl,imx53-ccm";
192 reg = <0x53fd4000 0x4000>;
193 interrupts = <0 71 0x04 0 72 0x04>;
194 #clock-cells = <1>;
195 };
197 can1: can@53fc8000 {
198 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
199 reg = <0x53fc8000 0x4000>;
200 interrupts = <82>;
201 clocks = <&clks 158>, <&clks 157>;
202 clock-names = "ipg", "per";
203 status = "disabled";
204 };